A

LABORATORY REPORT
Submitted to

EMBEDDED APPLICATION LAB

in partial fulfilment of the requirements

for the second semester course work

Of

MASTER OF TECHNOLOGY
in

EMBEDDED SYSTEM DESIGN

By

Teekam Chand Khandelwal

(ROLL NO. -31911117)

DEPARTMENT OF VLSI & EMBEDDED SYSTEM DESIGN

NATIONAL INSTITUTE OF TECHNOLOGY

(INSTITUTE OF NATIONAL IMPORTANCE)

KURUKSHETRA–136119.

HARYANA

2019 – 2020

1
 NATIONAL INSTITUTE OF TECHNOLOGY
(INSTITUTE OF NATIONAL IMPORTANCE)

KURUKSHETRA-136119

HARYANA

CERTIFICATE
This is to certify that Teekam Chand Khandelwal studying M.Tech in Embedded System
Design bearing the Roll No. 31911117 has successfully completed 2 modules during the
academic year 2019-20 in the subject Embedded Application Lab.

Lab Supervisor:-
Dr. R.K.Sharma

Professor
Department of ECE

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 INDEX

S. NO NAME OF EXPERIMENTS PAGE REMARK

NO.

1. Implementation of LMS based noise filter on FPGA for

audio processing system. 4-23

2. Real Time Video Processing on FPGA using SOBEL EDGE 24-37

DETECTION ALGORITHM

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 EXPERIMENT NO. 1

AIM: Implementation of LMS based noise filter on FPGA for

audio processing system.

Hardware:
❖ Zybo-Zynq board
❖ Micro-USB cable
❖ Headphones or speakers
❖ Audio input device

Software:
❖ Vivado Design suit 2018.1
• Newer/older version can be used, but the procedure may vary slightly
• Digilent board support files for vivado

To download board file click on link given below

https://reference.digilentinc.com/learn/software/tutorials/vivado-board-
files/start?redirect=1

Flow Chart

Figure: Flow chart of Audio Processing usimg LMS filter

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Theory
Zynq- Board
Xilinx providing 7 devices in Zynq family – Z-7010, Z-7015, Z-7020, Z-7030, Z-7040, Z-
7100. ARM cortex-A9 is presented in all devices. The first three devices provide FPGA
fabric is Artix-7 and clock frequency up to 866MHz. Other three devices have Kintex-7
and clock frequency up to 1GHz.The FPGA fabrics having different quantity of resources
(like-logic cells, block RAMs, DSP slices and I/O pins etc.) in each device.
Zynq Architecture
The Zynq device is mainly contains two parts - (1) Programmable Logic (2) Processing
System
Programmable Logic is used for the FPGA fabrics and HW development. Processing
System is used for processor and SW development. Both parts are interface through AXI
interface .

Zynq

Figure: Zynq basic Architecture

Development Tools
All Zynq projects are developed on Xilinx Vivado Suite. For this project following tools
is used
Vivado IDE
The IDE is used for creating the HW base system. All features of the HW system are
controlled here: PS configuration, IP cores, external connections etc. The HW system can
be created using block design. The HW design can be exported from Vivado IDE to
Vivado SDK.
Vivado SDK
It is used for software design suite for the PS SW development. The programming
language supported by Vivado SDK is C and C++. It contains GCC compiler and drivers
for all Xilinx IP blocks.

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The Vivado SDK is also launched from Vivado IDE for project to build SW application
that will be run on PS.

Zynq Design Flow

Any project starts with the requirements and specifications which includes features like
– functionality, target device and performance criteria etc.

Figure: Zynq Design flow

Least Mean Square Filter

Least mean square Filter LMS filter uses a algorithm which is a noise cancellation
algorithm and was developed by Bernard Widrow, a professor at Stanford University in
1960.His first PhD student Ted Hoff gave equal contribution in his work. It uses
continuous adaption process to remove the noise efficiently and precisely from the system
by using updated weight, Vector (W) in all iteration until error signal becomes zero.

Figure: LMS filter

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Required IPs
❖ LMS Filter
❖ LED controller
❖ NCO
❖ GPIO
❖ ZYNQ Processing system
❖ Processor System Reset
❖ ZYNQ audio controller
❖ AXI interconnect

Procedure for adding IPs in Vivado

Open vivado and follow the procedure as given below

Open Vivado->Create New project->Project Name->select RTL project->target language

VHDL+ simulator language mixed

Select board->ZYBO->next->Finish

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IP Catalog->add repository->ok

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Click on Create Block design->ok

Add IP->led_controller_v1.0->double click

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Add IP->nco->double click

Add IP->lms_pcore_v1_0->double click

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Led_controller_0->click on LEDs_out[3:0]->click external

Add IP->ZYNQ7 Processinsystem>doubl click

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Click on Run block Automation->ok

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Click on Run connection automation->click on all automation->ok

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Connect (if not connected) lms_pcore_0 (pcore_clk to axi4_lite_aCLK) and lms_pcore_0
(p_core_resetn to nco_0 (ap_rst_n))

Add IP->zybo_audio_ctrl->double click

Run connection automation->ok

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Make external Zybo_audio_ctrl_0 pin (BCLK, PBLRCLK, RECLRCLK, PBDATA)

For make external, click on BLCLK->Right click->make external same follow for
(PBLRCLK, RECLRCLK, and PBDATA)

Double click on ZYNQ processing system

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Click on clock Configuration->PL fabric clocks->check on FCLK_CLK1->DDR PLL->12.288

MIO configuration->I/O peripherals-> enable (I2C0)->EMI0->OK

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Make external pin IIC_0 and FCLK_clk1

Add ip ->AXI_GPIO->double click

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RUN auto connection->click on S_AXI->OK

Double click on AXI_GPIO->IP configuration->gpio width->1->ok

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Make external AXI_GPIO_0

ADD IP->AXI GPIO->Double click->RUN connection automation->S_AXI->OK Double click

on AXI gpio_1->IP configuration->check on Enable dual channel->ok

Run connection automation->GPIO(BTNS_4bit)->GPIO2(SWS_4bits)->ok

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20
Address Editor (edit range as shown below)

Validate design (F6) ->Sources->design_1->right click->create HDL wrapper->ok

Run synthesis

ADD source->add constraints file->zybo->adventures_with ip integrator->constraints-

>adventures_with_ip.xdc-> ok->finish

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Generate bit stream->File->export hardware->File->launch SDK->OK Application project-
>project_ name->next->empty application->finish Right click on ‘LMS Filter’->import->file
system->next

Right click on Xilinx tools->repositories->new->ip_repo->led_controller_1_0->ok->new-

>ip_repo->nco_1_0-

>ok

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System.mss->modify the BSP’s settings->drivers->ok Project name->src->import->general-
>file system->next

Drivers->browse-
>zybo/book/sources/zybo/adventures_with_ip_integrator/drivers>lms_pcore_adder.h>audio.h-

>finish

Src->software->browse->adventures_with_ip_c->adventures_with_ip.h->audio.c-
>ip_functions_c->finish Select “lms filter” in project explorer than click on ‘built debug’

Connect the zybo board with your pc using usb cable then right click on Xilinx tool->program-
>FPGA-

>Program

Then right click on ‘LMS Filter’->run as ->launch on hardware system [debugger]

CONCLUSION:

In the FPGA, implementation of the audio processing system different input signals with a
large number of noises like sinusoidal noise etc. is sent to the programmed device. In each
combination of input and noise, the performance of the system is reliable with the noise being
effectively eliminated in each of the case. Thus, it can be concluded that LMS based Noise
filter is a effective algorithm to remove unwanted noise present in audio signals and thus be
used in Audio Processing applications.

Signature of Student: Signature of Teacher:

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 EXPERIMENT NO. 2

REAL TIME VIDEO PROCESSING ON FPGA USING SOBEL EDGE

DETECTION ALGORITHM

OBJECTIVE:
To take the video signal from video player or Camera through HDMI input and process it
(using Sobel algorithm) and send it to VGA display.

PRE REQUISITE:
• Basic knowledge in using vivado HLS, HLx software and C language.
• Basic Knowledge on Zybo Board

THEORETICAL BACKROUND:
The entry cost of application-specific integrated circuit (ASIC) design is still high
despite advancements in fabrication technologies. Depending on the product, forecasts and
ASIC design might not be viable economically. Bridging the gap between generic processor
circuits and ASICs are FPGAs, allowing the use of blank reprogrammable hardware logic
elements to implements a custom circuit. It offers a lower barrier of entry to power savings and
performance benefits of fabrication technologies without the cost of ASIC. In addition, an
algorithm optimized for FPGA implementation benefits from the inherently parallel nature of
custom circuits.

HARDWARE USED:
Digilent ZYBO Z7 Development Boards are ready-to-use embedded software and digital circuit
development boards built around the Xilinx Zynq-7000 family. The family is based on the
Xilinx All Programmable System-on-Chip (AP-SoC) architecture, which integrates a dual-core
ARM Cortex-A9 processor with the Xilinx 7 FPGA logic. The Zybo Z7 comes in a Zybo Z7-10
variant that features Xilinx XC7Z010-1CLG400C and a Zybo Z7-20 variant that features the
larger Xilinx XC7Z020-1CLG400C. The Zybo Z7-20 variant includes SDoC voucher that
provides a familiar embedded C/C++ application development experience.
The Zybo Z7 surrounds the Zynq with a set of multimedia and connectivity peripherals to create
a formidable single-board computer. The Zybo platforms are video-capable and include MIPI
CSI-2 compatible Pcam connector, HDMI input, HDMI output, and high DDR3L bandwidth

FPGA ARCHITECTURE:

Basic FPGA architecture (Figure 1) consists of thousands of fundamental elements called

configurable logic blocks (CLBs) surrounded by a system of programmable interconnects,

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called a fabric, that routes signals between CLBs. Input/output (I/ O) blocks interface
between the FPGA and external devices. An individual CLB is made up of several logic
blocks. A lookup table (LUT) is a characteristic feature of an FPGA. An LUT stores a
predefined list of logic outputs for any combination of inputs: LUTs with four to six input
bits are widely used. Standard logic functions such as multiplexers (mux), full adders (FAs)
and flip-flops are common. This simplified CLB has two modes of operation. In normal
mode, the LUTs are combined with Mux 2 to form a four-input LUT; in arithmetic mode,
the LUT outputs are fed as inputs to the FA together with a carry input from another CLB.
Mux 4 selects between the FA output and the LUT output. Mux 6 determines whether the
operation is asynchronous or synchronized to the FPGA clock via the D flip-flop.

Current-generation FPGAs include more complex CLBs capable of multiple operations

with a single block; CLBs can combine for more complex operations such as multipliers,
registers, counters and even digital signal processing (DSP) functions.

VIVADO DESIGN SUITE:

Vivado HLx

The Vivado Design Suite offers a new approach for ultra-high productivity with next generation
C/C++ and IP-based design. The new HLx editions include HL System Edition, HL Design
Edition and HL Web PACK Edition. When coupled with the new Ultra-Fast High-Level
Productivity Design Methodology Guide, users can realize a 10-15X productivity gain over
traditional approaches.

Unlike traditional RTL-based design where the majority of the design effort is spent in the
backend of the design process, C and IP based design allows for reduced development cycles in
verification, implementation and design convergence, so designers can focus on their
differentiated logic. This flow includes:

Rapid generation of the platform connectivity design, along with the necessary software stack.

Dramatically shortened verification times from high-level languages, compared to RTL.

Using high levels of abstraction, design teams can quickly get overall better or equal Quality of
Results (performance, power, utilization).

Vivado HLS

Advanced algorithms used today in wireless, medical, defense, and consumer applications are
more sophisticated than ever before. Vivado® High-Level Synthesis included as a no cost
upgrade in all Vivado HLx Editions accelerates IP creation by enabling C, C++ and System C
specifications to be directly targeted into Xilinx programmable devices without the need to

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manually create RTL. Supporting both the ISE® and Vivado design environments Vivado HLS
provides system and design architects alike with a faster path to IP creation by:

• Abstraction of algorithmic description, data type specification (integer, fixed-

point or floating-point) and interfaces (FIFO, AXI4, AXI4-Lite, AXI4-Stream)
• Extensive libraries for arbitrary precision data types, video, DSP and more… see
the below section under Libraries
• Multi-language support and the broadest language coverage in the industry
• Automatic use of Xilinx on-chip memories, DSP elements and floating-point
library

FLOW CHART:

Figure: Flow chart showing video processing using Zybo Board

PROCEDURE: In this experiment, we will decode DVI input and forwards it to the VGA output.
1. Launch Vivado from the start menu and create a new project.

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 2. Click Next to name the project and then choose a folder for Project Location Click Next
twice

3. Choose "RTL Project" for project type and make sure "Do not specify sources at this time" is
ticked. Click Next.

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4. Choose Zybo from the list and click next and then open project settings.

5. Select the IP category, ands in repository manager tab select the IP definitions and then click
OK.

6. Double-click on System Clock 16.Accept the default of instantiating a new Clocking Wizard.
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Select HDMI In and accept the default DVI to RGB converter IP.

7. Add IP for VGA I.e. RGB to VGA output. Repeat for Video In to AXI4-Stream, AXI4
Stream to Video Out, Video Timing Controller and two instances of constants.

8. Right-click the doubt interface on the xlconstant_1 block and choose "Make External" Repeat
for rgb2vga_0/vga_pRed, rgb2vga_0/vga_pGreen, rgb2vga_0/vga_pBlue, rgb2vga_0/vga_pHS
sync, rgb2vga_0/vga_pVSync . Double click the v_tc_0 block and configure it.

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9. Select clk_wiz_0 block and configure it. It should generate 200 Mhz clock from 125 MHz
onboard clock.

10 Configure the dvi2rgb_0 block as shown..

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11. Click on the external port created for xlconstant_1, named dout[0:0] by default.
On the left, under External Port Properties modify the name field to "hdmi_hpd.

12. In the same manner, rename xlconstant_0 to zero, and set its value to ‘0’. Repeat it for
xlconstant_1 block and set its value to 1.

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13. Click-and-hold on one interface and drag it to another to establish a connection. The
Regenerate Layout button on the toolbar to the left of the diagram will re- arrange the blocks
into a more readable layout.

Figure: Video Processing Block Diagram

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14. Validate the design by clicking on the corresponding button on the toolbar on the left. There
should be no errors reported 41.If there are, revisit the wiring between blocks

15. Click on add sources and the n add constraints. Then click next and add files. Browse to the
provided video.xdc.

16. Click Generate Bit stream in the Flow Navigator on the left. Save the design and confirm
that synthesis and implementation should be run. When bit stream generation is completed,
choose "Open Hardware Manager", which is also accessible in Flow Navigator

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17. Make sure the Zybo is connected to the PC via USB, it is turned on and the red PGOOD
LED is lit. Choose Open Target and Auto Connect from the Flow Navigator on the left

18. Click on Program device on the top 53.Click Program to download the bit stream file shown
there to the Zybo. The green DONE LED on the Zybo should light up

Edge detection using sobel algorithm:

The video pipeline created above provides a good basis for image processing functions. The bus
between blocks “Video In to AXI4-Stream” and “AXI4-Stream to Video Out” is a streaming
interface sending data pixel-by-pixel in raster format. While it may seem unnecessary to convert
the RGB video data to AXI-Stream then back, this step ensures the greatest interoperability
between IPs. The RGB video stream is a continuous stream of pixels forming lines interleaved
by blanking intervals. It lacks a handshake mechanism that could stop the stream for a while when
the downstream processing logic requires it. AXI-Stream transmits data more efficiently by
packing pixel data and framing signals. Furthermore, thanks to handshake signals it allows for
buffering and stopping the stream momentarily. All Xilinx Video Processing IP use AXI-Stream
interfaces, if needed these can be easily inserted into the stream. Due to the streaming nature of
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the data, different processing blocks can even be daisy- chained by attaching the output of one
to the input of another. This is called video processing pipeline. Therefore, our task is writing a
processing block that accepts an AXI-Stream RGB video input (argument), and outputs the
similarly formatted processed video data (argument).

1. Switch back to the video_pipeline project in Vivado we created above. Click Project
Settings on the left toolbar Select IP and Repository Manager Click the green plus sign
Browse to the project path For sobel edge detect ip Click Select and OK

2.Add HLS IP i.e Edge detect. click on the wire between v_vid_in_axis4s /video_out and
v_axi4s_vid_out /video_in Press the Delete key Wire video_out to stream_in of edge_detect
Wire stream_out to video_in.

3. Wire ap_clk of edge_detect to the pixel clock of the pipeline (PixelClk of dvi2rgb) Click the
plus icon next to ap_ctrl . Wire ap_start to the "one" Constant block Wire ap_rst_n to the same
"one" Constant block

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4. Generate Bitstream. Click program to download to programmable logic on the Zynq.

After applying the edge detextion algorithm, we will get the required output from the incoming
Video data as shown below:

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CONCLUSION:

The video processing using Sobel edge detection algorithm is performed for Real time video
input from HDMI cable and VGA output is observed. The edges are detected properly and
sharply

Signature of Student: Signature of Teacher:

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