SD CARD INTERFACE USING FPGA FOR MULTIMEDIA

APPLICATIONS

A PROJECT REPORT

Submitted by

SAKTHEKANNAN M S (212220060228)

UDAYA KRISHNAN M (212219060284)

YOGAVIGNES B M (212219060302)

In partial fulfilment for the award of the degree

of

BACHELOR OF ENGINEERING

in

ELECTRONICS & COMMUNICATION ENGINEERING

SAVEETHA ENGINEERING COLLEGE (AUTONMOUS)

ANNA UNIVERSITY: CHENNAI 600 025

APRIL 2023
 ANNA UNIVERSITY: CHENNAI 600 025

BONAFIDE CERTIFICATE

Certified that this report titled “SD CARD INTERFACE USING FPGA FOR
MULTIMEDIA APPLICATIONS” is the bona-fide work of “SAKHTEKANNAN M
S (212219060228), UDAYA KRISHNAN M (212219060284), YOGAVIGNES B M
(212219060302)” who carried out the work under my supervision.

SIGNATURE SIGNATURE
Dr. SRIGITHA S NATH, M.E., Ph.D Dr. SRIGITHA S NATH, M.E., Ph.D
HEAD OF THE DEPARTMENT SUPERVISOR
Professor Assistant Professor
Department of ECE, Department of ECE,
Saveetha Engineering College, Saveetha Engineering College,
Thandalam, Thandalam,
Chennai - 602105 Chennai – 602105

Submitted for the project viva-voce examination held on ________________.

INTERNAL EXAMINER EXTERNAL EXAMINER

 PROJECT APPROVAL SHEET

The project sheet “SD CARD INTERFACE USING FPGA FOR MULTIMEDIA
APPLICATIONS” submitted by “SAKTHEKANNAN M S (212219060228),
UDAYA KRISHNAN M (212219060284), and YOGAVIGNES B M
(212219060302)” is approved for submission, as partial requirement for the award of
the Degree of Bachelor of Engineering in Electronics and Communication, Anna
University during the academic year 2022-2023.

Submitted for the project viva-voce examination held on

INTERNAL EXAMINER EXTERNAL EXAMINER

 ACKNOWLEDGEMENT

If words were considered as symbols of approval and token of acknowledgement, then

let words play the heralding role of not praising and glorification but also to exhibit the
deeply embedded feelings of thanks and gratefulness.

We wish to express our gratitude to our Founder president, Dr. N.M. Veeraiyan,
President Dr. V. Saveetha and Director Dr. S. Rajesh and for providing us with the
facilities for the completion of our project. We also thank our principal
Dr.N.Duraipandian , M.E.Ph.D., for his continuous support and encouragement in
carrying out our project work. Also, our thanks to Dr. Srigitha S Nath M.E., Ph.D.,
Head of the Department, Electronics and Communication Engineering of our college for
providing us facilities and permission to carry out our project work

We mention our special thanks to our project coordinator Dr. K. Mahendran M.E.,
Ph.D., Assistant Professor, Department of Electronics and Communication Engineering
for his wisdom, guidance, and constant encouragement. We manifest cut deep sense of
gratitude to our internal guide Dr. Srigitha S Nath M.E, Ph.D., Assistant professor,
Department of Electronics and Communication Engineering for his encouragement and
faith in as though this endeavor.

We take this opportunity to acknowledge the efforts to staff members and

friends at Saveetha Engineering College for their sincere cooperation in guiding us.
Finally, we express our deepest gratitude to our family, for their constant
encouragement, support and motivation throughout under graduate career and for always
being there for us.
 TABLE OF CONTENTS

CHAPTER NO. TITLE PAGE NO.

ABSTRACT iii
LIST OF TABLE xvi
LIST OF FIGURES xviii
LIST OF SYMBOLS xxvii

1. INTRODUCTION 1

1.1 GENERAL 1
1.2 .... ......... 2
1.2.1 General 5
1.2.2 ........... 12
1.2.2.1 General 19
1.2.2.2 . . . . . . . . . . 25
1.2.2.3 . . . . . . . . . . 29
1.2.3 . . . . . . . . . . . . 30
1.3 . . . . . . . . . . .. . . . . . . 45
1.4 .................. 58
2. LITERATURE REVIEW 69
2.1 GENERAL 75
2.2 .......... 99
2.2 ……………. 100

i
 ABSTRACT

Based on FPGA (Field Programming Gate Array) chips, this application is used

for audio, video and image processing. At the same time, applications require more

memory in addition to on-chip memory to resolve additional data. Onboard memory can

be used to meet the requirements of FPGA systems but cannot be expanded by adding

just a few cards. More convenient is SD card (Secure Digitals) is a microcontroller which

can read and write to SD card. The main goal is to provide a storage solution for FPGA,

a low-cost, removable, non-volatile, flash memory, portable and easy-to-use storage

solution for FPGA for storing large files. The hardware design is done in Verilog HDL

language and implemented in FPGA. All data access from the SD card is through

Verilog, eliminating the need for an on-chip microcontroller or general-purpose

processor. Spartan 6 (XC6SLX9-3csg324) FPGA is used. The FPGA runs on 5V power

supply with a built-in oscillator frequency of 100 MHz. A 4GB micro SDHC card (class

6) from Strontium is used in this particular project. FAT32 is formatted by SD card. The

ultimate aim of this project is to read a BMP image file from the SD card. FAT32 is

formatted by SD card before interfacing. The code for the FAT32 is written to interface

the SD card.

ii
 LIST OF TABLES

TABLE NO NAME OF THE TABLE PAGE NO

1.1 PIN FUNCTIONS OF SD MODE 5

1.2 COMMANDS OF SD CARD FOR SPI MODE 6

COMPARISON OF ONE-BIT SD MODE, 4-BIT

3.1 SD MODE, SPI MODE 24

COMPARISON BETWEEN EXISTING

5.1 METHODS AND OUR METHOD 46

iii
 LIST OF FIGURES

FIGURE NO NAME OF THE FIGURE PAGE NO

1.1 BLOCK DIAGRAM OF SD CARD 3

1.2 MEMORY ARCHITECTURE OF SD CARD 4

SD CARD COMMAND RESPONSE 1 IN SPI

1.3 MODE 7

SD CARD COMMAND RESPONSE 2 IN SPI

1.4 MODE 8

SD CARD COMMAND RESPONSE 3 IN SPI

1.5 MODE 8

1.6 FPGA DEVELOPMENT BOARD 10

1.7 MOSI 11

BIT TRANSMISSIOIN IN PARALLEL

1.8 COMMUNICATION 12

BIT TRANSMISSIOIN IN SERIAL

1.9 COMMUNICATION 12

1.10 CLOCK SIGNAL 13

1.11 SLAVE SELECT ACTIVATION 13

1.12 MASTER TO SLAVE DATA TRANSFER 14

1.13 SLAVE TO MASTER DATA TRANSFER 14

3.1 SPI MODE PIN DIAGRAM 23

3.2 ONE-BIT SD MODE PIN DIAGRAM 23

3.3 FOUR-BIT SD MODE PIN DIAGRAM 24

iv
3.4 FPGA BLOCK DIAGRAM 25

3.5 SD CARD INITIALIZATION FLOW CHART 27

WRITE DATA FLOW CHART FOR SD

3.6 CARD 29

READ DATA FLOW CHART FOR SD

3.7 CARD 31

STRUCTURE OF SECTORS IN MEMORY

3.8 CARD 33

STRUCTURE OF CLUSTERS IN MEMORY

3.9 CARD 33

SCRAMBLED DATA STORAGE IN SD

3.10 CARD 34

3.11 FORMAT OF FAT32 34

PARTITION 512 BYTES – SECTOR 0 OF

3.12 SDCARD 36

PARTITION OF FIRST SECTION IN

3.13 MEMORY CORE 36

BIT VALUES OF BOOT SECTOR IN

3.14 MEMORY CORE 37

3.15 MASTER BOOT SECTOR/RECORD 38

3.16 ROOT DIRECTORY 39

STRUCTURE OF FS DIRECTORY IN SD
3.17 CARD 41

3.18 FAT32 ALGORITHM FOR READING 42

READ SCRAMBLER FILE IN FLASH

3.19 ‘MEMORY CORE’ 43

3.20 BLOCK DIAGRAM OF CODING LAYERS 43

v
IN FPGA

vi
 LIST OF SYMBOLS AND ABBREIVATIONS

LUT - Look Up Table

SD - Secure Digitals

CLK - Clock

CMD - Command

FIFO - First In First Out

SPI - Serial Peripheral Interface

I2C - Inter-Integrated Circuit

UART
- Universal Asynchronous Receiver-Transmitter

USB - Universal Serial Bus

WI-FI - Wireless Fidelity

DDR - Double Data Rate

VGA - Video Graphics Array

CPU - Central Processing Unit

PCB - Printed Circuit Board

OTP - One Time Programmable

DSP - Digital Signal Processing

1
 CHAPTER 1

INTRODUCTION

An SD (Secure Digital) card is a popular memory storage device that has

become an essential part of many electronic devices. It offers a small form
factor, high storage capacity, and fast data transfer rates, making it an ideal
choice for many applications. To use an SD card in a custom-designed
electronic system, an interface is required between the SD card and the system's
main controller. In this context, Field Programmable Gate Arrays (FPGAs)
provide a flexible and efficient solution for implementing such interfaces.
FPGAs are integrated circuits that can be programmed to perform a wide range
of digital functions. They consist of a large number of configurable logic
blocks, which can be interconnected to create custom digital circuits. This
flexibility makes FPGAs an ideal choice for implementing custom interfaces,
such as an SD card interface. An SD card interface using FPGA typically
involves implementing the SD card protocol on the FPGA, which involves
sending and receiving data to and from the card. The SD card protocol is a
complex standard that involves multiple layers of communication, including a
physical layer, a data link layer, and a file system layer. To implement the SD
card protocol on an FPGA, designers need to understand each of these layers
and how they interact with each other [1], [2], [3].

The physical layer of the SD card protocol is responsible for managing

the electrical signals between the SD card and the host system. It involves
controlling the voltage levels and timing of the signals, as well as managing the
initialization and power-up sequence of the card. To implement the physical
layer on an FPGA, designers need to understand the electrical characteristics of
the SD card interface, including the voltage levels, signal timing, and

2
impedance matching requirements. The data link layer of the SD card protocol
is responsible for managing the transfer of data between the SD card and the
host system. It involves sending and receiving commands and data packets, as
well as managing error detection and correction. To implement the data link
layer on an FPGA, designers need to understand the command and data packet
formats, as well as the error detection and correction mechanisms used by the
SD card. The file system layer of the SD card protocol is responsible for
managing the storage and retrieval of files on the SD card. It involves managing
the directory structure, file attributes, and data storage format. To implement the
file system layer on an FPGA, designers need to understand the file system
format used by the SD card, including the FAT (File Allocation Table) file
system used by most SD cards. Implementing an SD card interface using FPGA
involves designing custom digital circuits to perform each of these functions.
This typically involves writing Verilog code to describe the digital circuitry, and
then using software tools to synthesize and map the code onto the FPGA. The
resulting design can then be tested using simulation tools and debugged using
hardware debugging tools [4], [5], [6].

1.1 SD CARD
The SD card is consisting of two basic semiconductor sections, a
‘memory core’ and a ‘SD card controller’. The ‘memory core’ is the flash
memory region where the actual data of the file is saved. When we format the
SD card a file system will be written into this region. Hence this is the region
where the file system exists [7]. The ‘SD card controller’ helps to communicate
the ‘memory core’ with the external devices like FPGAs, FPGA. It can respond
to certain set of standard SD commands and read or write data from the memory
core in for the external device. Fig. 1.1 shows the block diagram of SD card.

3
 Fig. 1.1 Block Diagram of SD Card

The capacity of the ‘memory core’ is referred to as the size of the SD

card. Other than the ‘memory core’ there are certain registers associated with
the ‘SD card controller’. These registers store the status of the SD card. The
contents of these registers are read only. The SD card can be interfaced with the
FPGA using serial data bus. It can connect using ‘SD buses’ or ‘SPI bus’. The
‘SD bus’ is designed for high speed whereas the SPI bus can operate with much
lower speed only. The FPGA can read or write data the memory core and read
the registers using standard SD commands send through these serial buses [8].
Fig. 1.2 shows the memory architecture of SD card.

4
 Fig. 1.2 Memory Architecture of SD Card

1.1.1 MODE OF TRANSMISSION

SD cards can transmit in one of three ways: the serial peripheral interface
(SPI), which uses a different parallel input and output from 1-bit SD cards, as
well as 1-bit SD cards' one-time transfer type and different command and data
channels, and 4-bit SD modes, which use a wider parallel transmission bus and
have additional pins and some reset pins [9]. SD card mode provides faster and
more reliable access. In 1-bit SD mode, the maximum transfer rate is 25 Mbps,
whereas in 4-bit SD mode, the maximum transfer rate is 100 Mbps. Even if the
data transfer rate is higher in 4-bit SD transfer mode, the system's complicated
structure and timing make it challenging to build [10], [11], [12].

5
1.1.2 BUS PROTOCOL OF SD CARD
The idea behind SD communication is straightforward; it operates in a
master-slave fashion. A master controller and many slave controllers connected
through 3-6s lines are usual in such a setup. They are labelled as "CMD,"
"CLK," and "DAT0-3" (data lines). Table. 1.1 shows the pin function of SD
mode.
Table 1.1 Pin functions of SD mode.
Name Functions
CLK microcontroller uses this pin to send clock signal to SD card.
CMD bidirectional pin for information and command transmission between
microcontroller and SD card.
DAT0-3 Four bidirectional pins are used for bulk data transfer data between
microcontroller and SD card.

1.1.3 SYSTEM FILE OF SD CARD

On the SD card, a FAT16 file is divided up into four portions. File Data
Table (FDT), File Allocation Table (FAT), and Partition Boot Record (PBR) are
the three tables that make up the File System (File Directory Table). The BPB
(BIOS Parameter Record Blocks), the hard drive flag record book, the partition
boot record code section, and the end Flag 55AA are the standard components
of partitioned boot files [13], [14].

1.1.4 SD CARD COMMANDS

SD internal memory requires a total of six bytes to execute an instruction.
This consists of the one-byte command code, four bytes of command inputs,
and the checksum bits. When transferring SD card instructions, the host system
must always give 4 bytes of argument data, regardless of whether any
parameters are included in the command. In this case, the SD card will just

6
ignore the supplied value [15]. Below Table 1.2 describes the commands of SD
card and the functions of each command of the SD card.

Table 1.2 Commands of SD card for SPI mode

Commands Functions
CMD 0 Software gets reset.
CMD 1 Initialization starts.
CMD 3 Request card send back the RCA address.
CMD 7 Card entering the state.
CMD 9 Read CSD registers.
CMD 10 Read CID registers.
CMD 12 Stop reading data
CMD 16 Change of size in read/write.
CMD 17 Read command for single command.
CMD 18 Read command for multiple commands.
CMD 23 Amount of block sent.
CMD 24 Write in for single block.
CMD 25 Write in for multiple blocks.
CMD 32 Start erase block.
CMD 38 Erase the command.
CMD 55 ACMD <n> leading command.
CMD 58 Read OCR.

1.1.5 COMMAND RESPONSE

7
 In SPI mode the SD card response to all the incoming command using
three basic types of command response, R1, R2 and R3. Each bit in the response
block contains some specific details about the status of the SD card. Fig. 1.3,
Fig. 1.4, Fig. 1.5 shows the Response 1, Response 2, and Response 3 of SD card
respectively.

Response – R1

Fig. 1.3 SD card command Response 1 in SPI Mode

Response – R7
The R7 Response again is a product of the R1 response, it gives very similar
information back compared to R3. All we need to ensure is that the last byte is
equal to AA, that's it.

Response – R2

8
 Fig. 1.4 SD card command Response 2 in SPI Mode

Response – R3

Fig. 1.5 SD card command Response 3 in SPI Mode

Response R3 is available only for the 58th command (READ_OCR).

1.2 FPGA
Field Programmable Gate Arrays (FPGAs) are semiconductor devices
that are based around a matrix of configurable logic blocks (CLBs) connected
via programmable interconnects. FPGAs can be reprogrammed to desired
application or functionality requirements after manufacturing [16]. This feature
distinguishes FPGAs from Application Specific Integrated Circuits (ASICs),
which are custom manufactured for specific design tasks. Although one-time
programmable (OTP) FPGAs are available, the dominant types are SRAM
based which can be reprogrammed as the design evolves [17].

9
 The process of transforming the original system concept into an actual
FPGA implementation that performs the required task is called functional
design. A device built as an array of configurable logic elements (LE). Each
logic elements can be configured to work in combination or sequential
functions. Modern FPGAs integrate other useful things features such as built-in
multipliers and high-speed (I/O), data converters including analog to digital
converters, large RAM arrays (random access memory), and processor. All
these features allow you to create complex system-on-Chip (SoC) hardware that
provides options such as create a specific custom Central Processing Unit
(CPU), the purpose of which is executing multiple statements [18].

An existing printed circuit board (PCB) such as B. DE10 System on Chip

(SoC) and allows you to build and craft using the Hard Processor System (HPS)
implements two embedded systems in real time, each working independently or
together with its own processor (CPU). MIMAS V2 is a feature-rich and cost-
effective FPGA development board powered by Xilinx Spartan-6 FPGA.
MIMAS V2 is specifically designed for experimenting and learning system
design using FPGAs. This development board features a SPARTAN XC6SLX9
CSG324 FPGA with 512MB DDR SDRAM. A USB 2.0 interface allows quick
and easy configuration downloads to the integrated SPI flash. You don't need to
buy expensive programmers or special downloader cables to download
bitstreams to your board. Fig 3. displays the FPGA development board [19],
[20]. Fig. 1.6 shows the Mimas V2 Spartan 6 FPGA development board.

10
 Fig. 1.6 FPGA Development Board

1.2.1 FEATURES OF FPGA

 FPGA: Spartan XC6SLX9 in CSG324 package.
 DDR Memory: 166MHz 512Mb LPDDR
(MT46H32M16LF/W949D6CBHX6E).
 Flash memory: 16 Mb SPI flash memory (M25P16).
 USB 2.0 interface for On-board flash programming.
 FPGA configuration via JTAG and USB 8 LEDs, six push buttons and 8-
way DIP switch for user-defined purposes.
 VGA connector, Stereo Jack.
 Micro SD card adapter.
 Three-digit seven segment displays.
 32 IOs for user-defined purposes.
 Four 6×2 expansion connectors.
 Onboard voltage regulators for single power rail operation.

11
1.3 SPI
The Serial Peripheral Interface (SPI) is a protocol utilized by many
electrical devices. A card reader for SD or RFID cards and a wireless 2.4 GHz
transceiver are examples of peripherals that utilize SPI to connect with a
microcontroller. Sending and receiving any number of bits is possible so long as
the flow is continuous. I2C and UART both transmit data in discrete packets
with a defined number of bits. Start and stop criteria, which indicate the
beginning and end of each packet, distort data transmission [21].

Master-slave is the relationship between SPI devices. The device in

control is known as the master, while its subordinates (often sensors, displays,
or RAM) are referred to as slaves. A straightforward SPI network consists of a
single master and a single slave however a single master may supervise several
slaves. Fig. 1.7 depicts the connection between the master and the slave.

Fig. 1.7 MOSI

1.3.1 SERIAL VS PARALLEL COMMUNICATION

Electronic devices sending bits of data through wires physically
connected between devices. A bit is like a letter in a word, except instead of the
26 letters (in the English alphabet), a bit is binary and can only be a 1 or 0. Bits
are transferred from one device to another by quick changes in voltage. In a

12
system operating at 5 V, a 0 bit is communicated as a short pulse of 0 V, and a 1
bit is communicated by a short pulse of 5 V. The bits of data can be transmitted
either in parallel or serial form as shown in Fig. 1.8. In parallel communication,
the bits of data are sent all at the same time, each through a separate wire [22],
[23]. The following diagram shows the parallel transmission of the letter “C” in
binary (01000011):

Fig. 1.8 Bit Transmission in Parallel Communication

In serial communication, the bits are sent one by one through a single
wire as shown in Fig. 1.9. The following diagram shows the serial transmission
of the letter “C” in binary (01000011):

Fig. 1.9 Bit Transmission in Serial Communication

13
1.3.2 PIN FUNCTIONS OF SPI
 Master Output/Slave Input (MOSI) - the master transmits data to the
slave.
 Master Input/ Slave Output (MISO) – slave delivers data to master,
 Clock (SCLK) – clock signal line.
 Slave Select/Chip Select (SS/CS) – allows the master to select to which
slave to transfer data.

1.3.3 MISO and MOSI

The master sends individual data bits to the slave over the MOSI
connection. The master transmits data to the slave using the MOSI pin. The
norm for data transmission between the master and the slave is most significant
bit first. The slave sends the least significant piece of data back to the master as
shown in Fig. 1.10 and Fig. 1.11[24].

1.3.4 SPI DATA TRANSMISSION

Fig. 1.10 Clock Signal

14
 Fig. 1.11 Slave Select Activation

Fig. 1.12 Master to Slave Data Transfer

Fig. 1.13 Slave to Master Data Transfer

The master generates the frequency of the clock. When the master pushes
the SS/CS pins to a reduced voltage state, the slave is activated. The master
transmits information bit by bit to the slave over the MOSI line. The slave
inspected each received bit as shown in Fig. 1.12, Fig. 1.13. When a response is
required, the slave sends the data back to the master bit-by-bit over her MISO
line. The master performs an analysis on the received bits [25].

In summary, SD card interface using FPGA aims to design and

implement an efficient and reliable interfacing. This optimizes the design for
high-speed data transfer and low power consumption. The SD card interface

15
will provide an effective solution for data storage and transfer in a range of
portable devices.

CHAPTER 2

LITERATURE SURVEY

A literature survey involves existing published materials such as articles

and books related to a specific topic. The goal is to gain a better understanding
of the topic, identify what research has already been done, and determine what
areas still need further investigation. This chapter is split into 2 “SD Card
Interfacing” and “FPGA Implementation Using SD Card”

2.1 SD CARD INTERFACING

According to Dumitrel Catalin Costach et al [26] used the SPI protocol,

an FPGA controller may read and write data to an SD card. The SPI transfer
mechanism is required for the further development of fundamental storage
systems. If we want to use additional SD cards, we need to make sure that they
all use the same clock, data, and chip select signals. Only then can we use more
SD cards. Even though it requires the use of a number of separate cards, this
method of accessing memory permits the storing of very large quantities of
information.

According to Gul Munir Ujjan et al [27] introduced a basic hardware

architecture for processing SD cards in 4-bit SD mode that is based on FPGA
and has an integrated NIOS-II processor. Software for the NIOS II processor is
developed using the Eclipse platform. The read-and-write instructions for a
single block in the FAT-32 file system have been drafted and tested. These
instructions are able to be carried out in a single-bit SD mode. As compared

16
with SD cards that only have one bit, the read performance of SD cards that
have four bits is roughly 67% better than that of SD cards that just have one bit.
When it comes to write operations, the SD 4-bit mode is thus 80% quicker than
the SD 1-bit mode. It is vital to offer a mechanism that can do multi-block
writes and reads as well as swiftly generate 16-bit CRC write instructions since
it may be a high priority to improve the overall performance of the system.
Because of this, it will always be necessary to acquire more costly hardware
resources. The suggested firmware would be useful for a variety of different
applications, one of which is the capturing of video in real time.

According to Pallavi Polsani et al [28] The microcontroller may be

connected to the other devices via the use of external A/D converters, D/A
converters, and EEPROMs, as well as through serial synchronous
communication between master and slave devices. There are two primary
categories that can be used to classify protocols. Priorities: 2) The Inter-I2C
Link Each protocol has been fine-tuned to work optimally for the
communication between ICs on a board. Inside and between processors, SPI has
emerged as the preeminent standard for the delivery of data streams at low to
medium data transfer speeds. Serial Peripheral Interface, sometimes known as
SPI, is a master-slave system that transfers data in bits and may be configured in
a wide variety of ways. System Verilog was applied in both the verification
process and the actual implementation of the SPI architecture. Validation has
been performed on both the system's functioning and its code coverage. Verilog
is used to build the whole RTL for synthesis, while System Verilog is used to
design the verification architecture, and Spartan 3E is used to implement it. This
combination assures the highest possible level of quality.

According to J. Y. Qiang et al [29] it has been proved that the SPI bus is
similar to a synchronous, full-duplex serial interface data bus line. Moreover,

17
the SPI bus offers a straightforward protocol and a fast rate of data transfer.
Since they make quick device creation and testing possible, FPGAs are a
popular solution for applications that need parallel processing. In this section,
we will talk about the formation of SPI as well as its functioning. The operation
sequence as well as the four modes are broken down and analysed by the
communication bus. A module circuit provides an FPGA interface capability for
an SPI bus. This capability is given. The hardware description language Verilog
is used throughout the design process of the SPI, while the vivado simulator is
utilised to mimic the SPI's waveforms. The viability of the approach is shown
via the use of a simulation of waveform analysis.

According to Omar Elkeelany et al [30] using a programmable Field-

Programmable Gate Array (FPGA) data extractor device that permits
bidirectional SD card hardware design, this was revealed. In all, an SD card can
read and write 5000 blocks per second, or 1.051 seconds. On the last effort, the
same block size took 60 seconds. The differences result from the researchers'
choices of distinct software-based methods and finite-state machine
architectures. This demonstrates the technical feasibility of data transport speeds
of up to 25 Mb/s. This letter describes a technique for storing data from distant
SG activities on SD cards in real time. Scaling difficulties, such as the effect of
larger SD cards and SD cards from different manufacturers, will be addressed in
future work.

According to Zhenlin et al [31] it makes it possible to save crucial data on

an SD card in a very short amount of time. After this step, the system designs
and constructs an FPGA-based SD card reader system architecture in order to
fulfil the requirements of SD memory card readers. The item was examined and
evaluated prior to its installation. Since it is able to read and write data into SD
cards, it satisfies the FPGA device criteria that must be met for outside garage

18
devices. Because of this, it was necessary to create an SD card reader that could
be used on any device that is based on an FPGA.

According to K. Kumar et al [32] he results were then tested on three

different FPGAs, each with varying specifications. The first FPGA used was a
45nm Spartan-6, part name xc6slx4, package-tqg144, running on -3 speed grade
at an ambient temperature of 25.0°C. The second was a 90nm Spartan-3, part
name xc3s50, package-pq208, running on -5 speed grade at an ambient
temperature of 25.0°C. Finally, a 65nm Virtex-4, part name xc4vfx12, package-
sf363, running on -12 speed grade at an ambient temperature of 50.0°C was
used for testing. The energy consumption of each FPGA was analyzed using
XPower Analyzer. The authors aimed to compare the power consumption of the
UART design on different nanometer-based technology FPGAs. The use of
Verilog hardware description language allowed for a standardized design,
ensuring that the analysis results were accurate and reliable. The study provided
valuable insights into the energy consumption of UART designs on different
FPGAs, which can help in the development of low-power designs for digital
circuits and systems. The use of Xilinx ISE Design 14.1 software and XPower
Analyzer provided a comprehensive platform for designing, synthesizing, and
analyzing the power consumption of the UART design on different nanometer-
based technology FPGAs.

According to S. Bayar et al [33] The dynamic partial reconfiguration

feature can dramatically reduce chip area and maximize hardware utilization,
allowing for large and complex designs on small FPGAs. This approach is ideal
for low-cost, compute-intensive applications such as high-performance image
processing systems. The modified cPCAP core with block RAM controller,
bitstream decompressor unit, and ICAP FSM achieved the maximum theoretical
reconfiguration speed of 200MB/s on a Spartan-XC6SLX45 FPGA. The

19
Reconfigurable Processing Element (RPE) with an arithmetic unit that can be
reconfigured on-the-fly was also implemented. Multiple RPEs can be used to
design a General Purpose Image Processing System (GPIPS) that can switch
between different algorithms during runtime. As an illustrative example, the
GPIPS on Spartan-6 was programmed to switch between two applications on-
demand, such as two-dimensional filtering and block-matching.

2.2 FPGA IMPLEMENTATION USING SD CARD

According to P. J. Oliver et al [34] proposed a power consumption in

FPGAs using clock gating, clock enable, and blocking inputs. The laboratory
work includes measurement setups and benchmark circuits, with quantitative
measurements conducted on both a 65 nm CMOS Cyclone III and a 45 nm
CMOS Spartan 6 FPGA. The benchmark circuits used are different types of
multipliers, and power consumption results in both active and standby modes
are presented and compared. The study aims to investigate the effectiveness of
clock gating and clock enable techniques in reducing power consumption in
FPGAs. The results show that clock gating and clock enable techniques can
significantly reduce power consumption in both FPGAs. The use of blocking
inputs, however, does not provide a significant reduction in power consumption.
The study provides valuable insights into the use of clock gating and clock
enable techniques to optimize power consumption in FPGAs, which can be
applied in the design of low-power FPGA-based systems.

According to M. K. Birla et al [35] proposed that FPGAs have the ability

to perform operations in parallel, which allows them to outperform DSP chips
that operate sequentially. However, the interfaces between FPGAs and image
sensors have historically been slow, limiting the potential for parallel
processing. This paper presents a method for building an image-processing

20
platform using FPGAs that addresses this issue. Specifically, the paper focuses
on interfacing FPGAs with CMOS image sensors and VGA monitors. The
authors describe techniques used to achieve a processing speed of 50 FPS,
which is a significant improvement over the previously reported speed of 3 FPS.
The paper also presents benchmarking data for a real-time image-processing
application that was executed on both an FPGA-based system and a DSP-based
system, demonstrating the superior real-time performance of the FPGA-based
system. Overall, this paper provides valuable insights into the use of FPGAs for
image processing and highlights the potential for improving processing speed
through better interface design.

According to Y. Yang et al [36] described the development and

implementation of a hardware platform for a digital signal generating system
that converts various file data stored in an SD card into an SDI output signal
using an FPGA. The design process involves two main steps. The first step is
the development of the NIOS II system, which includes the design of SRAM
controller and SD card controller IP cores. The second step involves the
integration of the NIOS II system with scrambling encoders to generate the
entire functional SOPC system using the Quartus II development tool. The
NIOS II system is a critical component of the overall design, as it provides the
necessary processing power to execute the signal conversion algorithms. The
scrambling encoders add an extra layer of security to the system by encoding
the output signal to prevent unauthorized access. The resulting hardware system
is capable of generating SDI output signals at high speeds, making it suitable for
a variety of applications in the digital signal processing industry.

According to S. Navaneethan et al [37] that to implement a real-time

system on an FPGA board for detecting and tracking a human's eye. The
detection algorithm involves thresholding and image filtering, and the location

21
of the pupil is identified by computing the centre value of the detected region.
The proposed hardware architecture is designed using Verilog HDL and
implemented on an Altera DE2 Cyclone II FPGA. The logic utilization of the
system is compared with existing work. The setup includes a Cyclone II FPGA,
an E2V camera, SDRAM, and a VGA monitor. The experimental results
demonstrate the accuracy and effectiveness of the real-time implementation, as
the algorithm is able to manage various types of input video frames, and all
calculations are performed in real-time. Although there is room for further
improvement, the project is a success as it enables accurate detection and
tracking of any inputted eye.

According to V. Asanza et al [38] described the implementation of a

classification system on FPGA that can classify characterized data of an
imaginary motor task and a motor task in lower extremities. A three-layer feed-
forward neural network was designed and tested in Matlab, using various
architectures to evaluate the classifier's performance through methods such as
the confusion matrix and ROC curve.

According to K. Kumar et a [39] described the design and

implementation of a UART on Xilinx ISE Design 14.1, which was tested on
three different FPGAs: Virtex-4 90nm, Virtex-5 65nm, and Virtex-6 40nm. The
UART code was written in Verilog, and power analysis was performed for all
three technology-based FPGAs. The Virtex-4 device used was xc4vfx12,
operating at -12 speed grade with an ambient temperature of 50.0 °C, and the
package used was sf363. The Virtex-5 device used was xc5vlx20t, operating at -
2 speed grade with an ambient temperature of 50.0 °C, and the package used
was ff323. Finally, the Virtex-6 device used was xc6vlx75t, operating at -3
speed grade with an ambient temperature of 50.0 °C, and the package used was

22
ff484. The power consumption of the UART was analysed for each FPGA,
providing insights into its efficiency in different technologies.

According to P. S. Mutha et al [40] presented a novel FPGA

reconfiguration approach that utilizes an external flash memory with an FPGA,
eliminating the need for JTAG port and reducing the reconfiguration time
significantly. The approach employs UART and SPI communication protocols,
enabling configuration file transfer over UART lines only, making the process
simple and eliminating the need for Xilinx tools like iMPACT. The proposed
method is implemented entirely with Xilinx 14.7 Design tools.

23
 CHAPTER 3

PROPOSED WORK

The proposed work aims to develop an SD card interface using an FPGA

(Field-Programmable Gate Array) as a controller. The FPGA will act as a
bridge between the SD card and the host system, allowing for efficient data
transfer and storage. The design will be optimized for high-speed and low-
power consumption, making it suitable for use in portable devices. The
proposed work will involve designing and testing the hardware and firmware of
the SD card interface using the Verilog HDL (Hardware Description Language).
This will be a reliable and efficient SD card interface that can be integrated into
various electronic systems, such as cameras, smartphones, and embedded
devices.

3.1 MODES OF SD CARD

Fig. 3.1 SPI mode pin diagram

24
 Fig. 3.2 One-bit SD mode pin diagram

Fig. 3.3 Four-bit SD mode pin diagram

Among these three modes from Fig 3.1, Fig 3.2, Fig 3.3 (SPI
mode, one-bit SD mode and four-bit SD mode), the latter two are significantly
slower than the former. The higher bit rate of four-bit SD mode allows for rapid
and efficient command execution, including read/write operations and Table.
3.1 shows the comparison between all 3 modes.

Table 3.1 Comparison of one-bit SD mode, four-bit SD mode, SPI

mode.

One - bit SD mode Four - bit SD mode SPI mode

Input Signal 1 CLK PIN, 1 CLK PIN, MOSI,
1 DATA PIN 1 CMD PIN, MISO, CS, CLK
4 DATA PINS
Minimum 0 MHz 0 MHz 1 kHz
Frequency
Maximum 25 MHz 25 MHz 75 MHz
Frequency
Bit Rate 25 Mbps 100 Mbps 25 Mbps

3.2 CONTROL STRUCTURE OF FPGA

25
 Fig. 3.4 illustrates the recommended FPGA block architecture for 4-bit
SD mode and SPI mode protocol. Regarding the data pins, 4-bit SD mode
requires only one clock and four data ones. The Clock Control module's
principal purpose is information sharing. All functionality of 4-bit SD mode
may be assured with the Command Control package. Due to the SD card's
limited 512-byte memory location, two FIFO buffers are designed to
temporarily store data during transmission and reception.

Fig. 3.4 FPGA block diagram.

3.3 SD CARD INITIALIZATION
To start an SD card increased actions are required. A switch on the rear of
every SD card slot indicates whenever a card is inserted. We must enter the card
choose pin. It will disable the card. SD must always be initialized with a
minimum 76 - 160 pulses transmitted to the clock. SD lacks an internal clock
primary source.
Command 0 is just a computer reset which puts the SD card to rest. When
it reaches this condition, it may be configured to operate in SPI mode. There is
only one NCR needed.
cmd_out<= 56'hFF_40_00_00_00_00_95

26
 Command 8 is to check if we are using the correct card. Otherwise, this
particular program will always return to the beginning. This part of the
initialization procedure is mandatory.
cmd_out<= 56'hFF_48_00_00_01_AA_87;
Then to get R3 reaction after the R1 reaction. The one and only thing we
need to understand is that the final byte we get has to be (hex) AA. This signals
the detection of an SD card version 2 (SDHC). There is only one NCR
necessary. Furthermore, the ACMD41 instruction configures the SD card to
operate in SPI mode. There is only one NCR necessary.
cmd_out<= 56'hFF_69_40_00_00_00_01;
During the initial run, the idle flag remains set. This activation procedure
is complete if the flag is cleared. Alternatively, command 55 is delivered. The
ACMD command has a feature in that all commands are preceded with
command 55.
cmd_out<= 56'hFF_77_00_00_00_00_65;
CRC, NCR, and null arguments are often transmitted as 0xFF. The SD
card operates in this manner, which explains why the data remains high.
Whenever the SD card gets busy, the output data pin goes to ground, and when
it is ready, it goes too high. This is helpful when writing on cards. To read a
state register, no instructions are required. Fig. 3.5 illustrates the initialization of
Secure Digital card.

27
 Fig. 3.5 SD card initialization flow chart.

3.3.1 WRITE DATA FOR SD CARD

The data could well be transferred to the SD card's 'Memory Core' using
the instructions shown below, followed by real data. WRITE_BLOCKs–Single
blocks of data is being written (512 bytes).
WRITE_BLOCK
A block on an SD card has been believed to be a sequence of 512 bytes of
memory addresses for as long as anybody can remember. The WRITE BLOCK

28
command is used to permanently store data in a memory block beginning at
address 2000. For the command set to operate properly, it must appear as
follows:

Everything begins at byte 0x18 (command). Second through fifth bytes

(0x000007d0) (argument) (This option is needed to be 0, even when the other
commands have no further arguments. (CRC) represents the random values
included in the sixth byte. Seven-byte NCR. After receiving the command from
the FPGA, the R1 should respond. Every bit must be zero. With the R1 response
byte set to zero, the FPGA is able to transmit the data for writing to the SD card.
The minimal data length should be 512 bytes. This is true even if the length of
the real data is shorter. Immediately following the 512 bytes of data is the Data
Token byte. Next, a 16-bit CRC byte must be utilized for the final verification.
The total number of bytes in the data packet will be 515, which is equivalent to
1 plus 512 plus 2. The least significant bit (LSB) is set to 1 in this informative
token (0xFE).

The command to be concerned with is 24, and until a clear R1 data is

received, dummy bytes are sent; a dummy byte is followed by a token byte
(11111110b); the same 512 bytes of data are sent; two CRCs are sent to
determine if the data is valid; and finally, a data response is received to
determine if the data is viable. This is accomplished in hardware, not via an SD
card erase command.
cmd_out<= {16'hFF_58, address, 8’hFF};

After receiving the data response, the SD card may be written to; however,
before the card's status can be verified, it must be de-asserted eight times (1
byte) and then reasserted. While the preceding code snippet may occasionally
function and is frequently how datasheets are to be understood, the SD card
29
must be deselected prior to beginning the writing procedure. When the SD card
is being used for something else, the output data will be reduced (if this option
is set), but when it is no longer in use, the output data will be increased to
indicate that it is accessible. Fig. 3.6 illustrates write data of Secure Digital
Card.

Fig. 3.6 Write data flow chart for SD card.

3.3.2 READ DATA FOR SD CARD

We can retrieve the information saved in the "Memory Core" of SD card
by following the instructions listed below.

30
 A single block of data (512 bytes) is read from the SD card in READ
BLOCK mode.

READ_SINGLE_BLOCK
Each SD card block is represented by a 512-byte memory address
sequence. The READ SINGLE BLOCK command is used to get a single block
of data beginning at the given memory address. In this instance, 2000 is the
beginning address. The command packet format must be as follows:
When the time comes to record the succeeding data block.
0x51 is the value of the first byte (command).
(The argument) positions 0x000007d0 through 0x000007ff (This field must be
set to zero even when there are no parameters for those other commands.)
(CRC) represents the random values included in the sixth byte. Seven-byte
NCR. The response from R1 should reach FPGA immediately following the
instruction. All bits should be set to zero. The FPGA may get information from
the SD card if the R1 response byte is zero. Each READ SINGLE BLOCK
request from an SD card returns 512 bytes in response. Fig. 3.7 illustrates read
data of Secure Digital Card.

cmd_out<= {16h’FF_51, address,8’hFF};

31
Fig. 3.7 Read data flow chart for SD card.

32
3.3.3 SD CARD CONTROLLER WORKING
Input
Clock - 25Mhz
Reset - Active high reset
Din [7:0] - Data in [write operation]
Address [31:0] - Sector address [Read/Write operation]
Wr - Write enable
Rd - Read enable
Multi_sector_en - Multiple sectors read Henable
I_blk_num - Read total number of blocks in multi sector mode
Miso - Read total number

Output
Cs - chip select
Mosi - FPGA send command/data to be shared
Sclk - spi clock
byte_counter - byte count till 512 bytes
Dout, recv_data - data out from Sd card
status - state changes
byte_available - ensure the valid data by data enable
Reading - data is reading from Sd card
Ready - ready to send the read/write command
Read_for_next_byte - each byte has 8bits. Ready to send next byte
Read_done - enable every 512 bytes completed

33
3.4 FILE SYSTEM LAYER
This section explains the FAT32 file system implementation of the SD
card in detail. The FAT32 file system is actually written into the ‘Memory
Core’ when it was formatted. The FAT32 stands for File Allocation Table 32,
means it has a file allocation table of length 32 bits. The entire data of a file is
scrambled across the Memory Core and the FAT (File Allocation Table) holds
the location of next block corresponding to the location of the current block.

3.4.1 SECTORS
The Memory Core has 8-bit (1 byte) memory locations. The consecutive
8-bit memory locations are grouped into ‘Sectors’. A FAT32 sector usually has
512 bytes per Sector. The grouping of memory bytes to form Sectors is shown
in the following Fig. 3.8.

Fig. 3.8 Structure of Sectors in Memory Card

3.4.2 CLUSTERS
The consecutive Sectors are grouped to form ‘Clusters’. The number of
Sectors per Cluster depends on the size of the entire file system. The grouping
of Sectors to form Clusters is shown in the following Fig. 3.9.

Fig. 3.9 Structure of clusters in Memory Card

34
3.4.3 SCRAMBLED STORAGE
The entire data of a file is scrambled across the Memory Core as Data
Clusters. The following figure shows how the data from three files named A, B,
C are scrambled across the Memory Core. FAT (File Allocation Table) holds
the location of next Cluster corresponding to the location of the current Cluster
of the file as shown in Fig. 3.10.

Fig. 3.10 Scrambled Data Storage in SD Card

3.5 FILE FORMAT OF FAT32

Data is read from and written to memory modules using FAT32. Initially,
clusters concentrate on a small number of sectors. It is displayed in Fig. 3.11.

Fig. 3.11 Format of FAT32.

The first and foremost sector is the MBR which is known as Master Boot
Record. This comes after a lengthy time in which many sectors remained
inactive. These sectors are designated as reserved ones; the BOOT sector comes
first, followed by the FAT sector. The count of FAT sectors is determined by
the file system size. Clusters followed FAT sectors and before insecure ones.

35
3.5.1 PARTITION
The MBR (Master Boot Record) is the very first Sector of the ‘Memory
Core’ and it is meant to hold the information regarding the partitions inside the
file system. The MBR can hold details of four fundamental partitions. The first
accessible line of data in an SD card will start at something like address 8192
but in a HEX editor such as WinHex you will not see these first 8192 bytes and
it will in fact say sector 0. When in reality reading from sector 0 will actually
require address 8192, in general this offset will take this value but of course a
computer needs to be certain as it can take other values. There are a few things
first which should be known. Firstly, a sector consists of 512 bytes, this is set
and cannot be changed. Each bit in the SD card command address corresponds
to a sector, therefore single bytes cannot be written or read, only in multiples of
512-byte sectors. A cluster is a multiple of sectors, for example my SD card has
been configured to 64 sectors per cluster, this is written into the FAT boot
record. Lastly all of the SD card data, not our file data, follows something called
"little endian", the data is read backwards, so byte 1, byte 2, byte 3, etc… Below
is an example of the partition, the software does a great job of decoding what all
of these bytes mean. The only part of data that we need is the location of the
first sector, so we would read from address zero and then continuously read and
discard the data until we reach bytes 0x1C6 through to 0x1C9. The first sector
is known as the boot sector, this is where most HEX editors will start from,
without reading the partition we would be unable to accurately reach this point.
The data read is 00 20 00 00 which is actually 0x00002000, following little
endian, this corresponds to 8192 decimals.

36
 Fig. 3.12 Partition 512 bytes – Sector 0 of SDCARD

The Partition Info Bytes are 16 bytes long and each of them holds
important information regarding the corresponding partitions. The last byte of
the MBR is the signature byte which holds a specific value (0xAA55 for
FAT32) which can be used to check whether the sector is MBR or not. The four
bytes long First Sector number of the partition can be read starting from 8 th bit
to 11th bit of the Partition Info Bytes as shown below Fig. 3.13:

Fig. 3.13 Partition of First Section in Memory Core

FIRST SECTOR = 00 20 00 00 (Fig. 3.12 Partition)

So, Boot sector address = 0x00002000 (in decimal 8192).
37
3.5.2 MASTER BOOT SECTOR
The Boot Sector is the very first sector inside a partition. This Sector
holds all the valuable details regarding the file system inside that particular
partition.

Fig. 3.14 Bit Values of Boot Sector in Memory Core

From Fig. 3.14 the first two bytes are Check Bytes which together holds a
specific value, usually 0xE9 or 0xEB. The 11 th and the 12th bytes when read
together give the number of Bytes per Sector for the file system. The FAT32
usually has 512 bytes per Sector. The 13 th byte holds the number of Sectors per
Cluster for the file system. The 14 th and the 15th bytes together read the number
of Reserved Sectors before the FATs, starting from the beginning of the
partition. The 16th bit holds the value of the number of FATs in the file system.
The 4 bytes starting from the 27th byte to 30th byte can be read together to get
the number of Hidden Sectors between the FATs and the First Cluster of the
partition. The 4 bytes starting from the 43rd byte to the 46th byte holds the
address of the root cluster, which is the very first cluster of the partition (usually
2). The 47th and the 48th bytes can be read together to get the location of the
Sector where the File Information is stored (Directory Sector).

After finding the start of the boot sector we need to load this value into
the read command, so loading 8192 into the SD cards read command will bring
us to the boot sector. Here is an example of the boot sector, the main things we
need to read from this are, the bytes per sector (this should always be 512), the

38
sectors per cluster, the reserved sectors, the hidden sectors and the sectors per
FAT. You may notice the offset in the software can be calculated by sectors x
bytes per sector, 8192 x 512 = 4194304, 0x400000.

Fig. 3.15 Master Boot sector/Record

Check Bytes = EB 58 90 (0th– 2nd bytes) (from Fig. 3.15)

Bytes per Sector = 00 02 (11th – 12th bytes)

0x0200 = 512 bytes

number of Sectors per Cluster = 40 (13th byte)

0x40 = 64

number of Reserved Sectors = 98 18 (14th& 15th byte)

39
 = 0x1898

= 6296

number of FATs = 02 (16th byte)

number of Hidden Sectors = 00 00 20 00 (8192)

3.5.3 ROOT DIRECTORY

To find the start of the root directory we use the formula, "Hidden
Sectors + Reserved Sectors + (2 x sectors per FAT)". So using the formula I
would get 16384, loading this into the read command would bring me to the
root directory as shown in the example below. The root directory contains
entries relating to the files saved on the card, each entry takes 32 bytes from
Fig. 3.16.

40
 Fig. 3.16 Root Directory
Taking the first entry from the root directory,

The entry has been deleted, the file is called "001", the file is an archive, etc...
You may also notice that some data is missing such as a the cluster offset and
the size of the file, the reason is that this is a deleted file. The following is the
actual file, we can see this time that the file is about 17kbyte long and the offset
cluster is 3. In the boot sector there was an entry called the "root cluster", it's
value was 2, it will always be 2

41
The root cluster is referring to the root directory, so when the cluster offset in
the entry above says 3 it means that it is the cluster after the root directory. Our
root directory is cluster 2 and our file is in cluster 3. The root directory has the
sector address location 16384, since there are 64 sectors per cluster it means that
our file is at sector 16448. You will find there are a great deal of entries relating
to your file even if you have only ever saved one copy, only one of them will be
valid, a disc clean up tool such as a defragmenter will remove these obsolete
entries.

3.5.4 FILE SEARCH DIRECTORY SECTOR

It is the first Sector inside the first Cluster of the file system. The first Cluster
always starts with a Cluster number 2. It is also the very first Data Sector of the
partition. The FS Directory is 32 bytes long and hence there are 16 FS
Directories per FS Directory Sector. The Sector number of the First FS
Directory Sector can be found by using the following equation:
DIR_SECTOR_NUM = No. RESERVED SECTORS + No. FATS + No.
HIDDEN SECTORS
Each FS Directory holds the significant details regarding a single file as shown
in the following Fig. 3.17:

Fig. 3.17 Structure of FS Directory in SD Card

3.5.5 READING FILE FROM FAT32

42
 Fig. 3.18 illustrates that it is able to read FAT32-formatted files. This
sector read has been discovered to be the final phase of every operation. We can
use the READ_SINGLE_BLOCK command supplied by the SD Command
Layer to read only this one sector from the memory core of the SD card.
sdcard_fat _32_read. V
FAT32 sector cluster counts are expressed by 32 bits. Every cluster is
represented by a 32-bit set. If each cluster consists of 512 bytes, then the sector
will have 128 cluster pointers. This section describes how space is allotted to
files in a FAT32 file system.

The following equation may be used to compute the number of the next cluster
pointer within the FAT32.
Number of sectors of FAT in the next cluster pointer = number of first
sectors in partition + reserved number of sectors + ((clusters of current number
* 4)/bytes per sector).

43
 Fig. 3.18 FAT32 Algorithm for reading.

From Fig. 3.19 the yellow-coloured box indicates the cluster that contain
the data for each file in FAT32 and the respective cluster pointers. The red-

44
coloured line shows that the next cluster pointer which matches the present
cluster is being sought, while the green-coloured line shows that the next cluster
is being sought using the cluster thing about having in the FAT32 clusters
pointer.

Fig. 3.19 Read Scrambler file in flash ‘Memory Core’.

3.5.6 LAYERS OF FPGA

Since there are three functional layers, namely Serial Interface Layer, SD
Commands Layer and File System Layer, the coding is also done for each of the
layers separately and then combined together. The code layers are shown in the
following Fig. 3.20:

45
 Fig. 3.20 Block Diagram of Coding layers in FPGA

The FPGA read and writes data using the File System Layer. The File
System Layer interacts with the SD Commands layer using
READ_SINGLE_BLOCK command only. The SD Commands Layer interacts
with the Serial Interface Layer using SPI transmission and SPI reception
function calls. The entire FPGA system interacts with the SD card using the SPI
bus interface.

Function pointers have been used for the interaction between different
layers effectively. Structures and dynamic memory allocation has been used to
store and access 512 bytes of data each time.

46
 CHAPTER 4
SOFTWARE DESIGN
Xilinx 14.7 is a software tool used for programming, designing, and
testing FPGAs (Field Programmable Gate Arrays) and SoCs (System on Chips).
The software is produced by Xilinx, a leading provider of FPGAs and
programmable devices. Xilinx 14.7 software has a user-friendly interface that
allows designers to easily create and configure their designs. One of the key
features of Xilinx 14.7 is the Integrated Design Environment (IDE), which
provides a comprehensive platform for designing, testing, and debugging
FPGAs and SoCs. The IDE includes tools such as a synthesis engine, place-and-
route algorithms, and a timing analyzer, which allow designers to quickly and
efficiently develop complex designs. Another notable feature of Xilinx 14.7 is
its support for a wide range of FPGAs and SoCs, including the Zynq-7000 and
the Virtex-7 families. This allows designers to choose the device that best suits
their application requirements and ensures that their designs can be easily
migrated to newer devices as they become available. Xilinx 14.7 also includes a
range of IP (Intellectual Property) cores that can be used to accelerate the
development of FPGA and SoC designs. These cores include digital signal
processing (DSP) blocks, memory controllers, and Ethernet and USB interfaces,
among others. The use of IP cores can significantly reduce design time and
complexity, allowing designers to focus on the unique aspects of their
application. Finally, Xilinx 14.7 includes extensive documentation and support
resources, including online tutorials, user guides, and a community forum. This
ensures that designers can quickly and easily get up to speed with the software
and obtain help if they encounter any issues.

47
 CHAPTER 5
RESULTS

Table 5.1 Comparison between existing methods and our method

Proposed Work LUT (Look-Up Flip Flop Clock period
Table)

Spartan 6 916 464 5.35 ns

Artix-7 653 413 3.254 ns

Existing Method

[26] Artix-7 1025 579 10.5 ns

Comparing the specifications of the Spartan 6 FPGA (530 Slice

Registers, 916 LUT's, 464 Flip Flops, 5.35 ns clock period, 186.925 MHz
frequency) and the Artix-7 (512 Slice Registers, 653, LUT's, 413 Flip Flops,
3.254 ns clock period, 307.342 MHz frequency) demonstrates that our proposed
results provide better resource utilization than existing methods shown in Table
5.1.

48
 CHAPTER 6
CONCLUSION

Thus, we conclude our proposed work that an FPGA controller allows SD

card writing and reading with Strontium 4-bit SD mode using Spartan 6 FPGA
and Artix-7 which was executed in Xilinx ISE software tool. Easily expandable
storage system add number SD cards contain sharing the same clock and data
signals different chip select signal for each card was suggested the architecture
involves accessing each card in sequence, but it is allowed.

8.1 FUTURE SCOPE

 For future work, in the implementation of FPGA-based classification
systems, it is proposed to change the SD memory for a Double Data
Rate 3 Synchronous Dynamic Random-Access (DDR3-SDRAM)
memory, and test with different configuration to reduce the access
time; in the algorithmic part it is proposed to reduce the extraction
time of the characteristics using time-frequency characteristics.

49
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