UART -Universal Asynchronous Receiver Transmitter- IT CAN WORKING AS A DUPLEX AND

FULL DUPLEX.

IN UART SOME PARAMETERS ARE SET BY USERS ARE-

Baud Rate (9600, 19200, 115200, others)
Number of Data Bits (7, 8)
Parity Bit (On, Off)
Stop Bits (0, 1, 2)
Flow Control (None, On, Hardware)
FOR CORRECT TRANSMISSION AND RECEVING COMMUNICATION IT IS NECESSARY TO SET SAME
PARAMETERS VLUES BOTH SIDE.

BAUD RATE:- IT IS DEFINES HOW MUCH RATE THE SERIAL DATA IS TRANSMITTED . LIKE – 19200 BAUD
RATE MEAN IT IS TRANSMITTED 19200 BITS PER SECOND.

IN MAJORITY NO. OF DATA BITS VALUE USED IS 8.

PARITY BIT IS CALCULATED USING XOR OPERATION AND SENT AFTER THE DATA BITS.

STOP BITS ITS VALUE IS LOGIC 1 AND IT IS SET BY USER HOW MUCH BIT IS USED FOR REPERSENTAION
OF STOP BIT.

FLOW CONTROL IS NOT USED IN NOW DAYS SO ITS TAKING AS NONE.

START BIT – WHEN TRANSITION FROM HIGH TO LOW. This first transition indicates the
start bit. Once the beginning of the start bit is found, the FPGA waits for one half of a bit period. This
ensures that the middle of the data bit gets sampled. From then on, the FPGA just needs to wait one
bit period (as specified by the baud rate) and sample the rest of the data. The figure below shows
how the UART receiver works inside of the FPGA. First a falling edge is detected on the serial data
line. This represents the start bit. The FPGA then waits until the middle of the first data bit and
samples the data. It does this for all eight data bits.

UART Serial Data Stream

The code below uses one Start Bit, one Stop Bit, eight Data Bits, and no parity. Note that the
transmitter modules below both have a signal o_tx_active. This is used to infer a tri-state buffer for
half-duplex communication. It is up your specific project requirements if you want to create a half-
duplex UART or a full-duplex UART.

out_rx_dv
In_rx_clk
UART_RX
In_rx_serial Out_rx_byte
module UART_rs232_rx (Clk,Rst_n,RxEn,RxData,RxDone,Rx,Tick,NBits); //Define my module
as UART_rs232_rx

input Clk, Rst_n, RxEn,Rx,Tick; //Define 1 bit inputs

input [3:0]NBits; //Define 4 bits inputs

output RxDone; //Define 1 bit output

output [7:0]RxData; //Define 8 bits output (this will eb the 1byte received data)
//Variabels used for state machine...

parameter IDLE = 1'b0, READ = 1'b1; //We haev 2 states for the State Machine state 0
and 1 (READ adn IDLE)

reg [1:0] State, Next; //Create some registers for the states

reg read_enable = 1'b0; //Variable that will enable or NOT the data in read

reg start_bit = 1'b1; //Variable used to notify when the start bit was detected
(first falling edge of RX)

reg RxDone = 1'b0; //Variable used to notify when the data read process is done

reg [4:0]Bit = 5'b00000; //Variable used for the bit by bit read loop (in this case 8
bits so 8 loops)

reg [3:0] counter = 4'b0000; //Counter variable used to count the tick pulses up to
16

reg [7:0] Read_data= 8'b00000000; //Register where we store the Rx input bits before
assigning it to the RxData output

reg [7:0] RxData; //We register the output as well so we store the value
///////////////////////////////STATE MACHINE////////////////////////////////
//////////////////////////////////////////////////////////////////////////// ////////
///////////////////////////Reset//////////////////////////////////// ////////////////
////////////////////////////////////////////////////////////

always @ (posedge Clk or negedge Rst_n) //It is good to always have a reset always

begin if (!Rst_n) State <= IDLE; //If reset pin is low, we get to the initial state
which is IDLE

else State <= Next; //If not we go to the next state

end ////////////////////////////////////////////////////////////////////////////
////////////////////////////Next step decision//////////////////////////////
//////////////////////////////////////////////////////////////////////////// /*This
is easy. Each time "State or Rx or RxEn or RxDone" will change their value we decide
which is the next step. - Obviously we get to IDLE only when RxDone is high meaning
that the read process is done. - Also, while we are into IDEL, we get to READ state
only if Rx input gets low meaning we've detected a start bit*/

always @ (State or Rx or RxEn or RxDone) begin

case(State)

IDLE: if(!Rx & RxEn) Next = READ; //If Rx is low (Start bit detected) we start the
read process

else Next = IDLE;

READ: if(RxDone) Next = IDLE; //If RxDone is high, than we get back to IDLE and wait
for Rx input to go low (start bit detect)

else Next = READ;

default Next = IDLE;

endcase

end ////////////////////////////////////////////////////////////////////////////
///////////////////////////ENABLE READ OR NOT///////////////////////////////
////////////////////////////////////////////////////////////////////////////

always @ (State or RxDone) begin

case (State)

READ: begin read_enable <= 1'b1; //If we are in the Read state, we enable the read
process so in the "Tick always" we start getting the bits

end

IDLE: begin read_enable <= 1'b0; //If we get back to IDLE, we desable the read
process so the "Tick always" could continue without geting Rx bits

end

endcase

end //////////////////////////////////////////////////////////////////////////// ////

///////////////////////Read the input data//////////////////////////////
////////////////////////////////////////////////////////////////////////////
/*Finally, each time we detect a Tick pulse,we increase a couter. - When the counter
is 8 (4'b1000) we are in the middle of the start bit - When the counter is 16
(4'b1111) we are in the middle of one of the bits - We store the data by shifting the
Rx input bit into the Read_data register using this line of code: Read_data <=
{Rx,Read_data[7:1]}; */

always @ (posedge Tick) begin

if (read_enable) begin

RxDone <= 1'b0; //Set the RxDone register to low since the process is still going

counter <= counter+1; //Increase the counter by 1 with each Tick detected
if ((counter == 4'b1000) & (start_bit)) //Counter is 8? Then we set the start bit to
1.

begin start_bit <= 1'b0;

counter <= 4'b0000;

end if ((counter == 4'b1111) & (!start_bit) & (Bit < NBits))

//We make a loop (8 loops in this case) and we read all 8 bits

begin Bit <= Bit+1;

Read_data <= {Rx,Read_data[7:1]};

counter <= 4'b0000;

end

if ((counter == 4'b1111) & (Bit == NBits) & (Rx)) //Then we count to 16 once again
and detect the stop bit (Rx input must be high)

begin Bit <= 4'b0000;

RxDone <= 1'b1;

counter <= 4'b0000;

start_bit <= 1'b1; //We reset all values for next data input and set RxDone to high

end

end

end //////////////////////////////////////////////////////////////////////////// ////

//////////////////////////Output
assign///////////////////////////////// /////////////////////////////////////////////
/////////////////////////////// /*Finally, we assign the Read_data register values to
the RxData output and that will be our final received value.*/

always @ (posedge Clk) begin

if (NBits == 4'b1000) begin

RxData[7:0] <= Read_data[7:0];

end

if (NBits == 4'b0111) begin

RxData[7:0] <= {1'b0,Read_data[7:1]};

end

if (NBits == 4'b0110) begin

RxData[7:0] <= {1'b0,1'b0,Read_data[7:2]};

End

end //End of the RX mdoule

endmodule

////////////////////////////////////////////////////////////////////

module new_Rx_baud(clk,Rst,Rx_baud);
parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;
parameter S3 = 2'b11;
output Rx_baud;
input Rst;
input clk;
reg Rx_baud;
reg [1:0]Pr_state;
reg [1:0]Nx_state;
integer count;
always@(Rst or count or Pr_state)
begin
case(Pr_state)
S0:
begin
if(Rst)
begin
Nx_state = S0;
end
else
begin
Nx_state = S1;
end
end
S1:
begin
if((count >= 0) && (count <= 81))
begin
Nx_state = S1;
end
else
begin
Nx_state = S2;
end
end
S2:
begin
if((count > 81) && (count < 163))
begin
Nx_state = S2;
end
else
begin
Nx_state = S0;
end
end
default:
begin
Nx_state = S0;
end
endcase
end
always@(posedge clk or posedge Rst)
begin
if(Rst)
begin
count = 0;
Pr_state = S0;
end
else
begin
Pr_state = Nx_state;
case(Nx_state)
S0:
begin
count = 0;
end
S1:
begin
Rx_baud = 1;
count = count + 1;
end
S2:
begin
Rx_baud = 0;
count = count + 1;
end
default:
begin
count = 0;
Rx_baud = 1;
end
endcase
end
end
endmodule