UART Controller with FIFO Buffer Function Based

on APB Bus

Jiajing Li1, Lixin Yang2, Xi Feng2, Yanhui Xing1, Zhijie Chen1, Peiyuan Wan1*
1
Beijing Embedded System Key Lab, College of Microelectronics, Faculty of Information Technology
2022 IEEE 16th International Conference on Anti-counterfeiting, Security, and Identification (ASID) | 978-1-6654-9067-2/22/$31.00 ©2022 IEEE | DOI: 10.1109/ASID56930.2022.9996035

Beijing University of Technology, Beijing, China

2
Beijing Smart-chip Microelectronics Technology Co., Ltd. Beijing 100192, China
*
wanpy@bjut.edu.cn

Abstract—This paper proposes a UART communication
interface based on APB bus with asynchronous FIFO buffer.
Based on this design, the UART controller can be flexibly
configured through the AMBA bus to support baud rate
modification, transmission bits, configurability of parity mode
and other functions. And the asynchronous FIFO buffer function
is added for communication between high-speed devices and low-
speed UART devices. During data transmission, the FIFO can
buffer the data and the situation that the UART device occupies
the APB bus and the processor for a long time can be avoided,
improving the data transmission efficiency. The design is based
on the UART transmission protocol. the finite state machine
method is used to control the the transmission timing of UART
interface, and RTL simulation and FPGA verification are carried
out, showing good flexibility of this design.
Keywords—UART; APB bus; FIFO; Configurable; FPGA
I. INTRODUCTION
UART is a universal asynchronous transceiver for serial
data communication and is used for asynchronous
communication. The bus has bidirectional communication,
which can realize full-duplex transmission and reception. It
can receive data from peripheral devices and convert between
serial communication and parallel communication. Compared
with IIC and SPI communication protocols, UART can realize
full-duplex asynchronous transmission with only two wires,
which is more resource-saving and good at long-distance
transmission [1,2]. It is currently widely used in MCU multi-
computer communication and various external modules for
cache data transmission. The UART protocol stipulates that
both receiving and sending data should be transmitted on a
separate line, without the need for a clock line. The
transmission rate needs to be determined by the baud rate, but
the existing UART design functions are not comprehensive
enough. The baud rate and frame length of some UART
interfaces cannot be flexibly configured, and the application
scenario is single. Therefore, in order to provide the maximum
flexibility for SOC design and FPGA development, the
configurable UART interface based on APB interface
proposed in this paper solves the above problems. In order to
improve the efficiency of sending and receiving transmission,
a data buffer is provided and a FIFO module is added. As a
long-distance communication interface, UART has been
widely used in digital systems and is a very important module.
The modules of the UART are designed with a modular
approach, including the APB bus interface module, the
register management module, the synchronization module, and
the clock control module, as well as FIFO control module,
filter module, sending and receiving module, etc. This paper
firstly introduces the UART transmission protocol and divides
the internal structure of the UART module in detail according
to the protocol. Then the registers and SPI state machine of the
interface module are designed in detail. Finally, through RTL
simulation and FPGA verification, the UART communication
can be implemented correctly.
II. DESIGN SCHEME
A. UART and APB Transmission Process
The UART has one line for receiving data and the other
line for sending data. When the signal line is idle and does not
transmit data, it is in a high-level logic “1” state, indicating that
there is no data transmission on the current line. Then the
master device first sends a logic “0” signal, indicating the
beginning of the transmission character. Then send data bits,
which can be 5~8 logical “0” or “1”. Such as ASCII code (7
bits), extended BCD code (8 bits) in most cases using little
endian transmission. Then the data bit will be followed by a
parity bit. After the data bit is added with this bit, the number
of digits of “1” should be an even number (even parity) or an
odd number (odd parity). Finally, the stop bit is sent, which is
the end of a character data such as 1-bit, 1.5-bit, 2-bit high
level. The data transmission timing of the UART transmission
protocol is shown in Fig.1.
0 1 1
1 LSB Idle
MSB Parity Stop
Start bit bit bit
bit
DATA
Figure 1. UART transmission timing

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 difference is that PWRITE changes to low level during the
T1 T2 T3 T4 T5 SETUP cycle at the beginning of the transfer, indicating the
read transfer state. Secondly, during the ENABLE cycle, the
PCLK slave peripherals must provide valid data in advance to ensure
that the rising edge of the clock at the end of the ENABLE
PADDR ADDR
cycle can be captured, so that the master can read the correct
data [3,4].
PWRITE
B. Block Diagram
PSEL According to the transmission process and related
requirements of the UART protocol, the internal structure
PENABLE
design of the interface module is shown in Fig.4. The APB bus
controls the read/write of the entire UART internal registers.
PWDATA DATA The APB slave is the connection bridge between the UART
interface and the APB bus, and it is responsible for exchanging
Figure 2. APB write transfer data with the CPU through the APB bus [5]. The output of the
APB slave includes FIFO read and write signals and data
stream signals, which are responsible for writing the data from
T1 T2 T3 T4 T5 the APB bus into the FIFO and reading data from the FIFO to
the processor. The register control module is responsible for
PCLK latching the address on the APB and controlling the
configuration baud rate and other information. At the same
PADDR ADDR time, the CPU can operate the corresponding control register
and status register through the APB bus. Serial reception or
PWRITE transmission of data is realized by the receive shift register
RX_shifter or the transmit shift register TX_shifter. A filter is a
PSEL filter circuit module for the input signal. When data is input to
the UART port, glitches may appear. If data is not filtered, the
received signal may appear metastable. If data is used directly,
PENABLE
it may cause errors in data transmission results [6].
PRDATA DATA

APB Tx_FIFO Tx_Shifter TXD

Figure 3. APB read transfer

The basic transfer timing of APB bus write operation is Slave

shown in Fig.2. The rising edge of the clock PCLK during
write transfer is valid. The first cycle of T1~T2 is idle state; the CPU
Baud Rate Control Filter RXD
second cycle of T2~T3 is PSEL=1 and PENABLE=0 is the
SETUP state cycle; the third cycle of T3~T4 is PSEL=1 and
PENABLE=1 is the ENABLE state cycle, In the fourth cycle
of T4~T5, PSEL=0 and PENABLE=0 return to IDLE state. At
Rx_FIFO Rx_Shifter
the beginning of the write transfer, in other words, after the
rising edge of T2 in the figure, the write signal PWRITE, the
write address PADDR, the write data PWDATA and the chip Regilter
select signal PSEL all change to valid states. When the rising Control
edge of the next cycle comes, that is, T3 in the figure, the
Figure 4. UART architecture diagram
enable signal PENABLE Valid, and during the entire ENABLE
cycle, PADDR, PWRITE, PWDATA and PSEL remain stable
C. UART Register
and unchanged. Write transfer is performed during this cycle.
After this cycle ends, PENABLE is invalid, and a write transfer TABLE I. THE UART STATUS REGISTER DESCRIPTION
is completed. After the transmission is completed, if the device
does not continue to transmit, the PSEL becomes invalid, and Name Width Distribution
PADDR, PWRITE and PWDATA have no effect on the 2’b00:115200 bit/s
system transmission in the IDLE state, remaining unchanged BAUD_SEL 2bit
2’b01:9800 bit/s
until the next transmission in order to reduce power 2’b10:4800 bit/s
2’b11:2400 bit/s
consumption. The basic transfer timing of the APB bus read
operation is shown in Fig.3, and the read transfer process clock 2’b00:NO PARITY
is also triggered by the rising edge. In the process of APB read PARITY_MODE 2bit 2’b01:ODD PARITY
2’b10:EVEN PARITY
operation, the timings of PADDR, PWRITE, PSEL, and
PENABLE are similar to the timing of write operations. The

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 Name Width Distribution D. Design of State Machine
2’b00:5bit The UART module designed in this paper sends and
2’b01:6bit
DATA_LENGTH 2bit
2’b10:7bit
receives data through the state machine. When the UART
2’b11:8bit module sends data, the state machine is shown in Fig.5. After
Number of stop bit the circuit is reset, it first enters the IDLE state. When the
STOP_BIT 1bit 0:one stop bit UART starts to work, APB SLAVE will configure the
1:two stop bits corresponding working mode, such as the size of the baud rate,
Start bit of data transmission the mode selection of parity, the length of the data frame and
MSB_SEL 1bit 0:MSB stop bit, and the start bit of data transmission – MSB or LSB.
1:LSB When it is detected that the FIFO transmit data buffer is not
High indicates that the transmission empty, it goes to the START state. When the master sends a
TX_FIFO_FULL 1bit
buffer is full
low-level start bit, it enters the WAIT state, and then starts to
High indicates that the transmission send valid data bits. After different time intervals according to
TX_FIFO_EMPTY 1bit
buffer is empty the selection of the baud rate, it enters the SHIFT state,
High indicates that the receive sending a shift signal, and then enters the next WAIT state
RX_FIFO_FULL 1bit
buffer is full
again, sending the next data bit. According to the configured
High indicates that the receive
RX_FIFO_EMPTY 1bit
buffer is empty
data frame length, the data bits to send can be decided. After
the valid data is sent, it enters the PARITY state, sending the
parity bit according to the configured mode, and finally switch
to the STOP state, sending Stop bit, and thus completing the
IDLE transmission process of a data frame [7]. If it is detected that
the FIFO transmission data buffer is not empty at this time, it
will jump from the STOP state to the START state, otherwise
STOP it will jump to the IDLE state.
START When the UART module receives data, the state machine
is shown in Fig.6. Similar to the sending operation, the
corresponding working mode needs to be configured first. The
default is the IDLE state. When a low-level signal is detected,
PARITY it will switch to the START state. According to the baud rate
WAIT setting, when counting to the middle of the received bit unit, if
it is detected to be at a low level, it will be determined as a
start bit, and the state machine alternately enters the WAIT
state and the SAMPLE state to receive the corresponding valid
SHIFT data bits; then enters the PARITY state to receive the parity bit;
and finally enters the STOP state to receive the stop bit to
complete the entire receiving process.
Figure 5. UART sending state machine III. SIMULATION AND VERIFICATION
This design is implemented in Verilog HDL and uses RTL
simulation and FPGA to verify the design. In the RTL
IDLE simulation, the UART module registers are configured by
writing Testbench, which is the work of the UART module.
According to the simulation results of the IIC module, the
STOP
correctness of the IIC module can be verified. Logic function
START verification only verifies the logic implemented by the
hardware description language, and does not indicate whether
the actual circuit is correct. Therefore, after the RTL-level
verification is completed, in order to ensure that the functions
PARITY of the described circuit are completely correct, we adopt the
FPGA verification method. In the FPGA verification, the
WAIT designed UART is imported into the FPGA and verified with
an external UART device to verify the correctness of the
SAMPLE design [8-11].
A. RTL Simulation Verification
Figure 6. UART receive state machine After completing the RTL design of the UART module,
RTL simulation is performedfor the UART module design.

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Figure 7. UART transmission simulation waveform
Figure 8. UART FPGA verification diagram
By adding a testbench to the UART module, including
setting the UART baud rate, data frame length and parity
check mode, etc, the IIC module can realize the normal
communication function, shown in Fig.7, including the
transmission start signal, the transmission of valid data bits,
parity bits and stop bits. It proves the correctness of the
function of the UART module.
B. FPGA Verification
The design is verified by FPGA. The RTL is imported into
ISE for processing, and the generated BIT file is imported into
the FPGA test board. The output pins of the FPGA is tested,
and the results are captured by an oscilloscope as shown in
Fig.8, indicating that the UART module designed in this paper
functions normally.
IV. CONCLUSION
This paper designs and implements a UART
communication protocol equipped with FIFO buffer function
based on APB bus. Through the configuration register, the
baud rate, frame length and parity mode can be flexibly
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configured, and the communication between the high-speed
device and the low-speed UART device can be realized
through the FIFO buffer. During data transmission, the FIFO
can buffer the data synchronously, and at the same time, the
situation that UART device occupies the APB bus and the
processor for a long time can be avoided, improving the data
transmission efficiency. This design adopts finite state
machine design method and Verilog HDL for logic
implementation. Finally, through RTL simulation and FPGA
verification, the designed UART can communicate correctly
with other UART devices.
ACKNOWLEDGMENT
This paper is funded by the project of the State Grid
Corporation of China in 2020,: Research on cache data
consistency technology of main control chip in intelligent
distribution terminal under Grant 5700-202041395A-0-0-00.
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