Vellore – 632014, Tamil Nadu, India

SCHOOL OF ELECTRICAL ENGINEERING

WINTER SEMESTER 2022-2023
CAT-II

SLOT: A2
Programme Name & Branch : B.Tech EEE & EIE Course Code: BEEE208L

Course Name : Analog Electronics

Faculty Members : Dr. M.N. Venkataraman, Dr. G. Arunkumar and Dr. R. Gnanavignesh

Class Number(s) : VL2022230502462, VL2022230502062 and VL2022230502063

Date of the Examination : 13-March-2023

Duration: 90 minutes Max. Marks : 50

General instruction(s): Use calculator to the numerical with three decimal points.

Answer ALL Questions

Q. Question Max. CO BL
No. Marks

1. (a) Develop the circuit diagram of a 6-bit inverted R-2R ladder DAC circuit. And give 5 5 L3
the output voltage.

(b) Construct the 3 bit flash type ADC circuit with reference voltage as 12 V. Also 5
provide its encoder truth table.

2. (a) Design a monostable multivibrator using 555 timer to produce pulse width of 100 5 5 L4
ms. And sketch circuit diagram and necessary waveforms.

(b) For the Astable multivibrator RA = 2.2 kΩ, RB = 6.8 kΩ and c = 0.1 μF. Discover
(i) thigh, (ii) tlow, (iii) free running frequency and (iv) duty cycle. Also sketch the circuit 5
diagram.

3. (a) Construct a positive voltage regulator for an output voltage 12 V from 24 V. 5 5 L4

Assume load current as 1 A.

(b) Construct a negative voltage regulator for an output voltage -15 V from -32 V. 5
Assume load current as -2 A.

4. Calculate the input power, output power and percentage efficiency of the series fed 10 1 L5
directly coupled Class A power amplifier circuit with the following specifications;
VCC = 24 V, RB = 1 kΩ, RL = 20 Ω, and base current of 10 mA peak.

5. For a class B push pull amplifier with VCC = 30 V driving an 10 Ω load, determine (a) 10 1 L4
maximum input power, (ii) maximum output power (iii) maximum circuit efficiency.

Question Paper Setter: Moderator:

Dr. G. Arunkumar