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A New Transmission Gate Cascode Current Mirror Charge Pump for Fast
Locking Low Noise PLL

Article in Circuits Systems and Signal Processing · September 2014

DOI: 10.1007/s00034-014-9785-6

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Circuits Syst Signal Process
DOI 10.1007/s00034-014-9785-6

A New Transmission Gate Cascode Current Mirror

Charge Pump for Fast Locking Low Noise PLL

Umakanta Nanda · Debiprasad Priyabrata Acharya ·

Sarat Kumar Patra

Received: 18 September 2013 / Revised: 21 March 2014 / Accepted: 21 March 2014

© Springer Science+Business Media New York 2014

Abstract Charge Pump in a phase locked loop (PLL) generates non-ideal effects such
as current mismatches at the output node and switching errors at the pull up and pull
down networks. This work presents a novel transmission gate cascode current mirror
charge pump circuit. The switches incorporated in this work are Transmission Gates
which help to reduce various switching errors, and only one supply independent ref-
erence current source is used to have a minimum current mismatch. The performance
analysis carried out in the Cadence design environment, and it is observed that the loop
locks in 25 ns which is 50 % faster than the conventional charge pump. The control
voltage absolutely has no ripple in it after locking which reduces the reference spur
further. It could be achieved because the current mismatch is only about 7 %. This
PLL operates at 2.5 GHz having a wide lock range of 0.5–2.8 GHz where average
power consumption is 1.74 mW. Due to the use of cascade current mirror circuits, the
output voltage swing that can be obtained is 1.79 V.

Keywords Charge pump · Cascode current mirror · Current mismatch ·

Transmission gate · Lock in time

U. Nanda (B) · D. P. Acharya · S. K. Patra

Department of Electronics and communication Engineering,
National Institute of Technology, Rourkela 769008, India
e-mail: uk_nanda@yahoo.co.in
D. P. Acharya
e-mail: dpacharya@nitrkl.ac.in
S. K. Patra
e-mail: skpatra@nitrkl.ac.in
 Circuits Syst Signal Process

1 Introduction

Due to their wide range of advantages, charge pump phase locked loops (CP-PLLs) [4]
are widely used in current communication systems. Today all the wireless transceivers,
disk read-write channels, and other communication equipment are required to have a
fast locking and low noise PLL. A simple charge pump usually paired with a Phase
Frequency Detector (PFD) [7] as shown in Fig. 1 provides a wide lock range.
The operation of the circuit (Fig. 1) is as follows. The PFD generates either “Up”
or “Down” signal which switches the current of the charge pump. The D flip flops
make the PFD to generate Up and Down signal depending on the rising edge of the
CK Re f and CK Out , respectively. Now if both Up andDown are low, then both the
switches S1 and S2 will be off, and VCont remains constant. If Up is high and Down is
low, then IU p (UP current) charges the capacitor C P through S1 . Conversely, if Up is
low and Down is high, then I Down (DOWN current) discharges the capacitor through
S2 . Thus, if CK Re f leadsCK Out , then the output voltage of the charge pump increases
steadily and vice versa.
However, the charge pump should generate a constant current and supply to the
loop filter having the capacitor C P . But the current mismatch between pull up and
pull down network of the charge pump increases the glitches resulting in the static

CKRef
Up
IUp
S1
D
Flipflop

VCont

S2
CP
D
Flipflop
IDown
CK Out Down

Fig. 1 Simple charge pump with PFD architecture

Circuits Syst Signal Process

phase offset and dynamic jitter, known as reference spur [8] in PLL. This motivated
the designers to have a charge pump which will have a less current mismatch between
pull up and pull down network of the charge pump to lock faster and to have absolutely
no glitch in the control voltage of the Voltage Controlled Oscillator (VCO). To reduce
the current mismatch, they used only one current source [2,6] from which both the
charging and discharging current were derived. As the Up and Down switches are
responsible for charge injection [5], transmission gates are also used [9] to reduce the
non-ideal effects like charge injection and clock feed through, to get rid of the glitches
in control voltage of the VCO. Charge sharing is another non-ideal effect which leads
to current mismatch. It occurs due to the parasitic capacitances of the charge pump.
When the switches of the charge pump go from OFF to ON state, charge sharing
occurs between the parasitic capacitances of the charge pump and the output node due
to which the control voltage of the VCO deviates from its required value.

2 Conventional Charge Pump and its Non-Idealities

A simple charge pump consists of two current sources IU p and I Down and two switches
as shown in the Fig. 1. But in a conventional charge pump, the current sources are
realized by two MOSFETs (M1 , M4 )and the switches by NMOS M2 and PMOS M3
as shown in Fig. 2 by considering that a transistor biased with a constant voltage in
saturation can be implemented as constant current source. The inverter is inserted so
that the M3 will be on when Up is high. But the insertion of inverter introduces a delay
in path, thereby introducing a skew between Up and Down. To eliminate this effect,
a transmission gate is inserted between Down and M2 . Hence, delays of inverter and
transmission gate become equal.

Fig. 2 Conventional charge

pump
Vbp
M4

Up
M3
VCont

Down
TG M2

Vbn
M1
 Circuits Syst Signal Process

Fig. 3 Conventional charge pump non-ideal effects

Leakage current, current mismatch, and timing mismatch are the dominant non-
ideal effects of charge pump [8] on which the level of reference spurs of the PLL
depends. Switch errors due to current leakage, including charge injection, clock feed
through, and charge sharing are other non-ideal effects of charge pump [3]. In ON
state, the switch transistors M2 or M3 hold charge in their channels. But when they
are switched off partially, some charge will flow toward the drain terminal, causing
the load capacitor at the output of the charge pump to be charged up to some extent.
This gives rise to charge injection, which enhances the spikes in the control voltage.
When the switch transistors are in OFF state, the output of the charge pump floats.
When these transistors transit from OFF to ON, charge sharing occurs between the
parasitic capacitance and the output node of the charge pump resulting in a deviation
in the control voltage. Clock feed through is a result of the fast rise and fall of the
clock signal coupled into the signal node through the gate to source and gate to drain
parasitic capacitances. It raises the level of signal which could forward bias the PN
junction of the MOSFET, resulting in electron injection into the body of the MOS
causing faulty operation as it propagates through a nearby high impedance node [3].
The above described non-idealities of the charge pump give rise to the glitches
indicated in Fig. 3. Even after the PLL is locked, glitches are yet present, which can
introduce a formidable amount of reference spur. Hence, a high-performance charge
pump should be designed which will minimize these effects.
Several architectures are proposed in literature which are broadly classified into two
categories. Those are “Differential charge pump” and “Single-ended charge pump.”
Differential charge pumps [8] produce many advantages, but they suffer from some
critical drawbacks. They require two loop filters and common mode feedback circuitry.
Since more number of transistors are required, with two or more current sources, they
occupy a large silicon area. This also leads to higher power consumption. Single ended
charge pumps [8] have limited output voltage compliance range. For source charge
pump, if higher output voltage is desired, the charging and discharging current values
are to be enhanced. Switch mismatch results in timing mismatch as well as dead
zone. So, many modifications were done in single-ended charge pump to reduce these
limitations. Using gain boosting circuits [2,6], the current mismatch was controlled,
Circuits Syst Signal Process

but the other switching errors were not considered to improve reference spur. To
minimize these switching errors and also the current mismatch, Transmission Gate
charge pump (TGCP) [9] was designed where the switches are implemented using
transmission gate which are driven by complementary clock signals. Only one current
source is applied to reduce current mismatch. The high gain folded-cascode operational
amplifier (OP Amp) is added to this charge pump [9] to make the voltage V R E F to
follow the control voltage VC (voltage at output node or across the capacitor) at the
output of the charge pump. Although TGCP removes almost all non-ideal effects in
charge pump, use of Op Amp and a large bypass capacitor is not a wise move as it
consumes more power and silicon area. The level of reference spur is also higher than
source charge pump.
However, all the above-mentioned topologies did not mention about the output
voltage swing. Considering all these effects, a novel charge pump topology is proposed
which provides all the advantages and removes the limitations of TGCP.

3 Novel Transmission Gate Cascode Current Mirror Charge Pump

As current mirror is a primary component of a charge pump, an efficient current

mirror should have high output impedance, high output voltage compliance, low power
consumption, and no effect from power supply variation and noise. Considering many
topologies in literature, it is decided to use “Self Biased High Swing Cascode Current
Mirror” [1] because of its circuit simplicity.
Figure 4 shows the proposed charge pump topology. It has also a switch at the
source. Transistors M1 to M6 with T1 , T2 , and T D N form the DOWN network of
charge pump, where as transistors M7 -M10 with T3 and TU P form the complementary

Fig. 4 Proposed charge pump

topology

T3 Up TUp Up

Io
M10 M9

M8 M7
VOut
M2
M4 M5
M1
M3 M6

Down Down
T1 T2 TDown
 Circuits Syst Signal Process

Table 1 Aspect ratios of the

Transistors W/L Ratio
circuit elements
(nm/ nm)

M1 , M2, M3 , M4 , M8 , M10 360/100

M5 , M6 , M7 , M9 120/100
TUP , T Down (Both PMOS and NMOS) 120/100
T1 , T2 , T3 360/100

Fig. 5 Current reference circuit

M2 M3 M4
M1
I0
M7
M8
M5
M9
M6 IRef

Up part of the circuit. The current mirror used in this topology is discussed earlier
in this section. As in TGCP [9], switches are implemented using transmission gates
driven by complementary clock signals which removes the clock feed through effect.
The output node of the charge pump is not floating, when switches are off. In this work,
the current mismatch is avoided because both charging and discharging currents are
derived from the same reference current source. Transmission Gates T1 , T2 , and T3
are employed to reduce the mismatch caused due to insertion of TU P and T D N . The
glitches in current at the sources of output transistors (M5 and M7 ) while switching
TU P or T D N would not be conveyed to the output node because of the insertion of M6
and M9 . Transistors M5 and M7 would be turned on softly, since the rise and fall time
of current pulses is controlled by the RC time constants at their sources. Hence, this
is, therefore, a high speed charge pump avoiding switch errors.
The sizing of the transistors and transmission gates of the charge pump is tabulated
in Table 1. The W/L values of M1 to M4 are equal, and also sizes of T1 and T2 are
equal. But the W/L values of M5 , M6 , and T D N are 3 times smaller than M1 and T1 .
Similarly, sizes of M8 and M10 are equal, but 3 times higher than M7 and M9 . T3 is
3 times larger than TU P . All this sizing has been done so as to maximize effective
output voltage, remove current glitches, and to reduce the turn on time of the PFD.
Value of bias current is chosen such that the charge pump helps give optimum pull in
time for PLL.
The Current I0 is drawn from a current reference circuit [9] as shown in Fig.
5. It is a supply independent current source which provides biasing current for the
Circuits Syst Signal Process

Fig. 6 Physical design of the charge pump

charge pump. The W/L value of the transistors from M1 to M4 is (360/100) nm

and M5 to M9 is (120/100) nm. The current drawn from the current reference is
40 µA.

4 Post Layout Performance Analysis

The proposed charge pump is designed using 90 nm CMOS technology and simulated
with a 1.8 V power supply. The layout of the charge pump is shown in Fig. 6. Use of
high output impedance current mirror reduces the current mismatch between charging
(IU p ) and discharging (I Down ) currents. The current mismatch is recorded as 7 % for
the proposed charge pump and 20 % for the conventional one.
The transient analysis of the PLL is performed in Cadence Specter Analog Design
Environment and presented in Fig. 7. It is observed that the output voltage (vco_out)
swing is 0–1.79 V from a 1.8 V supply. The loop locks after 25 ns, and the con-
trol voltage of the VCO has no ripple in it after 50 ns reveals the fact of reduced
charge sharing and clock feed-through effect. To observe the superiority of con-
trol voltage variation of the modified charge pump, it is compared with the con-
ventional one by connecting both of the charge pumps to the same PFD, and the
results of comparison between the control voltage variations of both the charge pumps
are plotted in Fig. 8. Due to the stable characteristic after locking, the spur level
also could be minimized. Hence, we can say that the modified charge pump helps
the PLL to lock faster with reduced reference spur. Instead of two, only one cur-
rent source is used in this proposed charge pump which results only 1.7 mW of
 Circuits Syst Signal Process

Fig. 7 Transient analysis of the PLL

0.5
Control Voltage (VCont )

0.4

0.3

0.2

0.1 Modified Charge Pump

Conventional Charge Pump

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
-7
Time (Sec) x 10

Fig. 8 Comparison between the control voltage variations of both the charge pumps

average power consumption for the PLL. The power consumption plot is shown in
Fig. 9.
The phase noise variation with different offset frequencies is plotted in Fig. 10. The
phase noise is measured to be −87.1 dBc/Hz at 1 MHz offset, and the reference spur
is −57 dBc/Hz at 1.25 GHz offset frequency.
The proposed charge pump is compared with the conventional one with respect to
its phase noise performance analysis in Fig. 10. Here, it is observed that the noise level
is minimized by more than 10 %. The comparison table between the conventional and
proposed charge pumps is depicted in Table 2.
Circuits Syst Signal Process

Fig. 9 Power consumption plot

-55
-57.0
-60
______ Phase noise marker Modified Charge Pump
-65
Conventioanal Charge Pump
Phase Noise (dBc/Hz)

----------- Reference spur marker

-70

-75 -76.5

-80

-85 -87.1
-90

-95

-100 -101.0

-105
0 2 4 6 8 10
10 10 10 10 10 10
Offset frequency (Hz)
Fig. 10 Phase noise variation with different offset frequencies

Table 2 Performance comparison of both charge pumps

Parameters Fast frequency acquisition PLL OF 2.5 GHz range

Conventional CP Proposed CP

Technology CMOS 90 nm CMOS 90 nm

Frequency 2.5 GHz 2.5 GHz
Vdd 1.8 V 1.8 V
Current mismatch (%) 20 7
Lock range (GHz) 0.8–2.6 0.5–2.8
Lock in time (ns) 60 25
Phase noise (dBc/Hz @1 MHz offset) −87.1 −101.0
Reference spur (dBc/Hz @500 MHz offset) −57.0 −76.5
Power consumption (mw) 3.43 1.74
Layout area (µm2 ) of the CP 41.8 85.5
 Circuits Syst Signal Process

5 Conclusion

A high-performance transmission gate cascode current mirror charge pump is designed

and implemented using CMOS 90 nm technology. Due to its reduced non-ideal effects,
it can achieve better lock in time with reduced reference spur. The power consumption
also could be minimized due to the use of only one current source. A high swing
cascode current mirror circuit is used which results the output voltage of the charge
pump to range from 0 to 1.7 V from 1.8 V supply. This improved performance could
be achieved at the cost of more physical area of the charge pump.

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