CONTROLE DE PROJETOS Dep.

De Origem DATA: Página

Reservado para Cmos Drake ENGENHARIA 17/04/2008 1 de 7

1 2 3 4

+5VI -5VI

D33 HZ[1..6]
HZ[1..6]
MMBD4148SE 9
8 APEX_HZ HZ1
D R74 R176 U37C D
10
10K 2W 5K6 TLC2274ACD

10KpF

10KpF
+5VI 33pF R72

R177
C55

1.5KE62CA

20M
D15 100K 1%

C63
+5VI

C61
2M7
R70
CN14
-5VI
APEX +5VI 6
1 R73
-5VI STERNUM 7
GNDI 2 U37B
+5VI -5VI 5
3 6K81 1%

10KpF
TLC2274ACD
PAS
D30 -5VI
R63

C56
C137
MMBD4148SE

11
100KpF 100K 1%
R69 R171
3
10K 2W 5K6 U37A 1 STERNUM_HZ HZ2

1.5KE62CA

10KpF
2

R172
TLC2274ACD

20M
C130 D13 RA_HZ HZ3

C60
+5VI -5VI C133 LA_HZ HZ4
C +5VI C
LL_HZ HZ5
+5VI

4
-5VI V_HZ HZ6

4
100KpF
D20 100KpF MUX[0..11]
MMBD4148SE MUX[0..11]
2
R23
68K 2W 1 MUX0 RA 10K MUX
R143 U36A R31
RA 3
TLC2274ACD 10K 1%
33K +5VI -5VI
R140 220pF R26
MUX1 RA 5K MUX
1.5KE62CA

10K 1% R28
C37

D5 20M C128 4K99 1%

11
D21 MUX2 RA+LA/2 MUX
-5VI R27
MMBD4148SE 13 10K 1%
100KpF 14 MUX3 LA 10K MUX
R30 R150 U36D R37
LA -5VI 12
10K 1%
68K 2W 33K R33

1.5KE62CA

220pF
+5VI -5VI R145 TLC2274ACD MUX4 LA 5K MUX
10K 1% R41

C39
20M
D9 4K99 1%
CN13 D22 MUX5 LA+LL/2 MUX
MMBD4148SE R36
6 -5VI
B 6 R40 10K 1% B
LA 68K 2W 7 MUX6 LL 10K MUX
5 R156 U36B R46
LL LL 5
4 10K 1%
RA 33K +5VI -5VI
3 R43
220pF

V R154 TLC2274ACD MUX7 LL 5K MUX

1.5KE62CA

2 10K 1% R48
C43

RL D10 20M
1 D23 4K99 1%
MUX8 RA+LL/2 MUX
R45
ELETRODOS MMBD4148SE 9
10K 1%
8 MUX9 V 5K MUX
R47 R160 U36C R146
V -5VI 10
15K 1% 4K99 1%
68K 2W 33K TLC2274ACD R148
1.5KE62CA

220pF
R159
+5VI -5VI 20M
C44
15K 1%
D12 MUX10 RA+LA+LL/3 MUX
R147

R141 15K 1%
-5VI
D26
R51 R168 MMBD4148SE
RL MUX11 RL_RETORNO
68K 2W 33K
D11 Title
A A
1. 5KE62CA

Circuito de entrada dos Eletrodos com buffers para o ECG

Size Number Revision

DSP210 07B
A4
Date: 12-Dec-2007 Sheet 5of 9
File: D:\Backup Cmos Drake\Projetos\DSP200\DSP210\DSP210.00\Hardware\DSP210.07B
Drawn By: \DSP210_07.ddb
1 2 3 4
 CONTROLE DE PROJETOS Dep. De Origem DATA: Página
Reservado para Cmos Drake ENGENHARIA 17/04/2008 2 de 7

1 2 3 4

+5VI
R178
+5VI
CN300 100K 1% +5VI
CON3
R80
-5VI

1
2
3
49K9 1%
-5VI
D GNDI D
HZ[1..6] 13
HZ[1..6] R173
U37D 14 DT0
HZ1 12 D-PP
100K
HZ2 D14 DT[0..6]
TLC2274ACD Pás DT[0..6]
D41 MMBD4148
Presença 0
CT[0..9] +5VI -5VI 1N4733A
CT[0..9] Ausência 1

16
U20 U24C

7
MUX[0..11] CD4051BCM M74HCT4053M1R
MUX[0..11]
13 5 +5VI
I/O 0 cx R66

VEE
VCC
LA 10K MUX MUX3 14 4 C46
I/O 1 c
LL 10K MUX MUX6 15 3 3
I/O 2 O/I cy R65 130K 1%

C
12
I/O 3
RA 5K MUX MUX1 1 11

7
I/O 4 A R161 100KpF 330KpF5% 2K 1%
LA 5K MUX MUX4 5 10 3 6
I/O 5 B

9
LL 5K MUX MUX7 2 9 CT3 8 C49 U26B 7
I/O 6 C 20K 1% R50 R82

VS S
V 5K MUX MUX9 4 6 C-S U23 6 5
C I/O 7 INH C
1 AD623AR -5VI +5VI TLC2274ACD
R163 10K 1% 10K 1%
2 R55 R165
4K99 1%

5
CT9 U24B 1M1% 10M1%

8
R155 20K 1% C45
S-CAL M74HCT4053M1R +5VI

0, 05Hz
4

16
0, 5Hz
R157 2

8
bx

CD74HC T4066M

CD74HC T4066M
1R1% 15 U27A U27B U24A
b 100KpF
1 14 12
by +VCC ax

VEE

+VCC
OUT

OUT

GND
B
-5VI 14
a
7 13
GND ay

IN

IN
10

C
6
E

A
+5VI -5VI
M74HCT4053M1R

4
13
0 =x

11
16

U18 1 =y
7

CD4051BCM

CT3

CT4

CT4

CT5
13 C-S C-PR C-PR C-PA
I/O 0
VEE
VCC

RA 10K MUX MUX0 14

I/O 1
15 3
B I/O 2 O/I B
LA 10K MUX MUX3 12
I/O 3
LA+LL/2 MUX MUX5 1 11 CT0 C-A0
I/O 4 A
RA+LL/2 MUX MUX8 5 10 CT1 C-A1 C51
I/O 5 B 10KpF 1%
RA+LA/2 MUX MUX2 2 9 CT2 C-A2
I/O 6 C
VS S

RA+LA+LL/3 MUX MUX10 4 6 Fc = 80Hz

I/O 7 INH
TLC2274ACD
R169 R67
10
8 FT1 FT0
8

200K 1% 200K 1% U26C

9 ECG-FPB ECG-SF

R68
U23 AD620AR ==> R60 = 3K92 1% C50 R170 10K 1%
R81 C64 U23 AD623AR ==> R60 = 8K25 1% 100K 1%
10KpF 10KpF 1% FT[0..1]
1K 1% FT[0..1]
1M1%
R75 R61
Title
A R64 20K 1% A
13 R60 Circuito dos Multiplexadores e Amplificadores do ECG
MUX11 14 8K25 1%
U26D 10K 1% R59
RL_RETORNO 12 Size Number Revision
DSP210 07B
20K 1% A4
TLC2274ACD
Date: 12-Dec-2007 Sheet 6of 9
File: Drawn By:
D:\Backup Cmos Drake\Projetos\DSP200\DSP210\DSP210.00\Hardware\DSP210.07B\DSP210_07.ddb
1 2 3 4
 CONTROLE DE PROJETOS Dep. De Origem DATA: Página
Reservado para Cmos Drake ENGENHARIA 17/04/2008 3 de 7

1 2 3 4

FILTRO 60 Hz C35 FILTRO 35 Hz

100KpF
-5VI

4
C36
100KpF
+5VI
2
D D
C124 1 -5VI +5VI

8
U17A
1KpF 1% 3 C121
C127 1n5F 1% 3 TLC2272ACD
TLC2272ACD

16
1KpF 1% R134 U15A 1 U15C

8
C122 U16A

3M01 1%
2M71 % 2 M74HCT4053M1R

R130
C38 1n5F 1%

8
FT1 12 5
+5VI ax cx

VEE

GND

VCC
ECG-FPB 14 R24 4
R142 100KpF a c
FT[0..1] R135 13 C29 1K 1% 3

4
FT[0..1] 2M7 ay R132 cy

C
1K 1%

2M71 %

2M71 %
3M01 1% -5VI

3M01 1%
1n5F 1%

1n5F 1%
6

R137

R138
C126 E

A
100KpF

9
3M01 1%
1KpF 1%

R126

R125
5 CT7
M74HCT4053M1R

11
7 CT6

C116

C115
U17B
6 C-F60 5 C-F35
C125 R133
TLC2272ACD 7
1KpF 1% 10K 1% U16B
6
R25
TLC2272ACD 10K 1%
C C

U15B
M74HCT4053M1R
2
bx
15
b
1
by
B

+5VI C34 ECG-FIL

R136 ECG-FIL
100K 1%

8
10

100KpF
+5VI
3
R22
U14A 1 ECG-A
ECG-A
-REF R139 2
4K99
B 100K 1% TLC2272ACD B
R21 R128 10K 1% C26
270R 100KpF

4
CT[0..9]
CT[0..9] R127
CT8 6 -5VI
R129
REF. 2,5V 7
10K 1% U14B R131
C113 5
C28 100K 1%
+ TLC2272ACD
100K 1%
U13

10uF /10V
-REF

TANT

100KpF
TL431
-REF

+5VI
+5VI

-5VI
-5VI
GNDI
Title
A A
Circuito dos Filtros de 35Hz e 60Hz do ECG

Size Number Revision

DSP210 07B
A4
Date: 12-Dec-2007 Sheet 8of 9
File: Drawn By:
D:\Backup Cmos Drake\Projetos\DSP200\DSP210\DSP210.00\Hardware\DSP210.07B\DSP210_07.ddb
1 2 3 4
 CONTROLE DE PROJETOS Dep. De Origem DATA: Página
Reservado para Cmos Drake ENGENHARIA 17/04/2008 4 de 7

1 2 3 4
HZ[1..6]
HZ[1..6] TLC2274ACD
RA_HZ HZ3 9
R39
-5VI 8 DT3
R151 U21C
10 D-RA
4K99
D7
100K 1%
1 C52 TLC2274ACD
3 10
D MMBD4148CA D
2 8 13 U22A
TLC2274ACD 220KpF U25C R79
9 +5VI 14 1
U25D A
LA_HZ HZ4 6 12 +5VI 2 13 DT1
R38 1n5F 4K7 1% B Q
7 DT4 R56 C54 TLC2274ACD 3 4 D-MP
U21B CLR Q

49K9 1%
5 D-LA 10K 14
4K99 Cext
15 +5VI

R78
Rext/Cext
R54
TLC2274ACD 10M1% 8 16

1
MMBD4148CA
MMBD4148CC
GND VCC
HZ5 13
R53 MM74HC123A
LL_HZ 14 DT5 C47

10K 1%
U21D
12 D-LL 220KpF5%
4K99

R71
C129 D29 D28
D32
1
+5VI

3
3 MMBD4148CA
100KpF 2 R166 R167
4
100K 100K +5VI
V_HZ HZ6 2
R52 +5VI
1 DT6 D8
R152 U21A
3 D-V MMBD4148CA
C TLC2274ACD 4K99 C
47K 1% -5VI +5VI 1
3
-5VI
2
11

C131 -5VI
-5VI
R149
100KpF
GNDI
FT[0..1] 120K 1%
FT[0..1] 0R
ECG-SF FT0
R57
TLC2274ACD 6 D6
0R R42
ECG-FPB FT1 13 7 MMBD4148
R62 U19B
U19D 14 5
0R 12K 1%
ECG-FIL 12
ECG-FIL R200 R35
TLC2274ACD
0R 22K1 1%
R201
2
C57 100KpF1% 3
D24
+5VI MMBD4148CA 1 R144 C40
R77
+5VI C59 MMBD4148CA 100R
R164 100KpF 316K 1% C42 -5VI 470KpF5%
2
3

B +5VI 100KpF B
820K 3 D25
C132 MMBD4148CA D31 1 9 U22B
4

R29

11
150KpF 6 C136 U19C 8 9 DT[0..6]
R175 R158 A DT[0..6]
7 2 10 +5VI 10 5 DT2
2

C53 U25B R76 3K3 B Q

5 1 3 10K 11 12 D-OR
1

79K6 1% 100KpF1% U25A CLR Q

MMBD4148CC D27 3 6K81 1% 1 TLC2274ACD 6
470KpF TLC2274ACD U19A Cext
TLC2274ACD 2 7
R174 TLC2274ACD Rext/Cext
R49
R58 24K9 1% C58 C62 +5VI 1M8 1% MM74HC123A
3

11

1M5 R162 470KpF5% C41

-5VI
4

820K 100KpF C48

100KpF R34 R32
R194 -5VI 18K 1% 100KpF1%
1M1%
100K 1% C135 +5VI
100KpF R44 R153
-5VI
11

R195 12K 1% 120K 1%

3
100K 1% R198
U26A 1 ECG-SMP
ECG-SMP
-REF 2 Title
A R196 4K99 A
TLC2274ACD Circuito de deteção de onda "R" e Marcapasso do ECG
-REF 100K 1% C134
100KpF Size Number Revision
4

-REF +5VI
DSP210 07B
A4
R197 100K 1% Date: 12-Dec-2007 Sheet 7of 9
File: Drawn By:
D:\Backup Cmos Drake\Projetos\DSP200\DSP210\DSP210.00\Hardware\DSP210.07B\DSP210_07.ddb
1 2 3 4
 CONTROLE DE PROJETOS Dep. De Origem DATA: Página
Reservado para Cmos Drake ENGENHARIA 17/04/2008 5 de 7

1 2 3 4 5 6 7 8

PF[0..15]
PF[0..15]
+3.3V
R189
I/O[1..3] Q2

3
I/O[1..3]
IRLML2502

8
10K
S[0..3] U33
S[0..3]

VDD
1 OFF PF14 PF6 /CSTMP 2 7
CS ID
I/O1 SCK 3
SCLK
D +3.3V I/O2 MISO 5 D
R115 SDO
+5V TANT TANT +3.3V +3.3V I/O3 MOSI 6 AD7314ARM

2
SDI

GND
C22 C24 C23 C21
10K
R10 100KpF 100KpF +3.3V
220R CN7

10uF /10V
10uF /10V
R15 R116

4
6
C14 + + C107 4K7 4K7 R314
+ C110 5
R11 10K
4 R316
2K2 10uF/10V SCK PF1 PF6 Inibe 2 minutos

100KpF

100KpF
R5 3
TANT SDA PF0
2 R114 R315 100R
PF5 PF11 Congela
0R 1 470R +3.3V
C111 AGND C139
220pF 10K
330KpF AGND +3.3V I2C D18 PF15 R317

25

38

26

42
100R

9
R313

BEEP
R118 U5 R202 LED Alarme
R12 13 14
100K R304 +3.3V +3.3V
470K 11 12 330R

AVdd1

AVdd2

AVss1

AVss2

DVss1

DVss2

DVdd1

DVdd2
10K MMBD4148SE 100R
9 10
12 I/O1 SCK
100KpF PC_BEEP 7 8
I/O3 MOSI
5 6
23 11 PF11 Reset Codec /CSMMSou SINC ON +3.3V
+5V LINE_IN_L RESET 3 4
I/O2 MISO
8

1 2
C19 AGND 24
LINE_IN_R SDATA_OUT
5 S3 SDATA_OUT
2 C12 MMS CN6
R190
U6A 1 21 8 S1 SDATA_IN
MIC1 SDATA_IN +3.3V
VREF 3
330KpF 10K
AD8532AR 22 10 S0 SYNK +5V
MIC2 SYNC
R312
C25 18 6 BIT_CLK S2 9,84<Vo<13,94
4

C CD_L BIT_CLK C
100KpF Faixa = 33 Pontos

7
47R
20 DV = 0,125V
CD_R C146 C145 +3.3V +5V 10
U7

SHDN
VDD
AGND 19 45 47pF 18pF A
CD_GND_REF CS0

24
/CS_POT 4 10K AD5201BRM10

1
CS
16 AD1881AJST 46 U35 SCK 6 W 9
VIDEO_L CS1 CLK
MOSI 5
SDI

VCC A

VCC B
17 47 R311
VIDEO_R EADP

GND
VS S
10M B 1
14 48 D0 3 21 DB0
AUX_L MODE A1 B1
D1 4 20 DB1 +5V
A2 B2
15 D2 5 19 DB2

3
AUX_R A3 B3
D3 6 18 DB3
A4 B4
13 D4 7 17 DB4 R117
PHONE_IN A5 B5
39 D5 8 16 DB5 18K
LNLVL_OUT_L A6 B6
37 D6 9 15 DB6
MONO_OUT A7 B7
41 D7 10 14 DB7
LNLVL_OUT_R A8 B8 R13
36 CN9
LINE_OUT_R
C10 VREFOUT AM6 /ARE 2 200K
DIR R119 82K

XTL_OUT
220KpF 35 AM3 /AMS3 22

XTL_IN
AF ILT1

AF ILT2

LINE_OUT_L OE
FILT_R

FILT_L

CX3D

RX3D

VREF
0R

GND

GND

GND
R14 CN10 +5V
R4 0R
1 2
22K SN74LVCC3245ADW C/D
3 4
C17 RD WR
R301 5 6
3

2
29

30

31

32

34

33

VREF 28

27

11

12

13
C140 DB0 DB1
470pF 7 8
+ + DB2 DB3
100KpF + 10M 9 10
B C103 X3 DB4 DB5 B
11 12
270pF 24,576MHz DB6 DB7
13 14
NPO C20 CE RES
R6 15 16
AGND C18 C109 47KpF AGND C106 +5V LC
220K 17 18
C105 TANT TANT C16 TANT
19 20 R20 +5V

20
100KpF

270pF
10uF /10V
1uF/16V

1uF/16V

R308
+5V NPO C108 U34 Display
100KpF 22R 22R
C104 22pF

VCC
22pF NPO AM6 /ARE 2 18 RD
A1 Y1
NPO AM3 /AMS3 4 16 CE
6

A2 Y2
4 C13 AGND 0=ON AM7 /AWE 6 14 WR
- A3 Y3
1=OFF A1 8 12 C/D
A4 Y4
+V

U4 5 CN8 1
VOutA OE
+3.3V
1 Saida som
SSM2211S 8
VOutB 2 Alto Falante 8R
Bypass

11 9 LC
A1 Y1
-V

3 CN15 PF12 13 7 RES

+ A2 Y2
PF9 15 5
1

1 Saida som A3 Y3
17 3
7

2 Microfone Electret A4 Y4
19 +3.3V
2

OE

GND
AGND
+3.3V
C15
100KpF SN74HC244DW +5V

10
+5V
AGND

A GNDNI A

Códigos de Capacitores VISHAY

C18,C109 - 292D105X_016R2 Title

D[0..15] C23,C24,C106,C110 - TAJA106K010 Circuito do CODEC(voz) para o DSP
D[0..15]
AM[0..7] Size Number Revision
AM[0..7]
DSP210 07B
A3
A[1..19]
A[1..19]
Date: 12-Dec-2007 Sheet 4of 9
File: D:\Backup Cmos Drake\Projetos\DSP200\DSP210\DSP210.00\Hardware\DSP210.07B
Drawn By: \DSP210_07.ddb
1 2 3 4 5 6 7 8
 CONTROLE DE PROJETOS Dep. De Origem DATA: Página
Reservado para Cmos Drake ENGENHARIA 17/04/2008 6 de 7

1 2 3 4 5 6 7 8

D D

MI[1..5]
MI[1..5]
D[0..15]
D[0..15]
A[1..19]
A[1..19]
AM[0..7] C8 +3.3V C9 +3.3V C7 +3.3V
AM[0..7]
C87 100KpF C88 100KpF 10uF/10V
SM[0..6] TANT TANT C6 TANT
SM[0..6]
+ + + C4

100KpF
10uF /10V

10uF /10V
+3.3V 100KpF

37

37
CN5 U31 U32

14
27

43
49
1

3
9
GND1

VCC

VCC
D3 2 A1 25 29 D0 A1 25 29 D0 U2
D3 A0 Q0 A0 Q0
D4 3 A2 24 31 D1 A2 24 31 D1
D4 A1 Q1 A1 Q1

VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
D5 4 A3 23 33 D2 A3 23 33 D2 A1 23 2 D0
D5 A2 Q2 A2 Q2 A0 DQ0
D6 5 A4 22 35 D3 A4 22 35 D3 A2 24 4 D1
D6 A3 Q3 A3 Q3 A1 DQ1
D7 6 A5 21 38 D4 A5 21 38 D4 A3 25 5 D2
D7 A4 Q4 A4 Q4 A2 DQ2
AM2 /AMS2 7 A6 20 40 D5 A6 20 40 D5 A4 26 7 D3
C CS1 A5 Q5 A5 Q5 A3 DQ3 C
A10 8 A7 19 42 D6 A7 19 42 D6 A5 29 8 D4
A10 A6 Q6 A6 Q6 A4 DQ4
AM5 /AOE 9 A8 18 44 D7 A8 18 44 D7 A6 30 10 D5
OE / ATASEL A7 Q7 A7 Q7 A5 DQ5
A9 10 A9 8 30 D8 A9 8 30 D8 A7 31 11 D6
A9 A8 Q8 A8 Q8 A6 DQ6
A8 11 A10 7 32 D9 A10 7 32 D9 A8 32 13 D7
A8 A9 Q9 A9 Q9 A7 DQ7
A7 12 A11 6 34 D10 A11 6 34 D10 A9 33 42 D8
A7 A10 Q10 A10 Q10 A8 DQ8
13 A12 5 36 D11 A12 5 36 D11 A10 34 44 D9
VCC1 A11 Q11 A11 Q11 A9 DQ9
A6 14 A13 4 39 D12 A13 4 39 D12 SM5 SA10 22 45 D10
A6 A12 Q12 A12 Q12 A10 DQ10
A5 15 A14 3 41 D13 A14 3 41 D13 A12 35 47 D11
A5 A13 Q13 A13 Q13 A11 DQ11
A4 16 A15 2 43 D14 A15 2 43 D14 A13 36 48 D12
A4 A14 Q14 A14 Q14 A12 DQ12
A3 17 A16 1 45 D15 A16 1 45 D15 50 D13
A3 A15 Q15 A15 Q15 DQ13
A2 18 A17 48 A17 48 A18 20 51 D14
A2 A16 A16 BA0 DQ14
A1 19 A18 17 A18 17 A19 21 53 D15
A1 A17 A17 BA1 DQ15
20 A19 16 A19 16
A0 A18 R100 A18 R103
D0 21 9 47 9 47
D0 A19 BYTE +3.3V A19 BYTE +3.3V
D1 22 10 10 SM2 /SWE 16 15 /ABE0 MI1
D1 A20 10K A20 10K WE DQML
D2 23 SM1 /SCAS 17 39 /ABE1 MI2
D2 CAS DQMH
PF[0..15] 24 AM7 /AWE 11 12 RST0 /RESET AM7 /AWE 11 12 RST0 /RESET SM0 /SRAS 18
PF[0..15] WP / IOIS16 WE RESET WE RESET RAS
25 AM5 /AOE 28 AM5 /AOE 28 SM6 /SMS 19
CD2 OE OE CS
PF8 26 AM0 /AMS0 26 AM1 /AMS1 26 SM3 SCKE 37
CD1 CE CE CKE
D11 27 AM4 ARDY 15 AM4 ARDY 15 SM4 CLKOUT 38

VS SQ
VS SQ
VS SQ
VS SQ
D11 RY/BY RY/BY CLK

VS S
VS S
VS S
D12 28
D12

GND

GND

GND

GND
D13 29
D13
D14 30
D14
D15 31 MX29LV800BTC-70 MX29LV800BTC-70 48LC16M16A2-75

6
D15

28
41
54

12
46
52
AM2 /AMS2 32 FLASH_1MB_512X16 FLASH_1MB_512X16 SDRAM_64-512MB_8X16X4
CS2

27

46

27

46
33
VS1
34
IORD
B 35 B
IOWR
AM7 /AWE 36
WE
PF7 37
RDY/BSY / INTRQ
38
VCC2
RST1 RESET 0R 39
R96 CSEL
40
VS2
RST0 /RESET 0R 41
R99 RESET / RESET
42
PF5 Reset CF 0R IORDY
R203 43
INPACK
A11 44
REG
45
BVD2 / DASP
46
BVD1 / PDIAG Códigos de Capacitores VISHAY
D8 47
D8
D9 48
D9 C7,C87,C88 - T AJA106K010
D10 49
D10
50
GND2
MI20A-50PD-SF-EJR

RST[0..1]
RST[0..1]

A +3.3V A
+3.3V

Title
Circuito das expansões de Memória para o DSP
GNDNI
Size Number Revision
DSP210 07B
A3
Date: 12-Dec-2007 Sheet 3of 9
File: D:\Backup Cmos Drake\Projetos\DSP200\DSP210\DSP210.00\Hardware\DSP210.07B
Drawn By: \DSP210_07.ddb
1 2 3 4 5 6 7 8
 CONTROLE DE PROJETOS Dep. De Origem DATA: Página
Reservado para Cmos Drake ENGENHARIA 17/04/2008 7 de 7

1 2 3 4 5 6 7 8
C95 C94 C93 C92 C80 C74 C75 C78 C84 C86 C96 C89 C82 C77 C90 C97 C79 C83 C76 C81 C91 BMOD1 3 2
+3.3V
R182
VDDEXT VDDINT TANT 10K So0 MMBD4148SE

10uF /10V

10uF /10V

10uF /10V
R3

100KpF

100KpF

100KpF

100KpF

100KpF

100KpF

100KpF

100KpF

100KpF

100KpF

100KpF

100KpF

100KpF

100KpF

100KpF

100KpF

100KpF
100KpF
C5 SN74HC126D 10K So1 D35 +3.3V
+3.3V L3 U39A
100uF/10V R183 So2
0R

1
+3.3V C73
R184 100KpF
+ + + + 10uH 0 = SPI D34

5
6
7
8
10K

19
1 = FLASH MMBD4148SE

So2
So1
So0
C71

So0

So1

100KpF
TANT D17 100KpF

ZHCS1000 - 1A
2 3
C1+ V+

IRF7404
D3 +3.3V +3.3V +3.3V
BAT54C

470R
C67 7

107
118
134
145
156
171

111
143
157
168
BT1 -V

470R
12
20
31
45
57
71
93

25
52
66
80

18

19
17
15
13
11
A[1..19] SR220 4 C70

1
8
6
4
2

100KpF
A[1..19] D42 C1- D36

470R
D U3 U38 5 11 100KpF R187 D
+ Q1 C2+ Status MMBD4148SE
20 CN3

R186
BATERIA +3.3V

4
3
2
1
ShutDown +3.3V

VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT

VDDRTC

A4
A3
A2
A1

A4
A3
A2
A1
VDD INT
VDD INT
VDD INT
VDD INT
VDD INT
VDD INT
VDD INT
VDD INT

OE

OE
D[0..15] A1 149 4 +3.3V +3.3V C68 14

R185
D[0..15] ADDR1 VROUT2 R101 ONLine 1
A2 148 5 10 20 6 1
ADDR2 VROUT1 GND SN74HC244DW VCC C2- EN 2
A3 147
ADDR3 C85 0R 3
MI[1..5] A4 146 TX_IO 13 17 TX0_IO

Y4
Y3
Y2
Y1

Y4
Y3
Y2
Y1
MI[1..5] ADDR4 T1in T1out 4
A5 142 100KpF TX_DBI 12 8 TX1_IO
ADDR5 T2in T2out 5
A6 141 81 TX_DSP 15 16 RX0_IO
ADDR6 TX R1out R1in 6
AM[0..7] A7 140 82 RX_DSP 10 9 RX1_IO

3
5
7
9
AM[0..7] ADDR7 RX R2out R2in 7

12
14
16
18
A8 139 +3.3V U39D
ADDR8 8
A9 138 12 11 U29 RS232
ADDR9
SM[0..6] A10 137 65 SP3223ECY RJ45 RS232
SM[0..6] ADDR10 RSCLK1 R86

18
A11 136 64 RX_DBI SN74HC126D
ADDR11 RFS1 10K U39B 6 MMBD4148SE
A12 135 63 5 RX_ECG R95 R85

13
ADDR12 DR1PRI D16
A13 127 62 SN74HC126D 10K 470R RX1_5
ADDR13 DR1SEC
A14 126 61 8 9 TX_ECG +3.3V
ADDR14 TSCLK1
A15 125 60 SN74HC126D +5V

TX_ECG
RX_ECG
ADDR15 TFS1 U39C
A16 124 59 TX_DBI
ADDR16 DT1PRI +5V 1 2

20
A17 123 58

10
ADDR17 DT1SEC 3 4
A18 122
ADDR18 5 6
A19 121 TX_DBI +3.3V
ADDR19 7 8

VCC
76 S[0..3] 2 18 TX_DBI_5
RSCLK0 S[0..3] A1 Y1 9 10
75 SYNK S0 PF4 4 16 /RESET_DBI_5
RFS0 A2 Y2 11 12
D0 116 74 SDATA_IN S1 PF10 6 14 SINC_DBI_5
DATA0 DR0PRI A3 Y3 13 14
D1 115 73 +3.3V PF3 8 12 ECG2
DATA1 DR0SEC A4 Y4
D2 114 72 BIT_CLK S2 1 /RESET_ECG_5
DATA2 TSCLK0 OE
D3 113 69 ECG1 CN1
DATA3 TFS0 10K 10K 10K
D4 112 68 SDATA_OUT S3 ECG0 DBI100
C DATA4 DT0PRI R88 C
D5 110 67 11 9 D39
DATA5 DT0SEC A1 Y1 R199

R89

R87

R83
D6 109 4K7 1% CN2 13 7 ECG[0..2] R309
DATA6 A2 Y2 470R ECG[0..2]
D7 108 JTAG PF10 15 5 470R
DATA7 A3 Y3
D8 105 87 TDO 17 3
DATA8 TDO 14 13 A4 Y4 LED AMARELO
D9 104 86 TDI 19
DATA9 TDI 12 11 OE

GND
D10 103 84 TRST
DATA10 TRST 10 9
D11 102 94 TCK +3.3V Boot Load
DATA11 TCK 8 7 R188
D12 101 85 TMS U1 +12V
DATA12 TMS 6 5
D13 100 83 EMU +3.3V SN74HC244DW

8
DATA13 EMU 4 3 R90 10K +12V

10
+3.3V D14 99
DATA14 2 1
D15 98 PF2 1
DATA15 10K CS

VCC
ADSP-BF532SBST-400 53 I/O1 SCK SCK 6 3 +5V
SCK SCK WP
54 I/O2 MISO MISO 2 7
R109

MISO SO HOLD +5V

R98

R97

MI1 /ABE0 151 55 I/O3 MOSI MOSI 5

ABE0 MOSI SI

VS S
10K 10K 10K MI2 /ABE1 150
ABE1
MI3 /BR MI3 /BR 163 TMR[0..2] C138 +3.3V
BR TMR[0..2]

I/O2 MISO
I/O3 MOSI
MI4 /BG MI4 /BG 119 79 TMR0 U40 100KpF

I/O1 SC K
BG TMR0 +3.3V
MI5 /BGH MI5 /BGH 120 78 TMR1 +3.3V R9 25LC640IP

4
BGH TMR1 10K
77 TMR2 PF12 10K R8 +3.3V
TMR2 10K 10K R307
+3.3V PF3 PF6 10K
R106 10K 10K R305
AM0 /AMS0 161 PF4
AMS0 R107 R306 GNDNI
AM1 /AMS1 160 51 PF0 R310
AMS1 PF0 +3.3V
R102 AM2 /AMS2 159 50 PF1 10K
AMS2 PF1 R7 10K
10K AM3 /AMS3 158 49 PF2 CS_BOOT PF4 Disparo simulador DEA
AMS3 PF2
AM4 ARDY AM4 ARDY 162 48 PF3 /RESET_ECG +3.3V D40
ARDY PF3
AM5 /AOE 154 47 PF4 /RESET_DBI I/O[1..3]
AOE PF4 I/O[1..3]
AM6 /ARE 153 46 PF5
ARE PF5 R93
B AM7 /AWE 152 38 PF6 /CS_TMP MMBD4148 RST[0..1] B
AWE PF6 10K RST[0..1]
37 PF7 U30 +3.3V
PF7 R2 R302
SM0 /SRAS 167 36 PF8 1 8 RESET RST1
SRAS PF8 MR WDO
SM1 /SCAS 166 35 PF9 SINC_ECG
SCAS PF9 220R C69 10K
SM2 /SWE 165 34 PF10 SINC_DBI 2 7 \RESET RST0
SWE PF10 100KpF VCC RESET
SM3 SCKE 173 33 PF11 S1
22R 169 SCKE PF11
SM4 CLKOUT 32 PF12 RESET 3 6

3
R110 CLKOUT PF12 GND WDI
SM5 SA10 164 29 PF13 PF13 /SRESET V=4,44Volts +3.3V
SA10 PF13 R204 R94
SM6 /SMS 172 28 PF14 4 5 Q4 CARGA MAXIMA DO +3,3V
SMS PF14 R92 PFI PFO
27 PF15 PF15 /PFO 10K IRLML2502
PF15 4K7 1% 0R
RST0 13 ADM706SAR 1 ADS533 ==> 130mA
RESET
NMI 14 22 PPI0 AD1881A ==> 23mA
R108 NMI PPI0 R91
BMOD0 96 23 PPI1 CFA45 ==> 40 mA
10K BMOD0 PPI1 R303
BMOD1 95 24 PPI2 MX29LV800 ==> 2 X 50mA

2
BMOD1 PPI2 12K 1%
26 PPI3 MT48LC32M16 ==> 175mA
PPI3 10K
+3.3V 21 PPI4 PF[0..15]
PPI_CLK PF[0..15]
11 +12V TOTAL ==> 471mA
XTAL
10 D2 CN4
BMOD1

CLKIN 1N5817
R113 R111 +3.3V +5V
L1 L2 1
10K 10K 17 U28 R84
RTXI 0,7A 2 1
16 1 8 10K FU2
RTXO SWITCH IN 3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

R193 22uH 22uH

C3 4 1

220uF/10V
C65 2 7 + C66 FU1
+ 220KpF BOOST GND C72 5
C1
6
100uF/10V 3 6 100KpF 100KpF
BIAS SD
1
2
3
7
8
9

106
117
128
129
130
131
132
133
144
155
170
174
175
176
15
19
30
39
40
41
42
43
44
56
70
88
89
90
91
92
97

470R D1 Alimentação
JP2 JP1 1N4148 4 5 Códigos de Capacitores VISHAY
BMOD0 BMOD1 10M R179 FB COMP
X2 R181 C2
R112 xx R1
A 20MHz X1 +5V xx ADP3050AR-3.3 1KpF C1,C3 - EKE00BA322C00 A
Tabela BOOT S2 S1 S0 Modo 7K5
DEFAULT BOOT MODE = 32,768KHz C5 - EKE00PB347C00
PROM BOOT PPI[0..4] C77,C82,C90 - TAJA106K010
JP1 JP2 Modo x 0 0 Não Usar PPI[0..4]
R180
M1 M0 x 1 0 DSP/RS Tabela de Resistores
C100 C99 GND xx Title
22pF 12pF 0 0 EXT Mem x 0 1 ECG/RS R179 R180 R181
Circuito do DSP
0 1 FLASH 1 x 1 1 DSP/ECG ADP3050AR 18K 1% 10K 1% Não Montar
C101 C98 1 0 Reservado 0 x x Boot SPI ADP3050AR-3.3 0R Não montar 0R
22pF 12pF Size Number Revision
1 1 SPI EEProm 1 x x Boot Flash
DSP210 07B
A3
Date: 12-Dec-2007 Sheet 2of 9
File: D:\Backup Cmos Drake\Projetos\DSP200\DSP210\DSP210.00\Hardware\DSP210.07B
Drawn By: \DSP210_07.ddb
1 2 3 4 5 6 7 8