1

CS & IT Hinglish
Digital Logic DPP - 1

Number System
1. The two addition operations 24 + 14= 41 and 23 + 12 7. The greatest negative number, which can be stored
= 101 are performed on number bases b1 and b2 in a computer that has 8-bit word length and uses 2's
respectively. The values of b1 and b2 are respectively complement arithmetic, is
(a) 7 and 4 (b) 4 and 7 (a) -256 (b) -255
(c) 8 and 4 (d) 4 and 8 (c) -128 (d) -127

2. If x and y are successive numbers in a number system 8. F’s complement of (2BFD)hex is

of base b such that (xy)b = (25)10 and (yx)b = (31)10, (a) E304 (b) D403
then (c) D402 (d) C403
(a) x = 4, y = 5 and b = 7
(b) x = 3, y = 4 and b = 6 9. The result of addition operation 34 + 43 performed on
(c) x = 4, y = 5 and b = 6 minimum base is stored in an 8-bit register. The
(d) x = 3, y = 4 and b = 7 content of register will be
(a) 01000011 (b) 00101010
3. If a = (4.4)5 and b = (3.3)5, then a + b = (x)5. The (c) 01010101 (d) 01010100
subscript 5 denotes the base on which the
corresponding number is expressed. The value of x is 10. Which of the following is equal to (AB)16 ?
(a) 31.2 (b) 7.2 (a) (B7)16 – (A)16 (b) (B5)l6 – (A)16
(c) 8.7 (d) 13.2 (c) (A0)16 + (D)16 (d) (BA)16 + (01)l6

4. If (X 1CY)16 = (120702)8, then X and Y are 11. An equivalent 2's complement representation of the
(a) A and 2 (b) B and 1 2's complement number 1101 is
(c) l and B (d) 2 and A (a) 110100 (b) 001101
(c) 110111 (d) 111101
5. Given (135)b + (144)b = (323)b where subscript b
denotes the base on which numbers are expressed. 12. The 2's complement representation of –17 is
What is value of b ?
(a) 101110 (b) 101111
(a) 4 (b) 5
(c) 111110 (d) 110001
(c) 6 (d) 7
6. In a digital computer, binary subtraction is
13. 11001, 1001 and 111001 correspond to the 2’s
performed
complement representation of which one of the
(a) In the same way as we perform subtraction in following sets of number?
decimal number system
(a) 25.9 and 57 respectively
(b) Using two's complement method
(b) –6, –6 and –6 respectively
(c) Using 9's complement method.
(c) –7, –7 and -7 respectively
(d) Using 10's complement
(d) –25, –9 and -57 respectively
 2

14. X = 01110 and Y = 11001 are two 5-bit binary

numbers represented in two's complement format
The sum of X and Y represented in two's
complement format using 6 bits is
(a) 100111 (b) 001000
(c) 000111 (d) 101001
 1

Branch:CSE & IT Hinglish

Digital Logic
Logic Gate DPP-01

1. The input wave form is given 4. Bulb will glow when A and B are respectively.

(a) 00 (b) 01
Draw output wave form
(c) 10 (d) 11
(a)

(b) 0 5. Find expression of F

(c) 1

(d)

2.
(a) ABC  DE (b) ABCDE
(c)  A  BC  DE (d) ABC  D  E 

6. The inverter is ________ gate

(a) AND (b) OR
(c) NOT (d) none of the above

7.
When A = 1 then the value of Y equal
(a) 0 (b) 1
(c) VCC (d) none of the above

3.

Find expression of f ?
(a) AB (b) 1
(c) A + B (d) AB

Find value of f ?
(a) 1 (b) 0
(c) A (d) A
 AB 2

8.
09.

Find output frequency, if the propagation delay of

NOT gate is 2 n sec.
Find expression of f ? (a) 125 MHz (b) 500MHz
(a) 0 (b) 1 (c) 250 MHz (d) none of the above
(c) AB (d) AB
 1

Branch :CSE & IT Hinglish

Subject : Digital Logic DPP-02

Chapter : Logic Gate

1. For a 3-input logic circuit shown below, the output Z 7. For the circuit shown in figure the Boolean expression
can be expressed as for the output Y in terms of inputs P, Q, R and S is

(a) QR (b) PQ  R

(c) QR (d) P  Q  R

2. The complete set of only those Logic Gates (b) P  Q  R  S

(a) P Q R  S
designated as Universal Gates is
(a) NOT, OR and AND Gates (c) ( P  Q)  ( R  S ) (d) ( P  Q)( R  S )
(b) XNOR, NOR and NAND Gates
(c) NOR and NAND Gates 8. A universal logic gate can implement any Boolean
(d) XOR, NOR and NAND Gates function by connecting sufficient number of them
appropriately. Three gates are shown:
3. In the logic circuit shown in the figure, Y is given by

Which one of the following statements is TRUE ?

(a) Y  ABCD (a) Gate 1 is a universal gate.
(b) Y  ( A  B)(C  D) (b) Gate 2 is a universal gate.
(c) Y  A B C  D (c) Gate 3 is a universal gate
(d) Y  AB  CD (d) None of the shown is a universal gate.

4. F = AB + CD + E will be implemented with how 9. Consider the following gate network:

many minimum number NAND gates?
(a) Three (b) Four
(c) Five (d) Six

5. The minimum number of NAND gates required to

reduce the expression ((A + B) C) D is
(a) 6 (b) 5 Which one of the following gates is redundant?
(c) 8 (d) 4 (a) Gate No. 1 (b) Gate No. 2
(c) Gate No. 3 (d) Gate No. 4
6. In a two-input NAND gate, if both inputs are shorted,
it will behave like a _______ gate. 10. The minimum of NAND gates required to implement
(a) Buffer (b) AND A + A B C is equal to
(c) NOT (d) EX-OR (a) 0 (b) 1
(c) 4 (d) 7
 1

Branch : CS & IT Hinglish

Subject : Digital Logic DPP-03

Chapter : Logic Gate

1. The initial output of the following circuit is 1. If we (a) 1 (b) 0
apply 010101 at input A (first bit is zero), then what is (c) x (d) x
the bit pattern generated at the output Y. 5. A bulb in a staircase has two switches, one switch being
at the ground floor and the other one at the first floor.
The bulb can be turned ON and also can be turned OFF
by any one of the switches irrespective of the state of
the other switch. The logic of switching of the bulb
(a) 010101 (b) 101010 resembles
(c) remains at 0 (d) remains at ‘1’ (a) an AND gate (b) an OR gate
(c) an XOR gate (c) a NAND gate
2. The Boolean expression of the output of the logic 6. In the circuit shown below, X and Y are digital inputs,
circuit shown in figure is and Z is a digital output. The equivalent circuit is

(a) Y = AB + AB + C
(b) Y = AB + AB + C
(c) Y = AB + AB + C (a) XNOR gate (b) NOR gate
(d) Y = AB + AB + C (c) NAND gate (d) XOR gate
3. A, B, C and D are input, and Y is the output bit in the 7. Which one of the following gate is also known as
XOR gate circuit of the figure below. Which of the equivalence gate?
following statements about the sum S of A, B, C, D and (a) EX-OR (b) AND
Y is correct? (c) EX-NOR (d) NOR
8. The logic function f = xy + x y is equal to
(a) EX-NOR (b) NAND
(c) EX-OR (d) NOR
9. The minimum number of 2 input NOR gates required
(a) S is always either zero or odd. to implement a 2 input XOR gate is_________
(b) S is always either zero or even. 10. The minimum number of 2 input NAND gates required
(c) S = 1 only if the sum of A, B, C and D is even. to implement a 2 input EX-NOR gates is
(d) S = 1 only if the sum of A, B, C and D is odd. (a) 4 (b) 5
4. The output Y of the logic circuit given below is (c) 3 (d) 6
 1

Branch : CS & IT Hinglish

Subject : Digital Logic
DPP-01
Chapter : Minimization
Topic : Boolean Algebra
1. Find out minimize expression for following function. 6. The logic expression
f = ABC + ABC + ABC f = X + XY
(a) AB + BC (b) AC + AB Is equivalent to
(c) BC + AB (d) AB + BC (a) X +Y (b) XY
(c) X +Y (d) X +Y
2. Find out minimize expression for following function.
f = AB + AB + A B 7. The logic expression
f = ( A + B)( A + C )
(a) A+ B (b) A+ B
Is equivalent to
(c) A+ B (d) A+ B
(a) A + BC (b) B + AC

3. Find out minimize expression for following function. (c) C + AC (d) A + BC

f = ( A + B)( A + B )( A + B)( A + B )
8. The Boolean expression
(a) 1 (b) AB
f = (1 + A)( B + AC )
(c) 0 (d) AB
is equivalent to
(a) AC + B (b) AC + B
4. Find out minimize expression for following function.
(c) A + BC (d) 1
f = ( A + B + C )( A + B + C )
(a) ( A + C)B (b) A+ B 9. Find minimization expression
(c) A BC (d) A(B + C) f = ( A + A) + ( BC + AC )( A + D)
(a) 1 (b) 0
5. The Boolean expression (c) AB + CD (d) ABC + BCD + ACD
f = ( X + Y )( X + Y ) + X Y + X
(a) Y (b) X 10. Find out minimization
f = ( A + B)( A + B + C )
(c) XY (d) X +Y
(a) B+C (b) A+ B
(c) A+ B +C (d) AB + BC + AC
 3

Hints and solutions

1. f = ABC + ABC + ABC f = ( X + Y )( X + Y ) + X + XY

= AB + ABC f = X + XY + XY + YY + X + XY
= B( A + AC ) f = X 1 + Y + Y + 1 + Y 
= B( A + C )( A + A) f =X
= AB + BC 6. f = X + XY
2. f = AB + AB + A B
f = ( X + X )( X + Y )
= AB + ( A + A) B f = X +Y
= AB + B 7. f = ( A + B)( A + C )
= ( A + B )( B + B ) f = A + AB + AC + BC
= A+ B f = A + BC
3. f = ( A + AB + AB )( A + AB + A B ) 8. f = (1 + A)( B + AC )
f =0 f = 1 ( AC + B)
4. f = ( A + B + C )( A + B + C ) f = AC + B
f = ( A + AB + AC )( AB + B + BC )( AC + BC + 0) 9. f = ( A + A) + ( BC + AC )( A + D)
f = ( A)( B)( AC + BC ) f = 1 + ( BC + AC)( A + D)
f = ABC + ABC f =1

f = ABC 10. f = ( A + B)( A + B + C )

f = A + AB + AB + B + AC + BC
5. Let f = ( X + Y )( X + Y ) + ( X Y ) + X
f = A+ B
f = ( X + Y )( X + Y ) + X Y  X
f = ( X + Y )( X + Y ) + ( X + Y ) X

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 1

Branch:CS & IT Hinglish

Subject : Digital Logic
Minimization
DPP-02
K-Map Basic
1. For the given Boolean function f (A, B, C) = 5. The simplified SOP form of the k-map is

m ( 0,1,5,6)
Simplified output will be
(a) AB + BC + ABC
(b) AB + BC + ABC
(c) AB + BC + ABC
(d) AB + BC + ABC
(a) xz +wxy (b) x
2. For the given Boolean function f(A, B, C) = (c) wx+wx (d) x z

m (1,3,6,7) + d (0,2) simplified output will be

(a) A + B 6. The Boolean function f (A, B, C, D) =

(b) B + C m (5,7,9,11,13,15) is independent of variables

(c) A + B (a) A (b) C
(d) AC + AB (c) B (d) B and C

3. What is the other canonical form of the given function 7. The simplified Boolean function is

f (A, B, C) = m (0,1,2,3,4,5,6,7)
(a) f ( A,B,C) = M (0,1,2,3,4,5,6,7)

(b) f (A, B, C) = M (0, 2, 4, 7)

(c) f ( A,B,C) = M (1,2,4,7)

(d) Does not exist

(a) A  B  C (b) A  B C
4. The product of all the maxterms of a givne Boolean (c) A B C (d) A BC
function is always equal to _________?
(a) 0
(b) 1
(c) 2
(d) Complement of the function
 2

8. The simplified Boolean expression f (w, x, y, z) = 10. The simplified expression of k-map is independent of

m ( 0,2,5,9,15) +d (6,7,8,10,12,13)

variables

(a) x z + w y+xz (b) x z + w y + x z

(c) x z + w y+xz (d) x z + w y + x z

9. The minimum number of NAND gate required to

simplify k-map
(a) A (b) B
(c) C (d) A, B and C

(a) 4 (b) 5
(b) 3 (d) 9
 4

Hints and Solutions

1. (b) 4. (a)

Given: f (A, B, C) = m ( 0,1,5,6) The product of all the max terms is always zero.

5. (b)
3 variable k-map
Given: k-map

The simplified output expression f (A, B, C) =

A B + BC + ABC
f ( w,x, y,z) = x
2. (c)
6. (b)
Given: f (A, B, C) = m (1,3,6,7) + d (0,2) k-map of 4-variables

3-variable k-map

( A,B,C) = A + B

3. (d) f (A, B, C, D) = BD + AD

Given: f ( A,B,C) = m ( 0,1,2,3,4,5,6,7 )  function is independent of C.

In these functions are min terms are covering.

The relation between min terms and max terms is

xj = xj

 Hence max term does not exist

 5

7. (b, d) 9. (b)

f ( A,B,C) = ABC + ABC + ABC + ABC f ( A,B,C) = AB + AB

f ( A,B,C) = A( B C) + A ( B  C) f ( A,B,C) = A B

f ( A,B,C) = A B( )
C + A ( B  C) Hence 5 NAND gate required

f ( A,B,C) = A ( B (
C) + A B  C )
10. (d)
f ( A,B,C) = A  B C or A BC

8. (a)

f(A, B, C) = 1

Hence independent of A, B and C.

f ( w,x, y,z) = x z + w y + xz

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 1

CS & IT
Subject : Digital Logic DPP - 1

Combinational Circuit
1. Let x = x1x0 and y = y1y0 be unsigned 2-bit numbers. 3. The output y of a 2-bit comparator is logic-1
The function F = 1 if x > y and F = 0 otherwise. The whenever the 2-bit A is greater than 2-bit B the
minimal sum of product expression for F, is number of combination for which the output is logic -
(a) y1y0 + x 0 y0 + x1 x 0 y1 1 is ____?
(a) 6 (b) 2
(b) x 0 y1 + y1 y0 + x1 x 0
(c) 1 (d) 7
(c) y1 x1 + y0 x1 x 0 + y1y0 x 0 Common Statement for Question 4 and 5
(d) x1 y1 + x 0 y0 y1 + x 0 x1 y0 A logic Circuit is given,

2. The two 4 - bit numbers A3 A2 A1 A0 and B3 B2 B1 B0

are applied to a comparator circuit shown below. A
pair of correct input numbers forcing the output y = 0,
will be

4. A pair of correct input number (AB) forcing the

output x = 1, will be
(a) 10 (b) 01
(c) 11 (d) 00

(a) 1100, 1100 5. A pair of correct input number (AB) forcing the
output y2 = 1, will be
(b) 0111, 0111 (a) 00,11 (b) 01,10
(c) 1011, 1011 (c) 00,10 (d) 11,01
(d) 1100, 1101
 1

CS & IT Hinglish
Digital Logic DPP - 02

COMBINATIONAL CIRCUIT
1. The logic realized by the circuit shown in figure is 4. A designer has multiplexer units of size 2 × 1 and
multiplexer of size 16 × 1 is to be realized. The
number of units of 2 × 1 MUXs required, will be
(a) 30 (b) 7
(c) 15 (d) 11

5. The logic function implemented by 4 × 1 MUX, is

(a) F = A C (b) F = A  C
(c) F = B C (d) F=B C

2. The minimum number of 2-to-1 multiplexers required

to realize a 4-to-1 multiplexer is
(a) 1 (b) 2
(c) 3 (d) 4
(a) Z = xy (b) Z = x + y
3. The Boolean function f implemented in the figure (c) Z =x+ y (d) xy
using two input multiplexers is

6. The minimum number of multiplexers of size 2 × 1

required to implement a 2-input XNOR gate and 2-
input AND gate, are
(a) 1 and 1 (b) 2 and 1
(c) 2 and 2 (d) 3 and 1

(a) ABC + ABC (b) ABC + ABC

(c) ABC + ABC (d) ABC + ABC

 3

Hints and solutions

1. F = A B C + A BC + AB C + ABC 2
=1
2
F = AC ( B + B ) + AC ( B + B )
15
F = AC + AC
Total 15 2 1 MUX required to implemented 16 1
F = AC
MUX.
2.
5. z = x y x + x y y + x y x + x y0
z=x y+xyx
z=x y+xy
z = x y
6. X-NOR gate implementation

Two 2 1 MUX required to implementation X-NOR

3. E = BC + BC gate.
f = AE
f = A ( BC + BC )
f = ABC + ABC
16
4. =8
2
8
=4 One 2 1 MUX required to implementation AND
2 gate.
4
=2
2

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 1

CS & IT Batch:Hinglish
Digital Logic DPP-03

Combinational Circuits

[MCQ] [MCQ]
1. A demultiplexer of size 1 × 8 with active low outputs, 3. The figure shown below is a block diagram of ______
is programmed as shown below. The circuit has three demultiplexer?
inputs x, y, z and generates two outputs y1, y2.

+VCC

If de-multiplexer has active high output instead of Y7

active low outputs, then in order that outputs do not
change
(a) NAND gates should be replaced by NOR gates
(b) NAND gates should be replaced by OR gates
(c) NAND gates should be replaced by AND gates
(d) the inputs x, y, z should be inverted

(a) 1 to 4 (b) 1 to 8
[MCQ]
(c) 1 to 16 (d) None of the above
2. For what values of A, B, C the output (Y) will be 0

[MCQ]
4. Identify the circuit shown below?

(a) Bidirectional buffer

(a) A = 1, B = 0, C = 0
(b) De-multiplexer
(b) A = 0, B = 1, C = 1
(c) Multiplexer
(c) A = 1, B = 1, C = 0
(d) Encoder
(d) A = 1, B = 1, C = 1
 2

[NAT] [MCQ]
5. How many inputs will a decimal to BCD encoder 8. To implement a 1 : 128 De-Mux we require M number
have?__________ of 1 : 8 De-mux and N numbers of 1 : 2 De-mux.
Then which of the following is correct
[MCQ] (a) (M – N)/2 = 9 (b) M + N = M
6. Which one of the following de multiplexer requires (c) M/N = M (d) (M + N)/2=9
only five select lines?
(a) 1 × 2 de Mux [MCQ]
(b) 1 × 4 De Mux 9. Consider a circuit as shown below:
(c) 1 × 8 De Mux
(d) 1 × 32 De Mux
I=1

[NAT]
7. What is the minimum number of 1 × 4 De Mux
required to implement 1 × 210 De Mux.____________
Output y is
(a) A + B (b) A  B
(c) A ⊕ B (d) A ⊙ B

[MCQ]
10. Consider a combinational circuit as shown below.

For any sequence A, B which of the output pins

(y0 to y3) can be active
(a) y0 and y3 only
(b) y1 and y2 only
(c) y1 only
(d) all pins can be active
 1

CS & IT Batch: Hinglish

Digital Logic DPP-04

Combinational Circuit

[MCQ] [MCQ]
1. What are basic gates required to implement a full 4. A 3 line to 8 line decoder with three inputs A, B, C
adder and two outputs y1 and y2, is configured as shown
(a) 1 EX-OR gate, 1 AND gate below. The minimized expression of outputs will be
(b) 2 EX-OR gate, 1 OR gate
(c) 2 EX-OR gate, 2 AND gate, 1 OR gate
(d) 1 EX-OR gate, 2 AND gate, 2 OR gate

[NAT]

2. How many half adders are required to implement the

following expressions. (a) 𝑦1 = 𝐴𝐵̅ + 𝐴𝐵𝐶̄ ; 𝑦2 = 𝐴 ⊕ 𝐵
D = ABC + ABC, E = A  B  C (b) y1 = AB + ABC; y2 = A  B
F = AC + ABC + BC (c) y1 = AB + AC; y2 = AB + AC
(d) y1 = AB + AC; y2 = AB + BC

[MCQ]
[MCQ]
3. The following multiplexer circuit is equivalent to
5. A demultiplexer of size 1 × 8 with active low outputs,
___________.
is programmed as shown below. The circuit has three
inputs x, y, z and generates two outputs y1, y2.

(a) Implementation of sum equation of full adder

(b) Implementation of carry equation of full adder
(c) Implementation of borrow equation of full
subtractor
(d) All the above
 2

What is this circuit? [MCQ]

(a) Half subtracter (b) Full subtractor 8. Two 2 × 4 decoders one with active low outputs and
(c) Half adder (d) Full adder another with active high output are interconnected as
shown below. The output function f2(x3, x2, x1) will be
[MCQ]
6. The logic diagram of a 3 × 8 decoder with active low
outputs is shown below. What is state of outputs Q7,
….. Q0 for the set of inputs E3 = E1 = 1, E2 = 0,
A2 = A1 = 1 and A0 = 0?

(a) f2 = (x1 ⊕ x2) ⊙ x3

(b) f2 = (x1 ⊙ x2) ⊙ x3
(c) f2 = (x1 ⊕ x2) ⊕ x3
(d) f2 = (x1 ⊕ x2) ⊕ x3

[MCQ]
9. Three half adders HA1, HA2 and HA3 are inter-
(a) 1111 1111 (b) 1011 1111 coupled as shown below. The four output functions y1,
(c) 1111 0111 (d) 0000 0000 y2, y3 and y4 are expressed in terms of inputs a, b and
c. Which one of the following output expressions, is
[MCQ] correct?
7. A 3 line to 8 line decoder with active low outputs, is
used to realize Boolean function involving three
variables x, y and z(x is MSB and z is LSB) as shown
below.

The minimized Boolean function f(x, y, z) in POS

format, will be
(a) ( x + y + z )( x + y + z)( x + y + z )( x + y + z )
(a) y1 = (a ⊕ b)c
(b) ( x + y + z)( x + y + z)( x + y + z)( x + y + z )
(b) y2 = (a ⊕ b) ⊕ c
(c) (𝑥 + 𝑧)(𝑦 + 𝑧)(𝑥̄ + 𝑦̄ + 𝑧̅)
(c) y3 = ab ⊕ c
(d) ( x + z )( y + z )( x + y + z )
(d) y4 = a(b ⊕ c)
 3

[MCQ] [MCQ]
10. Determine the outputs for the circuit shown below. 11. How many half adders, will be required to add two k
bit numbers?
(a) 2k + 1 (b) 2k – 1
(c) 2k (d) 2(k + 1)

[NAT]
12. Eight 1-bit full adders are cascaded. Each 1-bit full
(a) Σ = 1, Cout = 1 adder generates carry out bit in 10 ns and sum bit in
30 ns. The number of addition performed per second,
(b) Σ = 0, Cout = 0
will be __________ × 107.
(c) Σ = 0, Cout = 1
(d) Σ = 1, Cout = 0
 1

CS & IT Batch: Hinglish

Subject : Digital Electronics DPP-05

Chapter : Combinational Circuit

[MCQ] [MCQ]
1. The circuit shown below, is a controlled half adder/ 3. What is this circuit?
half subtractor. The inputs to half adder/ half (a) Full adder (b) Full subtractor
subtractor are x and y while z is a control. The outputs (c) Magnitude comparator (d) Priority encoder
are y1 and y2.

[MCQ]
4. The output of the following circuit diagram represents

0 I0
1 I1 4 × 1
(a) Half adder for z = 0 Output
0 I2 MUX
(b) Half subtractor for z = 1
0 I3
(c) Half adder for z = 1 and half subtractor for z = 0 S1 S0

(d) Half adder regardless of whether z = 0 or z = 1 due A B

to design defect. (a) Borrow of half subtractor
Statement for question 2 & 3. (b) Carry of Half Adder
Three multiplexer of size 2 × 1, are interconnected as (c) Sum of half adder
shown below: (d) None of them

[MCQ]
5. The design of a combinational logic circuit with three
inputs x, y, z and three outputs A, B, C is attempted.
The constraint is that designer has only HA, HS, FA
and FS units only in his inventory.
When the binary input is 0, 1, 2 or 3 the binary output
is same as input and when binary input is 4, 5, 6 or 7
[MCQ] the binary output is 2 less than binary input. What
2. The function f1 and f2 are completes the design?
(a) f1 = ( x1  x 2 ) x3 and f2 = x1x 2 + x1x3 + x 2 x3 (a) One FA and one HS
(b) f1 = x1  x 2  x3 and f2 = x1x 2 + x1x3 + x 2 x3 (b) One HA and one HS
(c) f1 = ( x1  x 2  x 3 ) and f 2 = x1x 2 + x1x 3 + x 2 x 3 (c) One HA only
(d) f1 = x1 ( x 2  x 3 ) and f 2 = x1x 2 + x1x 3 + x 2 x 3 (d) One FA only
 2

[NAT] [MCQ]
6. A serial adder is operating with a clock frequency of 10. A D flip-flop is used in a 4-bit serial adder, why?
10 MHz. The time required to sum 1011011 and
(a) It is used to invert the input of the full adder
10110 is _______ (in sec)
(b) It is used to store the output of the full adder
[MCQ] (c) It is used to store the carry output of the full
7. A half subtractor (HS) and 2 × 1 MUX are inter- adder
connected as demonstrated below. What is NOT (d) It is used to store the sum output of the full adder
correct about this circuit?
Y(subtrahend)
[MCQ]
11. The circuit shown in the given figure represents a/an:
HS
X D 0 MUX
B out f Y0
(minuend) 1 S Y1
0
Y2
Din = 1 1 : 8 Y3
Z Delux Y4
(a) For Z = 0, f = 1 indicates that the minuend and Y5
the subtrahend bits are different. Y6
(b) For Z = 0, f = 0 indicates that minuend and Y7
subtrahend bits are same, that is, X = Y = 0 or S0 S 1 S2
X = Y = 1.
(c) For Z = 1, f = 1 indicates that X < Y. A B C
(d) For Z = 1, f = 0 indicates that subtrahend bit is (a) decoder (b) equality detector
definitely 0.
(c) full adder (d) full subtractor

[MCQ]
8. What does minuend and subtrahend denotes in a [MCQ]
subtractor?
(a) Their corresponding bits of input 12. Consider the following circuit diagram
(b) Its output Y 1
(c) Its input
(d) Borrow bits X 2
4-Bit D
Subtractor Bout
[MCQ] X 3
A
9. What is the expression for difference, borrow of full Y 4
subtractor circuit
(a) Diff = A  B  C, A 4-bit subtractor, four 4-bit three-state buffers (with
Borrow = AC + ( A B) C bus input and output), and one inverter is used to
(b) Diff = A  B  C, subtract two numbers (Y - X), X = 0101 and Y = 0010
( )
Borrow = AB + A  B  C If A = 0, then D and Bout are respectively
(a) 0011 and 0 (b) 1101 and 0
(c) Diff = A B C,
( )
(c) 0011 and 1 (d) 1101 and 1
Borrow = AB + A B C
(d) Diff = A B C,
Borrow = AC + ( A B) C
 1
Branch :CSE & IT Batch : Hinglish

Subject : Digital Logic DPP - 1

Chapter : Sequential Circuit

1. In an SR latch made by cross-coupling two NAND

gates, if both S and R inputs are set to 0, then it will 4. In the circuit shown below, outputs QQ = 01 , the
result in
possible values of X and Y are
(a) Q = 0, Q’ = 1
(b) Q = 1, Q’ = 0
(c) Q = 1, Q’ = 1
(d) Indeterminate states

2. In the circuit shown below, when inputs A = B = 0, the

possible logic states of C and D are

(a) X = 1, Y = 0 (b) X = 1, Y = 1
(c) X = 0, Y = 1 (d) X = 0, Y = 0

5. Latch is a device with

(a) C = 0, D = 1 or C = 1, D = 0 (a) One stable state
(b) C = 1, D = 0 (b) Two stable state
(c) C = 1, D = 1 or C = 0, D = 0 (c) Three stable state
(d) C = 0, D = 1 (c) Infinite stable states

3. The two NAND gates before the latch circuit shown

below, are used to

(a) act as buffers (b) operate the latch faster

(c) avoid racing (d) invert the latching action
 1

Branch : CS & IT Batch: Hinglish

DPP - 02
Subject : Digital Logic
Chapter: Sequential Circuit

1. Consider the following J-K flip-flop

In the above J-K flip-flop, J = Q and K = 1. Assume

that the flip-flop was initially cleared and then
clocked for 6 pulses. What is the sequence at the Q (a) S-R Flip-Flop with inputs X = R and Y = S.
output? (b) S-R Flip-Flop with inputs X = S and Y = R.
(a) 010000 (b) 011001 (c) J-K Flip-Flop with inputs X = J and Y = K.
(c) 010010 (d) 010101 (d) J-K Flip-Flop with inputs X = K and Y = J.
4. The frequency of the clock signal applied to the
2. Consider the given circuit. negative going edge triggered JK flip flop shown below
is 5 kHz. What is frequency of signal available at Q ?

In this circuit, the race around

(a) does not occur. (a) 2.5 kHz (b) 5 kHz
(b) occurs when CLK = 0. (c) 10 kHz (d) 1.25 kHz
(c) occurs when CLK = 1 and A = B = 1.
(d) occurs when CLK = 1 and A = B = 0. 5. The RS flip flop is modified so as to realize a flip flop
3. A sequential circuit using D Flip-Flop and logic gates with single input P. The characteristic equation of a
is shown in figure, where X and Y are the inputs and new flip-flop will be
Z is the output. The circuit is

(a) Q(t + 1) = P  Q

(b) Q(t + 1) = P  Q
(c) Q(t + 1) = P + Q
(d) Q(t + 1) = P
 2

(c) 0 1 0 0 1 0 (d) 0 1 0 1 0 1
6. The J-K FF shown below is initially cleared and then 7. For a J-K flip-flop, J input is tied to its own Q output
clocked for 5 pulses, the sequence at the Q output will and its K input is connected to its own Q output. If the
be flip-flop is fed with a clock of frequency 1 MHz, its Q
output frequency (in MHz) will be_________.

(a) 0 1 0 0 0 0 (b) 0 1 1 0 0 1
 1

Branch : CS & IT Batch: Hinglish

Subject : Digital Logic DPP-03

Chapter : Sequential Circuits

1. If Mod-60 counter is cascaded with Mod – 40 counter,
then it will becomes, 5. For given block, the value of f0 is _____Hz.

(a) Mod – 100 counter

(b) Mod – 2400 counter
6. Symmetric square wave of time period 100 sec can be
(c) Mod – 20 counter
obtained from square wave of time period 10 sec by
(d) Mod – 140 counter using a
2. The maximum decimal count of 7-bit asynchronous (a) divide by – 5 circuit
counter is ____.
(b) divide by – 2 circuit
3. The modulus of given block is, (c) divide by – 5 followed by a divide by 2 – circuit
(d) None of these
(a) 81 (b) 40 7. How many flip – flops are required to construct Mod–
(c) 144 (d) 162 31 counter?
(a) 4 (b) 3
4. If input frequency of clock is 10 KHz then output (c) 2 (d) 5
frequency of counter will be _____ KHz [Assume
mod of counter is 5]
 1

Branch : CS / IT Batch : Hinglish

Subject : Digital Logic DPP - 4

Chapter : Sequential Circuits

1. What is the output signal frequency of the following 4. The circuit shown consists of J-K flip-flops, each with
counter if the clock signal frequency is 16 kHz? All 'J' an active low asynchronous reset ( 𝑅̅𝑑 input ). The
and 'K' inputs are connected to 1. counter corresponding to this circuit is

(a) a modulo-5 binary up counter.

(b) a modulo-6 binary down counter.
(a) 4 kHz (b) 8 kHz
(c) a modulo-5 binary down counter.
(c) 10 kHz (d) 16 kHz
(d) a modulo-6 binary up counter.
2. The circuit is counter of mod 5. The circuit shown in figure is

(a) a MOD-2 counter

(b) a MOD-3 counter
(a) Mod-0 (b) Mod-16
(c) generate sequence 00, 10, 01, 00.....
(c) Mod-15 (d) Mod-14
(d) generate sequence 00, 10, 00, 10, 00
3. The circuit is a counter of mod