Reusable Platform Design Methodology
For SoC Integration And Verification
Kwanghyun Cho, Jaebeom Kim, Euibong Jung, Sik Kim, Zhenmin Li, Young-Rae Cho,
Byeong Min*, Kyu-Myung Choi
Design Technology Team, System LSI Division, Samsung Electronics
San #24, Nongseo-Dong, Giheung-Gu, Yongin-Si, Gyeonggi-Do, Korea
{khcho9, jay.b.kim, euibong.jung, s90.kim, zm.li, yr76.cho, *byeong.min, kmchoi}@samsung.com
Abstract— Today System-on-a-Chip (SoC) is like a black hole
which draws all the important IP/Cores in a digital system.
Current SoC design methodologies are no longer adequate to
meet the challenges of SoC design productivity, design quality
and diminishing time-to-market window. This paper describes an
innovative SoC platform integration and verification design
methodology to enhance design productivity based on IP reuse
and IP-XACT standard. Platform Integrator including RPTKit
(Reusable Platform Toolkit) is developed to improve the
efficiency and reliability in platform integration, and Platform
Verifier to improve verification setup time and work efficiency.
Several cases of SoC platform designs substantiate the validity
and capability of the Platform Integrator and Verifier, which
reduced the total SoC integration and verification time by more
than 30%.
Keywords-Platform based Design; IP Reuse; SPIRIT; IP-
XACT; RPTKit; Platform Integrator; Platform Verifier
I. INTRODUCTION
SoC platform designs nowadays are facing the two
conflicting trends regarding product development: Increasing
complexity and decreasing time-to-market window.
Verification issue induced by increasing complexity has
become another crucial problem, which directly affects the
efficiency of SoC design. Therefore, in order to design
complex multi-million gate SoCs under such rigorous
circumstances, designers are seeking a more efficient and more
reliable methodology. Several innovative technologies have
been proposed so far to solve this problem. Among these
emerging ideas, the design reuse [1] and SPIRIT [2] are the
two most promising technologies, and they are gaining more
and more attention in both academia and industry.
II. SOC PLATFORM DESIGN METHODOLOGY
A. Platform-based Design Methodology
The design complexity, together with the constantly
evolving specifications, has enforced designers to consider
intrinsically flexible implementations, which can be modified
rapidly and effectively. In addition, the industry’s thriving
inclination to choose the SoC chips that will work for several
designs makes manufacturers amortize development cost over
a large number of units. This alignment among designers and
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manufacturers has resulted in the birth of platform-based
design methodology, in which reusability and configurability
are two cornerstones.
Originally set forth by [3], the concept of platform is
actually an abstraction that covers several possible lower-level
refinements. Currently one prevalent approach is to develop a
family of similar SoC chips that differ in one or more
components but are based on the same platform prototype. A
designer can later derive an architecture of platform instance
from the platform prototype by replacing a set of components
from the platform library or by setting parameters of the
library’s reconfigurable components. Such an SoC chip family
can often be considered as a general platform, and the
derivatives can be called platform instances.
B. SoC Design Reuse Methodology
Reuse, which is essentially the use of pre-designed and pre-
verified cores, is now considered to be the foundation of SoC
design, as it is the only methodology allowing the design of
complex SoCs to meet the stringent schedule, productivity and
quality requirement. The challenge for designers nowadays is
not whether to adopt reuse methodology, but how to employ it
effectively. The details of this methodology have been
elaborated in the Reuse Methodology Manual [4].
As IP reuse methodology is becoming mature, several
commercial IP reuse tools implementing platform-based SoC
design methodology have been developed. They are aiming at
creation and integration of IPs into a knowledge-based
assembly flow. These tools provide designers with a relatively
standard environment to conduct platform-based design with IP
reuse methodology. They significantly improve the efficiency
and reliability of IP creation as well as platform integration.
However, they are apt to have low inter-operability between
the tools.
C. IP-XACT from SPIRIT Consortium
SPIRIT Consortium [2] has proposed the IP-XACT
description which is an XML-based SoC meta-data
specification as a standard to describe the components of an
SoC platform. This specification describes an IP in several
aspects: hardware model, signals, bus interfaces, memory map,
address space and model views. This standard representation
can also be used to describe a hierarchical subsystem resulting
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from an assembly of sub-components. IP-XACT components,
like normal IPs supplied by IP provider, can be assembled into
an SoC platform directly using IP-XACT compliant tools,
which greatly improves the interoperability of different
abstraction levels of an SoC platform. This method has made a
more flexible, automated and optimized platform design flow.
A number of industrial experiences of applying SPIRIT
technology have been proposed [5][6], and some researches
conducted in ESL to RTL design area [7][8].
III. REUSABLE SOC PLATFORM DESIGN METHODOLOGY
Most of the SoC platforms consist of heterogeneous
platform components like processor cores, memories, buses,
and hardware IP blocks. IP designers should consider
configurability and reusability in designing an SoC platform.
For this, we came up with standard representation methods and
its environment. IP-XACT of SPIRIT consortium offers a
standard in describing properties of an IP. Figure 1 presents
our comprehensive design flow for reusable platform design
methodology, which adopted the IP-XACT description
standard for IP reuse.
Figure 1. Reusable Platform Desigin Methodology and Flow
As shown in Figure 1, the first step of the platform design
is the architecture exploration and optimization stage which
accompanies extensive architecture analysis, which is out of
the scope of this paper. The next step is the platform
integration, in which the architecture is implemented into RTL
designs and integrated into a full-chip RTL design, an SoC
platform. In order to maximize productivity by reducing turn-
around-time (TAT), this paper presents Platform Integrator
which helps designer integrate an SoC platform easy by
automating signal connections and providing standards in
handling IP blocks. Platform Integrator is fully compliant to IP-
XACT standard maximizing reusability and compatibility with
the IPs from other vendors. Standardization and automation of
platform integration process means less design bugs or human
mistakes, and it allows reducing TAT and flexibility in the
platform design process. The next step is verification of the
SoC platform. Platform Verifier, which is the unique feature of
the proposed platform design methodology, serves automatic
set up of verification environment with the IP-XACT
information prepared in the platform integration step, and it
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helps quick start of verification activities. Following chapters
will describe our implementation of Platform Integrator and
Platform Verifier.
IV. PLATFORM INTEGRATION DESIGN METHODOLOGY
A. Configuration of IP
Reusable IP means that it can be used many times even
when the system environment requires different configuration
or different features that fit into the system. Configurability is
more important in platform design, since a platform by
definition is to be used to make many derivative designs from
it. The variety of current SoC designs would require many
slightly different versions of an IP. The proposed reusable
platform design methodology can handle configuration of RTL
designs. The IP designer can insert parameters and comment-
type pragmas in the design, which direct Platform Integrator to
generate the RTL that fits into the design requirement. The
availability of configuration of IP properties gives flexibility in
IP design and IP management.
B. IP Packaging with IP-XACT for Reuse
An ideal design reuse methodology completely separates IP
provider from SoC platform integrator. The SoC platform
integrator chooses IP components from IP library and stitches
them up to make an SoC platform. It is very important that this
integration work shouldn’t take long time to get enough
information for integration. IP packaging is the process which
prepares all the information of an IP into an IP-XACT coded
XML data as well as an RTL database.
The IP packaging process includes followings:
1) Memory map: Any IP has one or more registers as a way
of communication with others. Register information encoded
with a standard becomes the first stepping stone to design
automation. This information can be translated to make some
documents, integrity checkers, coverage monitors et al. Data
integrity with real RTL design database gives reliability and
no room for human errors.
2) Interface definition: The IP component has a large
number of ports. Many times, these are connected to other
components in groups with bundled signals, where the role of
every signal is predefined like an AXI bus, as an example.
Other private signals can be grouped each other to improve
work efficiency in SoC integration. An interface definition of
a component represents identifying signal groups to get logical
ports and giving them proper names. It is important to have
naming convention rules in defining interfaces.
3) Interface mapping: After the interface is defined, every
interface signals are identified according to the interface
definitions and mapping information is provided. IP packaging
process includes mapping the definitions to real design
database, and platform integration provides the connection
mechanism for the interfaces. The interface mapping process
serves certain level of integrity checking.
4) IP Packaging: IP packaging can include many other
design properties pertaining to the IP, such as information for
2008 International SoC Design Conference
synthesis like constraints, or attributes of verification. These
different kinds of information are packaged to be an XML
with IP-XACT standard.

The IP packaging gives efficiency in SoC platform

integration process and flexibility in IP sharing which forms an
emerging market.

C. Platform Integration with Packaged IPs

An SoC platform contains a lot of IPs and integrating the
IPs to form a top-level RTL design incurs tremendous signal
connections, which is time consuming work and vulnerable to
human errors. The integration work gets the worst case when
the design changes happen frequently. Automation of this
hassling work is inevitable for the SoC platform integration.
Figure 2. Specification description with spread-sheet style
The proposed platform design methodology defined types
of interface connections and presents an effective way to repackage an IP or re-assemble an entire system after
mapping the definitions into physical ports. The signal modifying the platform reuse specification by simply launching
interface connections include three different types of bus the specification translator, RPTKit (Reusable Platform
interface: (1) Standard bus interface, which uses standard Toolkit) and underlying tools. Moreover, design reuse
communication protocols like AMBA bus and OCP interface. specification can be easily used to generate detailed document
(2) Custom bus interface, which represents customizable for the SoC platform design. From IP packaging to subsystem
communication protocols like DMA interface and memory assembling, the effort spent on documentation can be
interface. (3) Dedicated bus interface, which represents significantly saved.
remaining signals that are regarded as another type of bus
which includes many other side signals interfacing different IPs
directly. All the interface signals in the top-level design belong V. PLATFORM VERIFICATION DESIGN METHODOLOGY
to its proper type of bus as defined in the above. Platform One of the major benefits that we can get from IP-XACT-
integration process has similar work flow as defined in IP based design methodology is verification automation. Platform
packaging process, which includes interface definition and Verifier generates testbenches for the verification of various
mapping. Top level interface connections are to be defined as aspects of SoC design using the information in IP-XACT XML
different type of bus interfaces and the bus interface definitions which is available from the result of the platform integration.
are mapped to physical ports of each IPs and bus units. The
As the number of IPs integrated in an SoC increases, the
interface signal connections can handle hierarchical
SoC bus fabric becomes more and more complex and it’s not
connections.
easy to verify the bus fabric as a whole. Platform Verifier can
Base address of each register group is added to the memory generate testbench for bus fabric verification. As the bus fabric
map information of the platform design. Several sanity check of an SoC is typically not designed as a separate module,
mechanisms are included in this stage: duplication of register Platform Verifier replaces all the IP instances connected to the
addresses, integrity of interface signals, and electrical rule bus fabric, with empty modules having nothing but I/O ports.
checks. These are static checks done before physical Bus functional models are attached to every masters and slave
interconnections. ports of those replaced IPs. Currently AMBA interface is
supported by Platform Verifier and Cadence’s AHB/AXI eVC
D. Flow Automation for IP Packaging & System Integration and proprietary APB eVC are used as verification IPs. Using
this testbench, all the master and slave connections through the
Specification-based design methodology has been put
bus fabric can be easily verified. Each master generates random
forward for years and gained pervasive attention. However, the
transactions for slave access and the result can be easily
importance of specification-based design reuse methodology
analyzed using the coverage information which also provided
has never been emphasized before. In practice, the
by Platform Verifier.
specification for design reuse is very crucial to SoC platform
design.
Design reuse specifications include many different aspects
of design reusability and configurability, such as memory map,
interface definition, interface mapping, dedicated signal
connection and design constraints. These specifications are
given to a spreadsheet style input templates as shown in the
Figure 2. These specifications can be employed directly to
generate packaging or assembling script so as to be used by
underlying IP reuse tools. It also plays an important role in
platform debugging and re-assembling. Designer is able to
Figure 3. Testbench for register access test

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 Register access test is one of the primitive tests to check if
an IP is integrated in the SoC chip correctly. Even though it is
not a difficult job, it is tedious and cumbersome to write tests
for all registers in an SoC. If we use the register information
included in IP-XACT XML, this test can be done
automatically. Platform Verifier generates testbench and test
sequences for this test. Automatic self checking facility is also
included in the generated testbench and thus it is possible to do
register reset value test by just reading each registers after
reset. As shown in the Figure 3 function coverage for register
access is also provided for easy analysis of simulation result.
The testbench generated by Platform Verifier is written in
Specman e-language and using the methodology called
sec_sVM, which has been developed in Samsung based on the
eRMTM from Cadence. Thus the generated testbench can be
easily extended or modified according to engineer’s need by
integrating with the existing verification components and
testbenches. The application results showed in the following
chapter shows that Platform Verifier is effective in saving
verification time.
VI. CASE STUDY: APPLICATIONS TO SOC PLATFORMS
We have applied the reusable platform design methodology
and flow in designing several SoC platforms. These platforms
applied are mobile, multimedia, and ASIC SoC designs and are
comprised of high end processors core, multiple on-chip-buses
based on AMBA (AXI, AHB, APB) technology, several
dedicated functional blocks, and peripheral IPs. These
platforms have almost hundred IPs and have over thousands of
interconnections. Table I shows the portion of interface signals,
which consists standard interfaces, custom interfaces, and
dedicated interfaces within the platforms which are applied.
TABLE I. THE ANALYSIS OF COMPLEXITY OF INTERFACES
Standard Custom Dedicated
Applications
Interface Interface Interface
Media SoC 19% 78% 3%
Mobile SoC 57% 39% 4%
ASIC SoC 49% 8% 43%
A connection between bus and IP is the standard interface,
which has predefined signal configuration. It is relatively easy
to connect them due to its regularity. However, other types of
connection like custom bus and many dedicated connection
signals have been relied on designers’ elaboration. The Figure
4 shows that Platform Integrator could save the interface
connections up to 74%. Some results of platform integration
flow and tools adoption, finally, showed the 30% reduction of
integration time. We have also generated the platform
verification environment automatically using Platform Verifier
with IP-XACT files generated by Platform Integrator. Platform
Verifier reduced verification time for the bus fabric of the
platform. In case of one application, it showed reduction of
verification time more than 70% compared to conventional
testbench writing methodology.
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Figure 4. Interconnect automation based on bus interface
VII. SUMMARY
This paper introduces a novel platform based SoC design
flow and methodology for SoC platform integration and
verification, as well as an innovative platform design reuse
methodology. It has been shown that the features implemented
in Platform Integrator and Verifier fully exploit the IP reuse
with SPIRIT technology. Especially, design flow automation
for IP packaging and platform integration using RPTKit is
proven to be beneficial for the efficiency and reliability in the
design of SoC platforms. Effective management of
heterogeneous SoC platform components enables completely
flexible platform integration. Once the platform integration has
been done based on the IP-XACT information of the integrated
platform, Platform Verifier successfully generated verification
environment for buses fabric and top-level testbench. Several
application experiences demonstrate validity and capability of
this platform design methodology. Application results show
that the reusable platform design methodology has reduced
platform design time 30% in mother version and more than
50% in derivative platforms compared with traditional
methodology.
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[3] A.S.Vincentelli and Grant Martin, “Platform-Based Design and
Software Design Methodology for Embedded Systems”, Design & Test
of Computer, IEEE, Vol 18, Issue 6, pp. 23-33, Nov.-Dec., 2000.
[4] Michael Keating and Pierre Bricaud, “Reuse Methodology Manual for
System-on-a-Chip Designs”, Third Edition, Kluwer Academic
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[5] Christopher K. Lennard, “Industrially Proving the SPIRIT Consortium
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2008 International SoC Design Conference