VLSI Programs

EC8661 VLSI DESIGN LABORATORY
EXP NO: DESIGN OF COMBINATIONAL CIRCUIT

DATE:
AIM:
To design implement the combinational circuit using Verilog HDL
APPARATUS REQUIRED:
1) PC
2) Xilinx ISE Design Suite 13.1
PROCEDURE:
1) Open Xilinx ISE Design Suite 13.1
2) Click on File🡪New Project for opening an project file
3) Enter the Project Name🡪Click Next
4) Enter the device details as Spartan3, speed as -4 and device as XC3S50
5) Click on New Source tab🡪 Verilog Module to Enter the name of the Project and click
Next\
6) Define the input and output port for the module being designed and type the program
code
7) Check Syntax and if successful click on Synthesize XST
8) RTL Schematic and Technological Schematic can be obtained by selecting the
Implementation tab
9) Repeat the same procedure for creating New Source🡪 Verilog Text Fixture
10) The output graph can be obtained by simulation of the Verilog Text Fixture
PROGRAMS:
1)FULL ADDER:
DATA FLOW MODEL:

module fulladdr(
input a,
input b,
input c,
output sum,
output carry
);
wire x,y,z;
assign x=a^b;
assign y=a&b;
assign sum=x^c;
assign z=x&c;
assign carry=z|y;
endmodule
VEL TECH HIGH TECH 1 DEPARTMENT OF ECE

STRUCTURAL MODEL:
module fulladdr(
input a,
input b,
input c,
output sum,
output carry
);
wire x,y,z;
xor(x,a,b);
and(y,a,b);
xor(sum,x,c);
and(z,x,c);
or(carry,z,y);
endmodule
TEST BENCH FOR FULL ADDER:

module fulladder;
// Inputs
reg a;
reg b;
reg c;
// Outputs
wire sum;
wire carry;
// Instantiate the Unit Under Test (UUT)
fulladdr uut (
.a(a),
.b(b),
.c(c),
.sum(sum),
.carry(carry)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
c = 0;
// Wait 100 ns for global reset to finish
#100;a=3'b0;b=3'b0;c=3'b0;
#100;a=3'b0;b=3'b0;c=3'b1;
#100;a=3'b0;b=3'b1;c=3'b0;
#100;a=3'b0;b=3'b1;c=3'b1;
#100;a=3'b1;b=3'b0;c=3'b0;
#100;a=3'b1;b=3'b0;c=3'b1;
#100;a=3'b1;b=3'b1;c=3'b0;

#100;a=3'b1;b=3'b1;c=3'b1;
// Add stimulus here
end
endmodule
SYNTHESIZE REPORT:
Synthesis report
Release 13.1 - xst O.40d (nt)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs

Total CPU time to Xst completion: 0.09 secs
--> Parameter xsthdpdir set to xst

--> Reading design: fulladdrfpga.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=====================================================================
====
* Synthesis Options Summary *
=====================================================================
====
---- Source Parameters

Input File Name : "fulladdrfpga.prj"

Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters

Output File Name : "fulladdrfpga"
Output Format : NGC
Target Device : xc3s400-4-pq208
---- Source Options

Top Module Name : fulladdrfpga
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : Yes
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : Yes
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : Auto
Automatic Register Balancing : No
---- Target Options

Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 8
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options

Optimization Goal : Speed

Optimization Effort :1
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator :/
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=====================================================================
====
=====================================================================
====
* HDL Compilation *
=====================================================================
====
Compiling verilog file "fulladdrfpga.v" in library work
Module <fulladdrfpga> compiled
No errors in compilation
Analysis of file <"fulladdrfpga.prj"> succeeded.
=====================================================================
====
* Design Hierarchy Analysis *
=====================================================================
====
Analyzing hierarchy for module <fulladdrfpga> in library <work>.
=====================================================================
====
* HDL Analysis *
=====================================================================
====
Analyzing top module <fulladdrfpga>.

Module <fulladdrfpga> is correct for synthesis.
=====================================================================
====
* HDL Synthesis *
=====================================================================
====
Performing bidirectional port resolution...
Synthesizing Unit <fulladdrfpga>.

Related source file is "fulladdrfpga.v".
Found 1-bit xor2 for signal <sum>.
Found 1-bit xor2 for signal <x>.
Unit <fulladdrfpga> synthesized.
=====================================================================
====
HDL Synthesis Report
Macro Statistics
# Xors :2
1-bit xor2 :2
=====================================================================
====
=====================================================================
====
* Advanced HDL Synthesis *
=====================================================================
====
=====================================================================
====
Advanced HDL Synthesis Report
Macro Statistics
# Xors :2
1-bit xor2 :2
=====================================================================
====

=====================================================================
====
* Low Level Synthesis *
=====================================================================
====
Optimizing unit <fulladdrfpga> ...
Mapping all equations...

Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block fulladdrfpga, actual ratio is 0.
Final Macro Processing ...
=====================================================================
====
Final Register Report
Found no macro
=====================================================================
====
=====================================================================
====
* Partition Report *
=====================================================================
====
Partition Implementation Status

-------------------------------
No Partitions were found in this design.
-------------------------------
=====================================================================
====
* Final Report *
=====================================================================
====
Final Results
RTL Top Level Output File Name : fulladdrfpga.ngr
Top Level Output File Name : fulladdrfpga
Output Format : NGC

Keep Hierarchy : No
Design Statistics
# IOs :5
Cell Usage :
# BELS :2
# LUT3 :2
# IO Buffers :5
# IBUF :3
# OBUF :2
=====================================================================
====
Device utilization summary:

---------------------------
Selected Device : 3s400pq208-4
Number of Slices: 1 out of 3584 0%

Number of 4 input LUTs: 2 out of 7168 0%
Number of IOs: 5
Number of bonded IOBs: 5 out of 141 3%
---------------------------
Partition Resource Summary:
---------------------------
---------------------------
=====================================================================
====
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:

----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -4
Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 9.033ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)

BLOCK DIAGRAM:
RTL SCHEMATIC:

TECHNOLOGY SCHEMATIC:
OUTPUT:

2)HALF ADDER:
STRUCTURAL MODEL:
module halfadder(
input a,
input b,
output sum,
output carry
);
xor r1(sum,a,b);
and p1(carry,a,b);
endmodule
TEST BENCH FOR HALF ADDER:

module halfadder2;
// Inputs
reg a;
reg b;
// Outputs
wire sum;
wire carry;
halfadder uut (
.a(a),
.b(b),
.sum(sum),
.carry(carry)
);
initial begin
a = 0;
b = 0;
#100;a=2'b0;b=2'b0;
#100;a=2'b0;b=2'b1;
#100;a=2'b1;b=2'b0;
#100;a=2'b1;b=2'b1;
end
endmodule

BLOCK DIAGRAM:
RTL SCHEMATIC:

TECHNOLOGICAL SCHEMATIC:
OUTPUT:

3) FULL SUBTRACTOR:
STRUCTURAL MODEL:
module fullsubtr(
input a,
input b,
input c,
output diff,
output borrow
);
wire x,y,z,l,m;
xor r1(x,a,b);
xor r2(diff,x,c);
not n1(l,a);
not n2(m,x);
and p1(y,l,b);
and p2(z,m,c);
or s1(borrow,z,y);
endmodule
TEST BENCH FOR FULL SUBTRACTOR:

module fullsubtest;
// Inputs
reg a;
reg b;
reg c;
// Outputs
wire diff;
wire borrow;
fullsubtr uut (
.a(a),
.b(b),
.c(c),
.diff(diff),
.borrow(borrow)
);
initial begin
a = 0;
b = 0;
c = 0;
#100;a=3'b0;b=3'b0;c=3'b0;

#100;a=3'b0;b=3'b0;c=3'b1;
#100;a=3'b0;b=3'b1;c=3'b0;
#100;a=3'b0;b=3'b1;c=3'b1;
#100;a=3'b1;b=3'b0;c=3'b0;
#100;a=3'b1;b=3'b0;c=3'b1;
#100;a=3'b1;b=3'b1;c=3'b0;
#100;a=3'b1;b=3'b1;c=3'b1;
end
endmodule
BLOCK DIAGRAM:
RTL SCHEMATIC:

OUTPUT:


4)HALF SUBTRACTOR:
DATAFLOW MODEL:
module halfsubtr(
input a,
input b,
output diff,
output borrow
);
assign diff=a^b;
assign l=~a;
assign borrow=l&b;
endmodule
TEST BENCH FOR HALF SUBTRACTOR:

module halfsubtest;
// Inputs
reg a;
reg b;
// Outputs
wire diff;
wire borrow;
halfsubtr uut (
.a(a),
.b(b),
.diff(diff),
.borrow(borrow)
);
initial begin
a = 0;
b = 0;
#100;a=2'b0;b=2'b0;
#100;a=2'b0;b=2'b1;
#100;a=2'b1;b=2'b0;
#100;a=2'b1;b=2'b1;
end
endmodule

BLOCK DIAGRAM:
RTL SCHEMATIC:

OUTPUT:

5) 8X3 ENCODER:
STRUCTURAL MODEL:
module encod(
input [0:7] E,
output X,
output Y,
output Z
);
assign X=E[0]+E[4]+E[5]+E[6]+E[7];
assign Y=E[2]+E[3]+E[6]+E[7];
assign Z=E[1]+E[3]+E[5]+E[7];
endmodule
TEST BENCH FOR ENCODER:

module encodte;
// Inputs
reg [0:7] E;
// Outputs
wire X;
wire Y;
wire Z;
encod uut (
.E(E),
.X(X),
.Y(Y),
.Z(Z)
);
initial begin
E = 0;
#100;E[0]=8'b1;E[1]=8'b0;E[2]=8'b0;E[3]=8'b0;E[4]=8'b0;E[5]=8'b0;E[6]=8'b0;E[7]=8'b0;
end
endmodule

BLOCK DIAGRAM:
RTL SCHEMATIC:


OUTPUT:

6) 3X8 DECODER:
module decode3_8(
input [0:2]x,
output [0:7]d
);
wire [0:2]a;
assign a[0]=~x[0];
assign a[1]=~x[1];
assign a[2]=~x[2];
assign d[0]=a[0]&a[1]&a[2];
assign d[1]=a[0]&a[1]&x[2];
assign d[2]=a[0]&x[1]&a[2];
assign d[3]=a[0]&x[1]&x[2];
assign d[4]=x[0]&a[1]&a[2];
assign d[5]=x[0]&a[1]&x[2];
assign d[6]=x[0]&x[1]&a[2];
assign d[7]=x[0]&x[1]&x[2];
endmodule
TEST BENCH FOR DECODER:
module decode3_8test;
// Inputs
reg [0:2] x;
// Outputs
wire [0:7] d;

decode3_8 uut (
.x(x),
.d(d)
);
initial begin
x = 0;
#100x[0]=1'b0;x[1]=1'b0;x[2]=1'b0;
#100x[0]=1'b0;x[1]=1'b0;x[2]=1'b1;
#100x[0]=1'b0;x[1]=1'b1;x[2]=1'b0;
#100x[0]=1'b0;x[1]=1'b1;x[2]=1'b1;
#100x[0]=1'b1;x[1]=1'b0;x[2]=1'b0;
#100x[0]=1'b1;x[1]=1'b0;x[2]=1'b1;
#100x[0]=1'b1;x[1]=1'b1;x[2]=1'b0;
#100x[0]=1'b1;x[1]=1'b1;x[2]=1'b1;

end
endmodule
SYNTHESIS REPORT:



--> Reading design: decode3_8.prj
TABLE OF CONTENTS
2) HDL Compilation
4) HDL Analysis
5) HDL Synthesis
8) Partition Report
9) Final Report
9.3) TIMING REPORT
=====================================================================
====
=====================================================================
====
Input File Name : "decode3_8.prj"

Output File Name : "decode3_8"
Output Format : NGC

Target Device : xc3s250e-4-pq208
---- Source Options

Top Module Name : decode3_8
FSM Style : LUT
RAM Style : Auto
Mux Style : Auto
ROM Style : Auto
---- Target Options

Slice Packing : YES

Keep Hierarchy : No
RTL Output : Yes
Read Cores : YES


Bus Delimiter : <>
Verilog 2001 : YES
=====================================================================
====
=====================================================================
====
* HDL Compilation *
=====================================================================
====
Compiling verilog file "decode3_8.v" in library work
Module <decode3_8> compiled
Analysis of file <"decode3_8.prj"> succeeded.
=====================================================================
====
=====================================================================
====
Analyzing hierarchy for module <decode3_8> in library <work>.
=====================================================================
====
* HDL Analysis *
=====================================================================
====
Analyzing top module <decode3_8>.
Module <decode3_8> is correct for synthesis.
=====================================================================
====
* HDL Synthesis *
=====================================================================
====
Synthesizing Unit <decode3_8>.

Related source file is "decode3_8.v".

Unit <decode3_8> synthesized.
=====================================================================
====
Found no macro
=====================================================================
====
=====================================================================
====
=====================================================================
====
=====================================================================
====
Found no macro
=====================================================================
====
=====================================================================
====
=====================================================================
====
Optimizing unit <decode3_8> ...

Found area constraint ratio of 100 (+ 5) on block decode3_8, actual ratio is 0.

=====================================================================
====
Found no macro
=====================================================================
====
=====================================================================
====

=====================================================================
====

-------------------------------

-------------------------------
=====================================================================
====
* Final Report *
=====================================================================
====
Final Results
RTL Top Level Output File Name : decode3_8.ngr
Top Level Output File Name : decode3_8
Output Format : NGC
Keep Hierarchy : No
Design Statistics
# IOs : 11
Cell Usage :
# BELS :8
# LUT3 :8
# IO Buffers : 11
# IBUF :3
# OBUF :8
=====================================================================
====

---------------------------
Selected Device : 3s250epq208-4

Number of IOs: 11
---------------------------
---------------------------

=====================================================================
====
TIMING REPORT

Clock Information:
------------------
----------------------------------------
Timing Summary:
---------------
Speed Grade: -4

Timing Detail:
--------------
=====================================================================
====
Timing constraint: Default path analysis
Total number of paths / destination ports: 24 / 8
-------------------------------------------------------------------------
Delay: 6.546ns (Levels of Logic = 3)
Source: x<0> (PAD)
Destination: d<0> (PAD)
Data Path: x<0> to d<0>

Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 8 1.218 0.932 x_0_IBUF (x_0_IBUF)
LUT3:I0->O 1 0.704 0.420 d_3_and00001 (d_3_OBUF)
OBUF:I->O 3.272 d_3_OBUF (d<3>)
----------------------------------------
Total 6.546ns (5.194ns logic, 1.352ns route)

(79.3% logic, 20.7% route)

=====================================================================
====

-->
Total memory usage is 132160 kilobytes
Number of errors : 0 ( 0 filtered)

Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

BLOCK DIAGRAM:
RTL SCHEMATIC:

OUTPUT:

MULTIPLEXER:
PROGRAM FOR MULTIPLEXER:

module MUX8_1(
input x,
input y,
input z,
output out
);
wire [0:2]a;
wire [0:7]b;
wire [0:5]c;
not n1(a[0],x);
not n2(a[1],y);
not n3(a[2],z);
and a1(b[0],a[0],a[1],a[2]);
and a2(b[1],b[0],a[1],z);
and a3(b[2],b[0],y,a[2]);
and a4(b[3],a[0],y,z);
and a5(b[4],x,a[1],a[2]);
and a6(b[5],x,b[1],z);
and a7(b[6],x,y,a[2]);
and a8(b[7],x,y,z);
or o1(c[0],b[0],b[1]);
or o2(c[1],b[2],b[3]);
or o3(c[2],b[4],b[5]);
or o4(c[3],b[6],b[7]);
or o5(c[4],c[0],c[1]);
or o6(c[5],c[2],c[3]);
or o7(out,c[4],c[5]);
endmodule
TEST BENCH FOR MULTIPLEXER:

module mux8_1test;
// Inputs
reg x;
reg y;
reg z;
// Outputs
wire out;
MUX8_1 uut (
.x(x),
.y(y),
.z(z),
.out(out)

);
initial begin
x = 0;
y = 0;
z = 0;
#100 x=1'b0;y=1'b0;z=1'b0;
#100 x=1'b0;y=1'b0;z=1'b1;
#100 x=1'b0;y=1'b1;z=1'b0;
#100 x=1'b0;y=1'b1;z=1'b1;
#100 x=1'b1;y=1'b0;z=1'b0;
#100 x=1'b1;y=1'b0;z=1'b1;
#100 x=1'b1;y=1'b1;z=1'b0;
#100 x=1'b1;y=1'b1;z=1'b1;
end
endmodule

BLOCK DIAGRAM:
RTL SCHEMATIC:


OUTPUT:

DEMULTIPLEXER:
PROGRAM FOR DEMULTIPLEXER:

module demux1_8(
input [0:2]s,
output [0:7]o
);
wire [0:2]a;
not n1(a[0],s[2]);
not n2(a[1],s[1]);
not n3(a[2],s[0]);
and a1(o[0],a[0],a[1],a[2]);
and a2(o[1],a[0],a[1],s[0]);
and a3(o[2],a[0],s[1],a[2]);
and a4(o[3],a[0],s[1],s[0]);
and a5(o[4],s[2],a[1],a[2]);
and a6(o[5],s[2],a[1],s[0]);
and a7(o[6],s[2],s[1],a[2]);
and a8(o[7],s[2],s[1],s[0]);
endmodule
TEST BENCH:
module demux1_8test;
// Inputs
reg [0:2] s;
// Outputs
wire [0:7] o;
demux1_8 uut (
.s(s),
.o(o)
);
initial begin
s = 0;
#100 s[2]=1'b0;s[1]=1'b0;s[0]=1'b0;
#100 s[2]=1'b0;s[1]=1'b0;s[0]=1'b1;
#100 s[2]=1'b0;s[1]=1'b1;s[0]=1'b0;
#100 s[2]=1'b0;s[1]=1'b1;s[0]=1'b1;
#100 s[2]=1'b1;s[1]=1'b0;s[0]=1'b0;
#100 s[2]=1'b1;s[1]=1'b0;s[0]=1'b1;
#100 s[2]=1'b1;s[1]=1'b1;s[0]=1'b0;
#100 s[2]=1'b1;s[1]=1'b1;s[0]=1'b1;
end
endmodule

SYNTHESIZE REPORT:



--> Reading design: demux1_8.prj
TABLE OF CONTENTS
2) HDL Compilation
4) HDL Analysis
5) HDL Synthesis
8) Partition Report
9) Final Report
9.3) TIMING REPORT
=====================================================================
====
=====================================================================
====
Input File Name : "demux1_8.prj"

Output File Name : "demux1_8"
Output Format : NGC
Target Device : xc3s250e-4-pq208
---- Source Options

Top Module Name : demux1_8

FSM Style : LUT
RAM Style : Auto
Mux Style : Auto
ROM Style : Auto
---- Target Options

Slice Packing : YES

Keep Hierarchy : No
RTL Output : Yes
Read Cores : YES
Bus Delimiter : <>


Verilog 2001 : YES
=====================================================================
====
=====================================================================
====
* HDL Compilation *
=====================================================================
====
Compiling verilog file "demux1_8.v" in library work
Module <demux1_8> compiled
Analysis of file <"demux1_8.prj"> succeeded.
=====================================================================
====
=====================================================================
====
Analyzing hierarchy for module <demux1_8> in library <work>.
=====================================================================
====
* HDL Analysis *
=====================================================================
====
Analyzing top module <demux1_8>.
Module <demux1_8> is correct for synthesis.
=====================================================================
====
* HDL Synthesis *
=====================================================================
====
Synthesizing Unit <demux1_8>.

Related source file is "demux1_8.v".

Unit <demux1_8> synthesized.
=====================================================================
====
Found no macro
=====================================================================
====
=====================================================================
====
=====================================================================
====
=====================================================================
====
Found no macro
=====================================================================
====
=====================================================================
====
=====================================================================
====
Optimizing unit <demux1_8> ...

Found area constraint ratio of 100 (+ 5) on block demux1_8, actual ratio is 0.
=====================================================================
====
Found no macro

=====================================================================
====
=====================================================================
====
=====================================================================
====

-------------------------------
-------------------------------
=====================================================================
====
* Final Report *
=====================================================================
====
Final Results
RTL Top Level Output File Name : demux1_8.ngr
Top Level Output File Name : demux1_8
Output Format : NGC
Keep Hierarchy : No
Design Statistics
# IOs : 11
Cell Usage :
# BELS :8
# LUT3 :8
# IO Buffers : 11
# IBUF :3
# OBUF :8
=====================================================================
====

---------------------------
Selected Device : 3s250epq208-4


Number of IOs: 11
---------------------------
---------------------------
---------------------------
=====================================================================
====
TIMING REPORT

Clock Information:
------------------

----------------------------------------
Timing Summary:
---------------
Speed Grade: -4

Timing Detail:
--------------
=====================================================================
====

-------------------------------------------------------------------------
Source: s<2> (PAD)
Destination: o<0> (PAD)
Data Path: s<2> to o<0>

Gate Net
---------------------------------------- ------------
IBUF:I->O 8 1.218 0.932 s_2_IBUF (s_2_IBUF)
LUT3:I0->O 1 0.704 0.420 o_3_and00001 (o_3_OBUF)
OBUF:I->O 3.272 o_3_OBUF (o<3>)
----------------------------------------
(79.3% logic, 20.7% route)
=====================================================================
====

-->


BLOCK DIAGRAM:
RTL SCHEMATIC:

OUTPUT:

MULTIPLIER:
module multplr(
input [0:1] A,
input [0:1] B,
output [0:3] C
);
wire[0:3]D;
and a1(C[0],A[0],B[0]);
and a2(D[0],A[0],B[1]);
and a3(D[1],A[1],B[0]);
and a4(D[2],A[1],B[1]);
halfaddr ha1(C[1],D[3],D[0],D[1]);
halfaddr ha2(C[2],C[3],D[3],D[2]);
endmodule
module halfaddr(
input a,
input b,
output c,
output d
);
xor r1(c,a,b);
and p1(d,a,b);
endmodule
TEST BENCH FOR MULTIPLIER:

module multitest;
// Inputs
reg [0:1] A;
reg [0:1] B;
// Outputs
wire [0:3] C;
multplr uut (
.A(A),
.B(B),
.C(C)
);
initial begin
A = 0;
B = 0;
#100;A[0]=0;A[1]=0;B[0]=0;B[1]=0;
#100;A[0]=1;A[1]=1;B[0]=1;B[1]=1;
end
endmodule

BLOCK DIAGRAM:
RTL SCHEMATIC:

OUTPUT:

8-BIT ADDITION:
module adder(a, b, c, sum, carry);
input [7:0] a;
input [7:0] b;
input c;
output sum;
output carry;
wire [8:0]tmp;
assign sum=[7:0]tmp;
assign sum=a+b+c;
assign carry=[8]tmp;
endmodule
test bench:
module ADDTEST_v;
// Inputs
reg [7:0] a;
reg [7:0] b;
reg c;
// Outputs
wire sum;

wire carry;
adder uut (
.a(a),
.b(b),
.c(c),
.sum(sum),
.carry(carry)
);
initial begin
a = 0;
b = 0;
c = 0;
#100 a=8'b11110000;b=8'b11110000;c=0;
end
endmodule

SIMULATION:

RESULT:
Thus the sequential circuits are designed and implemented using Verilog HDL by Xilinx and the
output is obtained

EXP NO: DESIGN OF SEQUENTIAL CIRCUIT

DATE:
AIM:
To design and implement the sequential circuit using Verilog HDL
APPARATUS REQUIRED:
1) PC
PROCEDURE:
Next\
code
7) Check Syntax and if successful click on Synthesize XST
8) RTL Schematic and Technological Schematic can be obtained by selecting the
Implementation tab
9) Repeat the same procedure for creating New Source🡪 Verilog Text Fixture
10) The output graph can be obtained by simulation of the Verilog Text Fixture
PROGRAMS:
D LATCH:
module delaylatch(
input d,
input clk,
output q,
output qbar
);
wire b,c,a;
not(a,d);
nand(b,d,clk);
nand(c,a,clk);
nand(q,b,qbar);
nand(qbar,c,q);
endmodule
TEST BENCH FOR D LATCH:

module delaylatchtest;
// Inputs
reg d;

reg clk;
// Outputs
wire q;
wire qbar;
delaylatch uut (
.d(d),
.clk(clk),
.q(q),
.qbar(qbar)
);
initial
clk=0;
always
#5 clk=~clk;
initial begin
d = 0;
//clk = 0;
#100 d=1;
#100 d=0;
#100 d=1;
end
endmodule
SYNTHESIS REPORT:


--> Reading design: delaylatch.prj
TABLE OF CONTENTS

2) HDL Compilation
4) HDL Analysis
5) HDL Synthesis
8) Partition Report
9) Final Report
9.3) TIMING REPORT
=====================================================================
====
=====================================================================
====
Input File Name : "delaylatch.prj"

Output File Name : "delaylatch"
Output Format : NGC
---- Source Options

Top Module Name : delaylatch
FSM Style : LUT
RAM Style : Auto
Mux Style : Auto
ROM Style : Auto


---- Target Options

Slice Packing : YES

Keep Hierarchy : No
RTL Output : Yes
Read Cores : YES
Bus Delimiter : <>
Verilog 2001 : YES
=====================================================================
====
=====================================================================
====
* HDL Compilation *

=====================================================================
====
Compiling verilog file "delaylatch.v" in library work
Module <delaylatch> compiled
Analysis of file <"delaylatch.prj"> succeeded.
=====================================================================
====
=====================================================================
====
Analyzing hierarchy for module <delaylatch> in library <work>.
=====================================================================
====
* HDL Analysis *
=====================================================================
====
Analyzing top module <delaylatch>.
Module <delaylatch> is correct for synthesis.
=====================================================================
====
* HDL Synthesis *
=====================================================================
====
Synthesizing Unit <delaylatch>.

Related source file is "delaylatch.v".
Unit <delaylatch> synthesized.
=====================================================================
====
Found no macro
=====================================================================
====

=====================================================================
====
=====================================================================
====
=====================================================================
====
Found no macro
=====================================================================
====
=====================================================================
====
=====================================================================
====
WARNING:Xst:2170 - Unit delaylatch : the following signal(s) form a combinatorial loop:
qbar_and0000.
Optimizing unit <delaylatch> ...

Found area constraint ratio of 100 (+ 5) on block delaylatch, actual ratio is 0.
=====================================================================
====
Found no macro
=====================================================================
====
=====================================================================
====
=====================================================================
====

-------------------------------
-------------------------------
=====================================================================
====
* Final Report *
=====================================================================
====
Final Results
RTL Top Level Output File Name : delaylatch.ngr
Top Level Output File Name : delaylatch
Output Format : NGC
Keep Hierarchy : No
Design Statistics
# IOs :4
Cell Usage :
# BELS :2
# INV :1
# LUT3 :1
# IO Buffers :4
# IBUF :2
# OBUF :2
=====================================================================
====

---------------------------

Number of IOs: 4
---------------------------
---------------------------

---------------------------
=====================================================================
====
TIMING REPORT

Clock Information:
------------------

----------------------------------------
Timing Summary:
---------------
Speed Grade: -4

Timing Detail:
--------------
=====================================================================
====
-------------------------------------------------------------------------
Source: clk (PAD)
Destination: qbar (PAD)
Data Path: clk to qbar

Gate Net
---------------------------------------- ------------

IBUF:I->O 1 0.821 1.140 clk_IBUF (clk_IBUF)

LUT3:I0->O 3 0.551 0.907 q1 (q_OBUF)
INV:I->O 1 0.551 0.801 qbar1_INV_0 (qbar_OBUF)
OBUF:I->O 5.644 qbar_OBUF (qbar)
----------------------------------------
(72.7% logic, 27.3% route)
=====================================================================
====

-->


BLOCK DIAGRAM:
RTL SCHEMATIC:

OUTPUT:

JK FLIP FLOP:
module jkflip(
input clk,
input reset,
input J,
input K,
output reg Q,
output reg Qbar
);
always @(posedge clk)
if(reset)
begin
Q<=0;
Qbar<=0;
end
else if(J==0&&K==0)
begin
Q<=Q;
Qbar<=Qbar;
end
else if(J==0&&K==1)
begin
Q<=0;
Qbar<=1;
end
else if(J==1&&K==0)
begin
Q<=1;
Qbar<=0;
end
else if(J==1&&K==1)
begin
Q<=Qbar;
end
//assign Qbar=~Q;
end
endmodule
TEST BENCH FOR JK FLIP FLOP:
module jkflip;
reg clk;
reg reset;
reg J;
reg K;
wire Q;

wire Qbar;
jkflip uut( clk(clk), reset(reset) J(J), K(K), Q(Q), Qbar(Qbar) );
begin
J=0;K=0;clk=0;reset=1;
#100;
#100;J=0;K=1;
#100;J=1;K=0;
#100;J=1;K=1;
#100;reset=0;J=0;K=0;
#100;J=0;K=1;
#100;J=1;K=0;
#100;J=1;K=1;
#100 $stop;
end always #1;
clk=~clk;

BLOCK DIAGRAM:
RTL SCHEMATIC:

OUTPUT:

T-FLIPFLOP:
module tff(
input rst,
input clk,
input t,
output reg q
);
always@(clk)
begin
if(rst)
q=1'b0;
else
begin
if(t==1'b0)
q=1'b0;
else
q=~q;
end
end
endmodule
TEST BENCH FOR T-FLIPFLOP:

module tfftest;
// Inputs
reg t;
reg clk;
// Outputs
wire q;
wire qbar;
tff uut (
.t(t),
.clk(clk),
.q(q),
);
initial
clk=0;
always
#5 clk=~clk;
initial begin
t= 0;
//clk = 0;
#100 t=1;
#100 t=0;

#100 t=1;
end
endmodule
BLOCK DIAGRAM:
RTL SCHEMATIC:

OUTPUT:

SR -FLIP FLOP:
module srff(
input rst,
input clk,
input s,
input r,
output q
);
reg q;
always@(rst,posedge clk,s,r)
begin
if(rst)
q=1'b0;
else
begin
if(s==1'b0&&r==1'b0)
q=q;
else if(s==1'b0&&r==1'b1)
q=1'b0;
else if(s==1'b1&&r==1'b0)
q=1'b1;
else
q=1'bX;
end
end
endmodule
TEST BENCH FOR SR-FLIP FLOP:

module srfftest;
// Inputs
reg rst;
reg clk;
reg s;
reg r;
// Outputs
wire q;
srff uut (
.rst(rst),
.clk(clk),
.s(s),
.r(r),
.q(q)
);
initial begin

rst = 0;
clk = 0;
s = 0;
r = 0;
#100 s=1'b0;r=1'b0;
#100 s=1'b0;r=1'b1;
#100 s=1'b1;r=1'b0;
#100 s=1'b1;r=1'b1;
end
endmodule

BLOCK DIAGRAM:
RTL SCHEMATIC:

OUTPUT:

ALU:
PROGRAM:
module ALU(A, B, ALU_sel, ALU_out, carryout);
input [7:0] A;
input [7:0] B;
input [3:0] ALU_sel;
output [7:0] ALU_out;
output carryout;
reg[7:0]ALU_result;
wire[8:0]tmp;
assign ALU_out=ALU_result;
assign tmp={1'b0,A}+{1'b0,B};
assign carryout=tmp[8];
always@(*)
begin
case(ALU_sel)
4'b0000:
ALU_result=A+B;
4'b0001:
ALU_result=A-B;
4'b0010:
ALU_result=A*B;
//4'b0011:
//ALU_result=A/B;
4'b0100:

ALU_result=A<<1;
4'b0101:
ALU_result=A>>1;
4'b0110:
ALU_result={A[0],A[7:1]};
4'b0111:
ALU_result={A[0],A[7:1]};
4'b1000:
ALU_result=A&B;
4'b1001:
ALU_result=A|B;
4'b1010:
ALU_result=A^B;
4'b1011:
ALU_result=~(A|B);
4'b1100:
ALU_result=~(A&B);
4'b1101:
ALU_result=~(A^B);
4'b1110:
ALU_result=(A>B)?8'd1:8'd0;
4'b1111:
ALU_result=(A==B)?8'd1:8'd0;

default:
ALU_result=A+B;
endcase
end
endmodule
TEST BENCH:
#50;
A = 8'b01010110;
B = 8'b11011111;
ALU_sel = 4'b1010;
RTL SCHEMATIC:

SYNTHESIS REPORT:
Release 9.2i - xst J.36
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 1.00 s
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 1.00 s

--> Reading design: ALU.prj
TABLE OF CONTENTS
2) HDL Compilation
4) HDL Analysis
5) HDL Synthesis
8) Partition Report
9) Final Report
9.3) TIMING REPORT
=====================================================================
====
=====================================================================
====
Input File Name : "ALU.prj"

Output File Name : "ALU"
Output Format : NGC
Target Device : xc3s100e-4-vq100
---- Source Options
Top Module Name : ALU
FSM Style : lut
RAM Style : Auto
Mux Style : Auto
Priority Encoder Extraction : YES
ROM Style : Auto
Mux Extraction : YES

Multiplier Style : auto
---- Target Options
Slice Packing : YES
Pack IO Registers into IOBs : auto
Library Search Order : ALU.lso
Keep Hierarchy : NO
RTL Output : Yes

Read Cores : YES
Bus Delimiter : <>
Case Specifier : maintain
Verilog 2001 : YES
Slice Utilization Ratio Delta :5
=====================================================================
====
=====================================================================
====
* HDL Compilation *
=====================================================================
====
Compiling verilog file "alu.v" in library work
Module <ALU> compiled
Analysis of file <"ALU.prj"> succeeded.

=====================================================================
====
=====================================================================
====
Analyzing hierarchy for module <ALU> in library <work>.
=====================================================================
====
* HDL Analysis *
=====================================================================
====
Analyzing top module <ALU>.
Module <ALU> is correct for synthesis.
=====================================================================
====
* HDL Synthesis *
=====================================================================
====
Synthesizing Unit <ALU>.

Related source file is "alu.v".
WARNING:Xst:646 - Signal <tmp<7:0>> is assigned but never used.
WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
WARNING:Xst:643 - "alu.v" line 41: The result of a 8x8-bit multiplication is partially used.
Only the 8 least significant bits are used. If you are doing this on purpose, you may safely ignore
this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit
behavior.
WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
Found 8-bit addsub for signal <ALU_result$addsub0000>.
Found 8-bit comparator equal for signal <ALU_result$cmp_eq0013> created at line 69.
Found 8-bit comparator greater for signal <ALU_result$cmp_gt0000> created at line 67.
Found 8x8-bit multiplier for signal <ALU_result$mult0001> created at line 41.
Found 8-bit xor2 for signal <ALU_result$xor0000> created at line 57.
Found 9-bit adder for signal <tmp>.
Summary:
inferred 2 Adder/Subtractor(s).
inferred 1 Multiplier(s).
inferred 2 Comparator(s).
Unit <ALU> synthesized.
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic
operations in this design can share the same physical resources for reduced device utilization.
For improved clock frequency you may try to disable resource sharing.
=====================================================================
====

Macro Statistics
# Multipliers :1
8x8-bit multiplier :1
# Adders/Subtractors :2
8-bit addsub :1
9-bit adder :1
# Comparators :2
8-bit comparator equal :1
8-bit comparator greater :1
# Xors :1
8-bit xor2 :1
=====================================================================
====
=====================================================================
====
=====================================================================
====
Loading device for application Rf_Device from file '3s100e.nph' in environment C:\Xilinx92i.
=====================================================================
====

Macro Statistics
# Multipliers :1
8x8-bit multiplier :1
# Adders/Subtractors :2
8-bit addsub :1
9-bit adder :1
# Comparators :2
8-bit comparator equal :1
8-bit comparator greater :1
# Xors :1
8-bit xor2 :1
=====================================================================
====
=====================================================================
====
=====================================================================
====
Optimizing unit <ALU> ...

Found area constraint ratio of 100 (+ 5) on block ALU, actual ratio is 6.
=====================================================================
====
Found no macro
=====================================================================
====
=====================================================================
====
=====================================================================
====
-------------------------------
-------------------------------
=====================================================================
====

* Final Report *
=====================================================================
====
Final Results
RTL Top Level Output File Name : ALU.ngr
Top Level Output File Name : ALU
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs : 29
Cell Usage :
# BELS : 134
# GND :1
# LUT2 : 20
# LUT3 : 22
# LUT4 : 50
# MUXCY : 23
# MUXF5 :9
# VCC :1
# XORCY :8
# IO Buffers : 29
# IBUF : 20

# OBUF :9
# MULTs :1
# MULT18X18SIO :1
=====================================================================
====
---------------------------
Selected Device : 3s100evq100-4
Number of IOs: 29
Number of MULT18X18SIOs: 1 out of 4 25%
---------------------------
---------------------------
---------------------------

=====================================================================
====
TIMING REPORT
Clock Information:
------------------
----------------------------------------
Timing Summary:
---------------
Speed Grade: -4

Timing Detail:
--------------
=====================================================================
====
-------------------------------------------------------------------------
Source: ALU_sel<3> (PAD)
Destination: ALU_out<7> (PAD)
Data Path: ALU_sel<3> to ALU_out<7>
Gate Net
---------------------------------------- ------------
IBUF:I->O 23 1.218 1.377 ALU_sel_3_IBUF (ALU_sel_3_IBUF)
LUT4:I0->O 9 0.704 0.855 ALU_result_cmp_eq00142 (ALU_result_cmp_eq0014)
LUT3:I2->O 1 0.704 0.000 Maddsub_ALU_result_addsub0000_lut<0> (N14)
MUXCY:S->O 1 0.464 0.000 Maddsub_ALU_result_addsub0000_cy<0>

(Maddsub_ALU_result_addsub0000_cy<0>)
MUXCY:CI->O 1 0.059 0.000 Maddsub_ALU_result_addsub0000_cy<1>







XORCY:CI->O 1 0.804 0.595 Maddsub_ALU_result_addsub0000_xor<7>

(ALU_result_addsub0000<7>)
LUT4:I0->O 1 0.704 0.424 ALU_result<7>159 (ALU_result<7>_map41)
LUT2:I1->O 1 0.704 0.420 ALU_result<7>229 (ALU_out_7_OBUF)
OBUF:I->O 3.272 ALU_out_7_OBUF (ALU_out<7>)
----------------------------------------
(68.4% logic, 31.6% route)
=====================================================================
====
CPU : 5.39 / 5.81 s | Elapsed : 5.00 / 6.00 s
-->

MOORE MODEL:
module moone(clk, reset, x1, out);
input clk;
input reset;
input x1;
output out;
library IEEE
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entry fsm is
port(clk,reset,x1: in STD_LOIC:
OUT P:OUT std_logic);
end fsm:
architecture behavioral of fsm is
type state_type is(s1,s2,s3,s4);
signal state:state_type;
begin
process(clk,reset)
begin
if (reset='1')then
state<=s1;

out<='1';
else if(clk='1' and clk'event)then
case state is
when s1=>if x1='1' then state <=s2;
else state<=s3;
out<='1';
when s2=>state <=s4;out <='1';
end case;
end if;
end process;
end behavioural;
endmodule
Test Bench:
#100 a=1'b0;clk=1'b0;
#100 a=1'b0;clk=1'b1;
#100 a=1'b1;clk=1'b0;
#100 a=1'b1;clk=1’b1;

SIMULATION:
MEALY MODEL:
PROGRAM
module mealy1(a, clk, z);
input a;
input clk;

output z;
reg z;
parameter st0=0,st1=1,st2=2,st3=3;
reg[0:1]mealy_state;
initial
begin
mealy_state=st0;
end
always@(posedge clk)
case(mealy_state)
st0:
begin
z=1;
if(a)begin
mealy_state=st3;
end
else
z=0;
end
st1:
begin
if(a)begin
z=0;
mealy_state=st0;
end

else
z=1;
end
st2:
begin
if (a) begin
z=1;
mealy_state=st1;
end
else
z=0;
end
st3:
begin
z=0;
if(a) begin
mealy_state=st1;
end
mealy_state=st2;
end
endcase
endmodule
Test Bench:
#100a=1'b0;clk=1'b0;

#100a=1'b0;clk=1'b1;
#100a=1'b1;clk=1'b0;
#100a=1'b1;clk=1'b1;
SYNTHESIS REPORT:
elease 9.2i - xst J.36
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.11 s | Elapsed : 0.00 / 0.00 s
--> Parameter xsthdpdir set to ./xst

CPU : 0.00 / 0.11 s | Elapsed : 0.00 / 0.00 s
--> Reading design: mealy1.prj
TABLE OF CONTENTS
2) HDL Compilation
4) HDL Analysis
5) HDL Synthesis
8) Partition Report
9) Final Report
9.3) TIMING REPORT
=====================================================================
====
=====================================================================
====
Input File Name : "mealy1.prj"

Output File Name : "mealy1"
Output Format : NGC
---- Source Options
Top Module Name : mealy1
FSM Style : lut
RAM Style : Auto
Mux Style : Auto
Priority Encoder Extraction : YES
ROM Style : Auto
Mux Extraction : YES

Multiplier Style : auto
---- Target Options
Add Generic Clock Buffer(BUFG) :8
Slice Packing : YES
Pack IO Registers into IOBs : auto
Library Search Order : mealy1.lso
Keep Hierarchy : NO
RTL Output : Yes
Read Cores : YES

Bus Delimiter : <>
Case Specifier : maintain
Verilog 2001 : YES
Slice Utilization Ratio Delta :5
* HDL Compilation *
=====================================================================
====
Compiling verilog file "mealy1.v" in library work
Module <mealy1> compiled
No errors in compilation.Analysis of file <"mealy1.prj"> succeeded.
=====================================================================
====
=====================================================================
====
Analyzing hierarchy for module <mealy1> in library <work> with parameters.
st0 = "00000000000000000000000000000000"
st1 = "00000000000000000000000000000001"
st2 = "00000000000000000000000000000010"
st3 = "00000000000000000000000000000011"
=====================================================================
====

* HDL Analysis *
=====================================================================
====
Analyzing top module <mealy1>.
st0 = 32'sb00000000000000000000000000000000
st1 = 32'sb00000000000000000000000000000001
st2 = 32'sb00000000000000000000000000000010
st3 = 32'sb00000000000000000000000000000011
Module <mealy1> is correct for synthesis.
=====================================================================
====
* HDL Synthesis *
Synthesizing Unit <mealy1>.
Related source file is "mealy1.v".
Found 1-bit register for signal <z>.
Found 2-bit register for signal <mealy_state>.
Summary:
inferred 3 D-type flip-flop(s).
Unit <mealy1>
synthesized.============================================================
=============
Macro Statistics
# Registers :2
1-bit register :1

2-bit register :1
=====================================================================
====
Loading device for application Rf_Device from file '3s400.nph' in environment C:\Xilinx92i.
=====================================================================
====
Macro Statistics
# Registers :3
Flip-Flops :3
=====================================================================
====Optimizing unit <mealy1> ...
INFO:Xst:2261 - The FF/Latch <mealy_state_1> in Unit <mealy1> is equivalent to the

following FF/Latch, which will be removed : <z>
Found area constraint ratio of 100 (+ 5) on block mealy1, actual ratio is 0.

=====================================================================
====
Macro Statistics
# Registers :2
Flip-Flops :2
=====================================================================
====
-------------------------------
* Final Report *
=====================================================================
====
Final Results
RTL Top Level Output File Name : mealy1.ngr
Top Level Output File Name : mealy1
Output Format : NGC
Keep Hierarchy : NO
Design Statistics

# IOs :3
Cell Usage :
# BELS :2
# LUT3 :2
# FlipFlops/Latches :2
# FD :2
# Clock Buffers :1
# BUFGP :1
# IO Buffers :2
# IBUF :1
# OBUF :1
Number of Slice Flip Flops: 2 out of 7168 0%
Number of IOs: 3
Number of GCLKs: 1 out of 8 12%
TIMING REPORT

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |2 |
-----------------------------------+------------------------+-------+
----------------------------------------
Timing Summary:
Speed Grade: -4
Minimum period: 2.576ns (Maximum Frequency: 388.199MHz)
Minimum input arrival time before clock: 2.791ns
Maximum output required time after clock: 7.271ns
Maximum combinational path delay: No path found
Timing Detail:

=====================================================================
====
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 2.576ns (frequency: 388.199MHz)
-------------------------------------------------------------------------
Source: mealy_state_1 (FF)
Destination: mealy_state_1 (FF)
Source Clock: clk rising
Destination Clock: clk rising
Data Path: mealy_state_1 to mealy_state_1
Gate Net
---------------------------------------- ------------
FD:C->Q 3 0.720 1.102 mealy_state_1 (mealy_state_1)
LUT3:I1->O 1 0.551 0.000 mealy_state_mux0000<1>1

(mealy_state_mux0000<1>)
FD:D 0.203 mealy_state_1
----------------------------------------
(57.2% logic, 42.8% route)
=====================================================================
====

Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
-------------------------------------------------------------------------
Offset: 2.791ns (Levels of Logic = 2)
Source: a (PAD)
Destination: mealy_state_1 (FF)
Destination Clock: clk rising
Data Path: a to mealy_state_1
Gate Net
---------------------------------------- ------------
IBUF:I->O 2 0.821 1.216 a_IBUF (a_IBUF)
LUT3:I0->O 1 0.551 0.000 mealy_state_mux0000<1>1

(mealy_state_mux0000<1>)
FD:D 0.203 mealy_state_1
----------------------------------------
(56.4% logic, 43.6% route)
=====================================================================
====
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
-------------------------------------------------------------------------
Offset: 7.271ns (Levels of Logic = 1)

Source: mealy_state_1 (FF)
Destination: z (PAD)
Source Clock: clk rising
Data Path: mealy_state_1 to z
Gate Net
---------------------------------------- ------------
FD:C->Q 3 0.720 0.907 mealy_state_1 (mealy_state_1)
OBUF:I->O 5.644 z_OBUF (z)
----------------------------------------
(87.5% logic, 12.5% route)
=====================================================================
====
CPU : 2.58 / 2.70 s | Elapsed : 3.00 / 3.00 s
-->

RING COUNTER:
module reg(clk, start, reset, comp, digitlaout, done);
input clk;
input start;
input reset;
input comp;
output [3:0] digitlaout;
output done;
reg[3:0]ring_count;
reg[3:0]digitl;
wire D4,set0,set1,set2,set3;
assign D4 = ring_count[0];
assign done = !D4;
always@(posedge clk or negedge reset)
begin
if(~reset)
ring_count<=4'b1000;
else
begin
if(start)
endmodule

RING COUNTER ANOTHER METHOD:
module register(clk, start, reset, comp, digitalout, done);
input clk;
input start;
input reset;
input comp;
output digitalout;
output done;
reg[3:0]ring_count;
reg[3:0]digital;
wire D4,set0,set1,set2,set3;
assign D4=ring_count[0];
assign done=!D4;
begin
if(~reset)
else
begin
if(start)
else
ring_count<=(ring_count>>1);
end
end

assign set3=ring_count[3];
begin
if(~reset)
digital[3]<=1'b1;else
if(start)
digital[3]<=1'b1;
else if(set3)
digital[3]<=comp;
end
always @(posedge clk or negedge reset)
begin
if(~reset)
digital[2]<=1'b1;else
if(start)
digital[2]<=1'b1;
else if(set2)
digital[2]<=comp;
end
endmodule

SHIFT REGISTER:
/////////////////////////////////////////////////////////////////////////////////
module shift1(clk, rst, mode, datain, dataout);
input clk;
input rst;
input [1:0] mode;

input [3:0] datain;
output reg [3:0] dataout;
begin
if(rst)
dataout<=0;
else
begin
case(mode)
2'b00:dataout<=dataout;
2'b01:dataout<={datain[0],dataout[3:1]};
2'b10:dataout<={dataout[2:0],datain[0]};
2'b11:dataout<=datain;
endcase
end
end
endmodule
test:
module universalshifttest_v;
// Inputs
reg clk;
reg rst;
reg [1:0] mode;

reg [3:0] datain;
// Outputs
wire [3:0] dataout;
shift1 uut (
.clk(clk),
.rst(rst),
.mode(mode),
.datain(datain),
.dataout(dataout)
);
initial begin
clk = 0;
rst = 0;
mode = 0;
datain = 0;
#100;mode=2'b00;datain=4'b1010;
#100;mode=2'b01;datain=4'b1010;
#100;mode=2'b10;datain=4'b1010;
#100;mode=2'b11;datain=4'b1010;

end
endmodule
SIMULATION:
RTL SCHEMATIC:

RESULT:
Thus the sequential circuits are designed and implemented using Verilog HDL by Xilinx and the
output is obtained

EXP NO: DESIGN OF LOGIC GATES USING MICROWIND

DATE:
AIM:
To implement and design logic gates using Microwind
APPARATUS REQUIRED:
1) PC
2) Microwind Software
PROCEDURE:
1. Open the layouteditor(L-Edit) from Tanner EDA tools.
2. Select the new file and enter the file type and enter the cell name in the new cell
section.
3. Making use of the pallets in L-Edit draw the required layers for the layout.
4. Each layer should be based on the lambda values.
5. Check for DRC for any error at each level of layer.
6. Output waveform is viewed in the waveform viewer.

INVERTER GATE:
PSPICE FOR INVERTER GATE:

CIRCUIT C:\Documents and Settings\vlsia2\Desktop\Example.MSK
*
* IC Technology: unknown
*
VDD 1 0 DC 5.00
Vclock1 11 0 PULSE(0.00 5.00 0.90N 0.10N 0.10N 0.90N 2.00N)
*
* List of nodes
* "s1" corresponds to n°4
* "N7" corresponds to n°7
* "clock1" corresponds to n°11
*
* MOS devices
MN1 0 7 4 0 N1 W= 2.00U L= 1.00U
MN2 9 11 7 0 N1 W= 2.00U L= 1.00U
MN3 0 12 9 0 N1 W= 2.00U L= 1.00U
MP1 1 7 4 1 P1 W= 2.00U L= 1.00U
MP2 7 11 1 1 P1 W= 2.00U L= 1.00U
MP3 1 12 7 1 P1 W= 2.00U L= 1.00U
*
*
* n-MOS Model 3 :
*?
.MODEL N1 NMOS LEVEL=3 VTO=0.70 UO=600.000 TOX= 3.0E-9
+LD =0.000U THETA=0.350 GAMMA=0.350
+PHI=0.680 KAPPA=0.010 VMAX=130.00K
+CGSO=100.0p CGDO=100.0p
+CGBO= 60.0p CJSW=240.0p
*
* p-MOS Model 3:
*?
.MODEL P1 PMOS LEVEL=3 VTO=-1.00 UO=300.000 TOX= 3.0E-9
+LD =0.000U THETA=0.350 GAMMA=0.350
+PHI=0.680 KAPPA=0.010 VMAX=100.00K
*
* Transient analysis
*
.TEMP 27.0
.TRAN 0.1N 20.00N

* (Pspice)
.PROBE
.END
CMOS INVEERTER LAYOUT:
3D LAYOUT FOR INVERTER:
OUTPUT:

NAND GATE:
PSPICE FOR NAND GATE:

*
*
VDD 1 0 DC 5.00
*
* List of nodes
*
* MOS devices
MN1 0 7 4 0 N1 W= 2.00U L= 1.00U
MN2 9 11 7 0 N1 W= 2.00U L= 1.00U
MN3 0 12 9 0 N1 W= 2.00U L= 1.00U
MP1 1 7 4 1 P1 W= 2.00U L= 1.00U
MP2 7 11 1 1 P1 W= 2.00U L= 1.00U
MP3 1 12 7 1 P1 W= 2.00U L= 1.00U
*
*
* n-MOS Model 3 :
*?
+LD =0.000U THETA=0.350 GAMMA=0.350
+PHI=0.680 KAPPA=0.010 VMAX=130.00K
*
* p-MOS Model 3:
*?
+LD =0.000U THETA=0.350 GAMMA=0.350
+PHI=0.680 KAPPA=0.010 VMAX=100.00K
*
*
.TEMP 27.0

.TRAN 0.1N 20.00N

* (Pspice)
.PROBE
.END

NAND GATE LAYOUT:
3D MODEL FOR NAND GATE:
OUTPUT:

AND GATE:
PSPICE FOR AND GATE:

*
*
VDD 1 0 DC 5.00
*
* List of nodes
*
* MOS devices
MN1 0 7 4 0 N1 W= 2.00U L= 1.00U
MN2 9 11 7 0 N1 W= 2.00U L= 1.00U
MN3 0 12 9 0 N1 W= 2.00U L= 1.00U
MP1 1 7 4 1 P1 W= 2.00U L= 1.00U
MP2 7 11 1 1 P1 W= 2.00U L= 1.00U
MP3 1 12 7 1 P1 W= 2.00U L= 1.00U
*
*
* n-MOS Model 3 :
*?
+LD =0.000U THETA=0.350 GAMMA=0.350
+PHI=0.680 KAPPA=0.010 VMAX=130.00K

*
* p-MOS Model 3:
*?
+LD =0.000U THETA=0.350 GAMMA=0.350
+PHI=0.680 KAPPA=0.010 VMAX=100.00K
*
*
.TEMP 27.0
.TRAN 0.1N 20.00N
* (Pspice)
.PROBE
.END

AND GATE LAYOUT:
3D MODEL FOR AND GATE:
OUTPUT:

NOR GATE:
PSPICE FOR NOR GATE:

*
*
VDD 1 0 DC 5.00
*
* List of nodes
*
* MOS devices
MN1 0 7 4 0 N1 W= 2.00U L= 1.00U
MN2 9 11 7 0 N1 W= 2.00U L= 1.00U
MN3 0 12 9 0 N1 W= 2.00U L= 1.00U
MP1 1 7 4 1 P1 W= 2.00U L= 1.00U
MP2 7 11 1 1 P1 W= 2.00U L= 1.00U
MP3 1 12 7 1 P1 W= 2.00U L= 1.00U
*
*
* n-MOS Model 3 :
*?
+LD =0.000U THETA=0.350 GAMMA=0.350
+PHI=0.680 KAPPA=0.010 VMAX=130.00K
*
* p-MOS Model 3:
*?
+LD =0.000U THETA=0.350 GAMMA=0.350
+PHI=0.680 KAPPA=0.010 VMAX=100.00K
*
*
.TEMP 27.0
.TRAN 0.1N 20.00N
* (Pspice)
.PROBE
.END

NOR GATE LAYOUT:
3D MODEL FOR NOR GATE:
OUTPUT:

OR GATE:
PSPICE FOR OR GATE:

*
*
VDD 1 0 DC 5.00
*
* List of nodes
*
* MOS devices
MN1 0 7 4 0 N1 W= 2.00U L= 1.00U
MN2 9 11 7 0 N1 W= 2.00U L= 1.00U
MN3 0 12 9 0 N1 W= 2.00U L= 1.00U
MP1 1 7 4 1 P1 W= 2.00U L= 1.00U
MP2 7 11 1 1 P1 W= 2.00U L= 1.00U
MP3 1 12 7 1 P1 W= 2.00U L= 1.00U
*
*
* n-MOS Model 3 :
*?
+LD =0.000U THETA=0.350 GAMMA=0.350
+PHI=0.680 KAPPA=0.010 VMAX=130.00K

*
* p-MOS Model 3:
*?
+LD =0.000U THETA=0.350 GAMMA=0.350
+PHI=0.680 KAPPA=0.010 VMAX=100.00K
*
*
.TEMP 27.0
.TRAN 0.1N 20.00N
* (Pspice)
.PROBE
.END
OR GATE:
3D MODEL FOR OR GATE:
OUTPUT:

RESULT:
Thus the design and implementation of Logic gates using Microwind layout is executed and the
output is obtained.

EXP NO: DESIGN OF LOGIC GATES USING TANNER

DATE:
AIM:
To implement and design logic gates using Tanner
APPARATUS REQUIRED:
1) PC
2) Tanner Software
PROCEDURE:
1) To launch S-Edit in PC, go to START > PROGRAMS > TANNER > S-EDIT
2) Click on Module 🡪 Symbol Browser or click on to launch the symbol browser window.
Choose your device and click on Place
3) Once the main parts are in place, it is time to add I/O pins and wire the parts together.
Select and place an Input Pad and an Output pad on the schematic and give the pads a
unique name.
4) Now using the wiring tool make appropriate connections
5) Once Design Entry is over, Click and open T-Spice, then open Insert Command Dialog
and select Transient🡪 Enter the time step and length 🡪Click Insert
6) Select Transient Result by expanding Output 🡪Enter the node to be traced.Select Voltage
Sources and Enter the values for inputs stream
7) Finally all the Commands are entered in Module0 Window. Save and run Simulation.
Expand Chart to view the output

NOT GATE:
OUTPUT:

NETLIST GENERATOR FOR NOT GATE:
Device and node counts:

MOSFETs - 2 MOSFET geometries - 2
BJTs - 0 JFETs - 0
MESFETs - 0 Diodes - 0
Capacitors - 1 Resistors - 0
Inductors - 0 Mutual inductors - 0
Transmission lines - 0 Coupled transmission lines - 0
Voltage sources - 2 Current sources - 0
VCVS – 0 VCCS - 0
CCVS – 0 CCCS - 0
V-control switch – 0 I-control switch - 0
Macro devices – 0 Functional model instances - 0
Subcircuits – 0 Subcircuit instances - 0
Independent nodes - 1 Boundary nodes - 3
Total nodes - 4
Parsing 0.01 seconds
Setup 0.00 seconds
DC operating point 0.00 seconds
Transient Analysis 0.04 seconds
-----------------------------------------
Total 0.05 seconds

AND GATE:
OUTPUT:

NETLIST GENERATOR FOR AND GATE:

BJTs - 0 JFETs - 0
VCVS - 0 VCCS - 0
CCVS - 0 CCCS - 0
V-control switch - 0 I-control switch - 0
Macro devices - 0 Functional model instances - 0
Subcircuits - 0 Subcircuit instances - 0
Total nodes - 6
*** 1 WARNING MESSAGES GENERATED
Setup 0.00 seconds
-----------------------------------------
Total 0.04 seconds

NOR GATE:
OUTPUT:

NETLIST GENERATOR FOR NOR GATE:

BJTs - 0 JFETs - 0
VCVS - 0 VCCS - 0
CCVS - 0 CCCS - 0
Total nodes - 6
Setup 0.00 seconds
-----------------------------------------
Total 0.05 seconds

OR GATE:
OUTPUT:

NETLIST GENERATOR FOR NOR GATE:

BJTs - 0 JFETs - 0
VCVS - 0 VCCS - 0
CCVS - 0 CCCS - 0
Total nodes - 6
Setup 0.00 seconds
-----------------------------------------
Total 0.05 seconds

RESULT:
Thus the logic gates were designed and implemented using tanner was executed and the output
was obtained

EXP NO: IMPLEMENTATION OF COMBINATIONAL CIRCUITS

DATE: USING FPGA
AIM:
To implement and design combinational circuits using FPGA
APPARATUS REQUIRED:
1) PC
3) Xilinx FPGA
PROCEDURE:
Next\
code
7) By using the command User Constraint 🡪Floorplan I/O 🡪 Click YES. Enter PIN
Details🡪Save🡪 Click OK.
8) RUN🡪 IMPLEMENT DesignRUN🡪Generate Program file RUN 🡪Configure Target
device🡪 Manage configuration project🡪 IMPACT Window opens up.
9) After Clicking Finish 🡪Assign New Configuration File Dialog Opens up-🡪 Click
Bypass. After Clicking Bypass 🡪Assign New Configuration File Dialog Opens
up🡪Select bit file🡪 Click open.
10) Right Click the second IC and select Program. Click on Apply🡪OK
11) Check the output in kit
PROGRAM FOF FULL ADDER:

module fulladdr(
input a,
input b,
input c,
output sum,
output carry
);
wire x,y,z;
xor(x,a,b);
and(y,a,b);
xor(sum,x,c);
and(z,x,c);
or(carry,z,y);
endmodule

UCF FOR FULL ADDER:

net “a” loc=p34;
net “b” loc=p44;
net “c” loc=p57;
net “sum” loc=p71;
net “carry” loc=p72;
OUTPUT:

FLOOR PLAN:
ROUTER DESIGN:

PROGRAM FOR FULL SUBTRACTOR:

module fullsubtr(
input a,
input b,
input c,
output diff,
output borrow
);
wire x,y,z,l,m;
xor r1(x,a,b);
xor r2(diff,x,c);
not n1(l,a);
not n2(m,x);
and p1(y,l,b);
and p2(z,m,c);
or s1(borrow,z,y);
endmodule
UCF FOR FULL SUBTRACTOR:

net “a” loc=p34;
net “b” loc=p44;
net “c” loc=p57;
net “diff” loc=p71;
net “borrow” loc=p72;
OUTPUT:

FLOOR PLAN:
ROUTING TABLE:

RESULT:
Thus the design and implementation of combinational circuits was executed by using FPGA and
the output was obtained as shown.

EXP NO: IMPLEMENTATION OF SEQUENTIAL CIRCUITS

DATE: USING FPGA
AIM:
To implement and design sequential circuits using FPGA
APPARATUS REQUIRED:
1)PC
2)Xilinx ISE Design Suite 13.1
3)Xilinx FPGA
PROCEDURE:
Next
code
7) By using the command User Constraint 🡪Floorplan I/O 🡪 Click YES. Enter PIN
Details🡪Save🡪 Click OK.
8) RUN🡪 IMPLEMENT DesignRUN🡪Generate Program file RUN 🡪Configure Target
device🡪 Manage configuration project🡪 IMPACT Window opens up.
9) After Clicking Finish 🡪Assign New Configuration File Dialog Opens up-🡪 Click Bypass.
After Clicking Bypass 🡪Assign New Configuration File Dialog Opens up🡪Select bit
file🡪 Click open.
10) Right Click the second IC and select Program. Click on Apply🡪OK
11) Check the output in kit
PROGRAM FOR JK FLIPFLOP:
module jkflip(
input clk,
input reset,
input J,
input K,
output reg Q,
output reg Qbar
);
if(reset)
begin
Q<=0;
Qbar<=0;
end

else if(J==0&&K==0)
begin
Q<=Q;
Qbar<=Qbar;
end
else if(J==0&&K==1)
begin
Q<=0;
Qbar<=1;
end
else if(J==1&&K==0)
begin
Q<=1;
Qbar<=0;
end
else if(J==1&&K==1)
begin
Q<=Qbar;
end
//assign Qbar=~Q;
end
endmodule
UCF FOR JKFLIPFLOP:

net "clk" loc=p181;
net "rst" loc=p182;
net “J” loc=p34;
net “K” loc=p44;
net “Q” loc=p71;
net “Qbar” loc=p72;

OUTPUT:
FLOOR PLAN:

ROUTING TABLE:
PROGRAM FOR COUNTER USING DELAY:
module counterusingdellay(
input clk,
input reset,
output reg [3:0] dout
);
reg[21: 0]delay;
wire en;
always@(posedge reset or posedge clk)
begin
if(reset)
delay = 22'b0;
else
delay = delay +1;
end
assign en=(delay ==22'b1111010000100100000000);
always@(posedge clk)
begin
if(((reset )||(dout>=15)))
dout=4'b0000;
else if(en)
dout=dout+1;
end
endmodule

UCF FOR COUNTER USING DELAY:

net "clk" loc=p181;
net "rst" loc=p182;
net "dout[3]"loc=p58;
OUTPUT:
FLOOR PLAN:

ROUTING TABLE:
RESULT:
Thus the design and implementation of sequential circuits was executed by using FPGA and the
output was obtained as shown.

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EC8661 VLSI DESIGN LABORATORY

EXP NO: DESIGN OF COMBINATIONAL CIRCUIT

DATA FLOW MODEL:

VEL TECH HIGH TECH 1 DEPARTMENT OF ECE

TEST BENCH FOR FULL ADDER:

VEL TECH HIGH TECH 2 DEPARTMENT OF ECE

Total REAL time to Xst completion: 0.00 secs

--> Parameter xsthdpdir set to xst

Total REAL time to Xst completion: 0.00 secs

--> Reading design: fulladdrfpga.prj

VEL TECH HIGH TECH 3 DEPARTMENT OF ECE

Input File Name : "fulladdrfpga.prj"

---- Target Parameters

---- Source Options

---- Target Options

---- General Options

VEL TECH HIGH TECH 4 DEPARTMENT OF ECE

VEL TECH HIGH TECH 5 DEPARTMENT OF ECE

Module <fulladdrfpga> is correct for synthesis.

Performing bidirectional port resolution...

Synthesizing Unit <fulladdrfpga>.

VEL TECH HIGH TECH 6 DEPARTMENT OF ECE

Optimizing unit <fulladdrfpga> ...

Mapping all equations...

Final Macro Processing ...

Partition Implementation Status

No Partitions were found in this design.

VEL TECH HIGH TECH 7 DEPARTMENT OF ECE

Device utilization summary:

Selected Device : 3s400pq208-4

Number of Slices: 1 out of 3584 0%

No Partitions were found in this design.

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

Asynchronous Control Signals Information:

VEL TECH HIGH TECH 8 DEPARTMENT OF ECE

Minimum period: No path found

VEL TECH HIGH TECH 9 DEPARTMENT OF ECE

VEL TECH HIGH TECH 10 DEPARTMENT OF ECE

VEL TECH HIGH TECH 11 DEPARTMENT OF ECE

TEST BENCH FOR HALF ADDER:

VEL TECH HIGH TECH 12 DEPARTMENT OF ECE

VEL TECH HIGH TECH 13 DEPARTMENT OF ECE

VEL TECH HIGH TECH 14 DEPARTMENT OF ECE

TEST BENCH FOR FULL SUBTRACTOR:

VEL TECH HIGH TECH 15 DEPARTMENT OF ECE

VEL TECH HIGH TECH 16 DEPARTMENT OF ECE

VEL TECH HIGH TECH 17 DEPARTMENT OF ECE

VEL TECH HIGH TECH 18 DEPARTMENT OF ECE

TEST BENCH FOR HALF SUBTRACTOR:

VEL TECH HIGH TECH 19 DEPARTMENT OF ECE

VEL TECH HIGH TECH 20 DEPARTMENT OF ECE

VEL TECH HIGH TECH 21 DEPARTMENT OF ECE

TEST BENCH FOR ENCODER:

VEL TECH HIGH TECH 22 DEPARTMENT OF ECE

VEL TECH HIGH TECH 23 DEPARTMENT OF ECE

VEL TECH HIGH TECH 24 DEPARTMENT OF ECE

VEL TECH HIGH TECH 25 DEPARTMENT OF ECE

TEST BENCH FOR DECODER:

// Instantiate the Unit Under Test (UUT)

VEL TECH HIGH TECH 26 DEPARTMENT OF ECE

Release 13.1 - xst O.40d (nt)

Total REAL time to Xst completion: 0.00 secs

--> Parameter xsthdpdir set to xst

Total REAL time to Xst completion: 0.00 secs