ASIC & FPGA IMPLEMENTATION OF

MODIFIED ADVANCED ENCRYPTION

STANDARD

GUIDE: Dr. SREENIDHI P R AKSHAYA ANAND

ASST. PROFESSOR M.Tech VLSI DESIGN, Sem III

DEPT OF ELECTRONICS & COMMUNICATION ENGINEERING AM.EN.P2VLD20002

AMRITAPURI
1
OUTLINE OF THE PRESENTATION

 A brief introduction of the project idea

 Literature Review
 Problem Definition
 Objective of the work
 Methodology
 Block diagram
 Schedule/Time plan of the work process
 References

2
 INTRODUCTION

 Over the last decade, Hardware Security has developed to become one of the major
research areas in Electronics and Computer Engineering and Computer Science.
 Hardware Security research deals with cutting-edge problems and their solutions in the
domains of Detection and Prevention of several attacks.

3
S.No TITLE
LITERATURE REVIEW AUTHOR SUMMARY YEAR

1. High-throughput field-programable gate array Prateek Sikka, Abhijit R. Asati, Propsed a high-throughput FPGA implementation of the AES 2021
implementation of the advanced encryption Chandra Shekhar: algorithm for automotivemicrocontrollers using a 128-bit key
standard algorithm for automotive security created via Vivado high-level synthesis (HLS) tool
applications.

2. Optimization of Advanced Encryption Standard on Cihangir Tezcan Focused on the performance of the Advanced Encryption 2021
Graphics Processing Units Standard (AES) on GPUs. They presented optimizations
which remove bank conflicts in shared memory accesses and
provide 878.6 Gbps throughput for AES-128 encryption

3. A Modified Advanced Encryption Standard for Lin Teng, Hang Li, Shoulin Yin, and A modified advanced encryption standard for data security in 2020
Data Security Yang Sun cloud computing is proposed by introducing random
disturbance information to improve the data security.

4. Security vulnerability in Internet of Things sensor Pasquale Arpaia, Francesco This paper reports the preliminary results of a side-channel 2020
networks protected by Bonavolonta, Antonella Cioff attack (scatter attack) addressed on an 8-bit IoT
Advanced Encryption Standard microcontroller protected by AES

5. The enhancement of security measures in advanced B. Srikanth, M. Siva Kumar, J.V.R. This research aims to develop the floating point double 2020
encryption standard using double precision floating Ravindra, K. Hari Kishore precision Furer Toom cook fast integer multiplication model
point in the Advanced Encryption Standard process round to
multiplication model enhance the security measures in communication channel.

4
S.No TITLE AUTHOR SUMMARY YEAR

6. A highly efficient and secure hardware implementation of the M. Masoumi A highly efficient and power analysis attack 2019
advanced encryption standard robust architecture for AES which combines a
randomized SBox with a modified Boolean
masking technique.

7. Modified Advanced Encryption Standard Algorithm for Oluwakemi Christiana Abikoye,Ahmad This paper presents an enhanced AES 2019
Information Security Dokoro Haruna, Abdullahi Abubakar,Noah algorithm that was achieved by modifying its
Oluwatobi Akande,Emmanuel Oluwatobi SubBytes and ShiftRows transformations
Asani

8. Optimization of Advanced Encryption Standard (AES) Using
Vivado High Level Synthesis (HLS)
Luka Daoud, Fady Hussein, and Nader Rafla
This paper present the implementation of AES 2019
encryption processor on FPGA using Xilinx
Vivado HLS. The AES architecture was
analyzed and designed by loop unrolling,
and inner-round and outer-round pipelining
techniques

9. Low Gate-Count Ultra-Small Area Nano Advanced A. Shreedhar, K.-S. Chong, N. K. Z. Lwin, N. This paper present a low gate-count ultra- 2019
Encryption Standard (AES) Design A. Kyaw, L. Nalangilli, W. Shu, J. S. Chang, small area 128-bit nano AES design using the
and B.-H. Gwee area efficient S-Box and MixColumn circuit
implementations,

10. MAES: Modified advanced encryption standard for resource A. R. Chowdhury, J. Mahmud, A. R. M. Optimization of algorithms in terms of energy 2018
constraint environments Kamal and M. A. Hamid consumption is presented. Efficiency rate of
MAES is around 18.35% in terms of packet
transmission which indicates MAES consumes
less energy than AES

5
 PROBLEM DEFINITION

The goal of this work is to implement a modified Advanced Encryption

Standard(AES) algorithm in both FPGA & ASIC that can produce a high
throughput, fully pipelined ultra-high-speed version, low power and low
area core useful for USB4 IP core.

6
OBJECTIVE OF THE WORK

 Both encryption and decryption process are carried out

 Throughput, Area, Power and Speed optimized design of AES
 FPGA implementation of the IP core
 RTL to GDS implementation of the core (ASIC)
 Design of the core that supports different key lengths (128,192,256 bits)

7
METHODOLOGY

 RTL design & verification of the design and

FPGA implementation

Tool used: Xilinix Vivado.

 ASIC development from synthesis to signoff

Synthesis: Cadence Genus

Static timing analysis: Cadence Tempus
Placement and Routing: Cadence Innovus.

8
BLOCK DIAGRAM

9
 SCHEDULE/TIME PLAN

July - Aug Sept -Nov December Dec-Jan

• Project selection • Block Level RTL • FPGA • Mini project

• Literature Survey Design implementation and review and
• Block level FPGA synthesis Report writing
representation • RTL Verification

10
 SCHEDULE/TIME PLAN

SCHEDULE III SEMESTER IV SEMESTER

JULY - SEPT (3) OCT - NOV (2) DEC -FEB (3) MAR - MAY(3)
RTL DESIGN
RTL VERIFICATION
FPGA IMPLEMENTATION
ASIC SYNTHESIS
STATIC TIMING ANALYSIS
BACKEND DESIGN
REPORT WRITING
 REFERENCES
[1] Prateek Sikka, Abhijit R. Asati, Chandra Shekhar, “High-throughput field-programable gate array implementation of the advanced
encryption standard algorithm for automotive security applications”. J. Ambient Intell. Humaniz. Comput. 12(7): 7273-7279 (2021)
[2] Cihangir Tezcan, “Optimization of Advanced Encryption Standardon Graphics Processing Units”, Digital Object Identifier, IEEE Access,
Vol. 9, 2021
[3] Lin Teng, Hang Li, Shoulin Yin, and Yang Sun, “A Modified Advanced Encryption Standard for Data Security” International Journal of
Network Security, Vol.22, No.1, PP.112-117, Jan. 2020 (DOI: 10.6633/IJNS.20200122(1).11)
[4] Pasquale Arpaia, Francesco Bonavolonta, Antonella Cioff, “Security vulnerability in Internet of Things sensor networks
protected byAdvanced Encryption Standard”, IEEE Xplore 978-1-7281-4892-2/20/$31.00 ©2020 IEEE
[5] B. Srikanth, M. Siva Kumar, J.V.R. Ravindra, K. Hari Kishore, “The enhancement of security measures in advanced encryption
standard using double precision floating point multiplication model ”Trans Emerging Tel Tech. 2020;e3948.
wileyonlinelibrary.com/journal/ett ,John Wiley & Sons, Ltd. pp. 1-13, https://doi.org/10.1002/ett.3948, 2020.
[6] M. Masoumi, “A highly efficient and secure hardware implementation of the advanced encryption standard” Journal of Information
Security and Applications, 2214-2126/© Elsevier Ltd. , 2019.
[7] Oluwakemi Christiana Abikoye,Ahmad Dokoro Haruna, Abdullahi Abubakar,Noah Oluwatobi Akande,Emmanuel Oluwatobi Asani,
“Modified Advanced Encryption Standard Algorithm for Information Security”, Symmetry 2019, 11, 1484; doi:10.3390/sym11121484
[8] Luka Daoud, Fady Hussein, and Nader Rafla, “Optimization of Advanced Encryption Standard (AES) Using Vivado High Level
Synthesis (HLS)”, Proceedings of 34th International Conference on Computers and Their Applications, Volume 58, 2019, Pages 36–44,
2019.
[9] A. Shreedhar, K.-S. Chong, N. K. Z. Lwin, N. A. Kyaw, L. Nalangilli, W. Shu, J. S. Chang, and B.-H. Gwee, “Low Gate-Count Ultra-
Small Area Nano Advanced Encryption Standard (AES) Design ” ISCAS:1-5, 2019.
[10] A. R. Chowdhury, J. Mahmud, A. R. M. Kamal and M. A. Hamid, "MAES: Modified advanced encryption standard for resource
constraint environments," 2018 IEEE Sensors Applications Symposium (SAS), 2018, pp. 1-6, doi: 10.1109/SAS.2018.8336747.
11
THANKYOU!

ANY QUERIES?
12