SCHOOL OF COMPUTER ENGINEERING

KALINGA INSTITUTE OF INDUSTRIAL TECHNOLOGY

DEEMED TO BE UNIVERSITY

BHUBANESWAR

LESSON – PLAN
School : School of Computer Engineering

Program : B. Tech. CSE

Academic Session : Autumn Semester 2023 (July. - November)

Subject : High Performance Computing (HPC) (CS 3010)

Course Cridit : 4 (L-T-P) (3-1-0) (Weekly 4 Hours)

Semester : 5th Semester

Course Faculty : Dr.Manoj Kumar Mishra

Mail_id : (manojfcs@kiit.ac.in)

Course Outcomes/Learning Objectives:

1. Understand different quantitative techniques used to measure the performance of the

system with various criteria like CPI, CPU time, speed up, throughput, efficiency, etc.

2. Understand the concept of different types of hazards along with their structural
implementation and applications.

3. Identify the criteria to enhance the performance of pipelined processors.

4. Understand ILP and the techniques to exploit ILP in scalar, super-scalar, super pipelined
processor, and the VLIW processor.

5. Understand memory hierarchy and to analyze various Cache optimization techniques.

6. Classify various parallel architecture like centralized and distributed memory architecture

Prerequisite: Computer Architecture (CS-2006)

Teaching Pedagogy: Whiteboard/Marker, PowerPoint Presentations, Web Resources

Assessment Methodology: Mid Term: 20; End Term: 50

Distribution of Internal Marks:- Total 50 Marks

Mid Semester Examination = 20 Marks
Activity-based assessment=30 Marks
Activity-based assessment includes Problem Solving, Critical
Thinking, Creation along with Quiz.
 LESSON – PLAN

Module No. & name / Topics/ Coverage Lecture serial COUrse No of

Section no. Name Number outcome classes

Introduction To High Lecture-1 CO 1

performance
Module-1
Computer
Architecture

Review of basic Lecture-2 CO-1

computer
architectures
Overview of

Computer

Architecture Introduction to Lecture -3 CO-1

09
instruction Set
architecture (ISA)
CISC & RISC
processor with
examples

Measuring and Lecture 4 CO-1

Reporting
Performance
Processor
performance
equation (with
numerical)
Performance
measurement with
respect to execution
time, CPU
time(concept with lecture 5
numerical)

Performance Lecture -6 CO-1

Measurement with
respect to the basic
performance
equation (concept Lecture -7
with numerical)
Amdahl’s law
(concept with
Exercises on
speedup and overall
 speedup calculation) Lecture 8

Tutorial(Doubt Lecture 9 CO-1

clearing)

Activity -1

Problem
Solving/Critical
Thinking/Quiz

Module-2 Basic concepts to Lecture -10 CO-2 10

parallel processing &
pipelining pipelining Concept.

Introduction to Lecture-11 CO-2

MIPS Architecture
with its data path
Registers in MIPS
MIPS Instruction
Format(R type,I Lecture-12
Type and J type)

MIPS Instruction Lecture -13 CO-2

set with examples
MIPS Data-path and
Control
 A brief introduction Lecture-14 CO-2
to Hazard and Types
of Hazards
(Concepts and
exercises) Lecture 15
Structural Hazard
Data Hazard (Inter-
instruction
dependency with
suitable examples:) Lecture-16
Control Hazard

Pipeline Stall Cycles Lecture-17

and its possible
effects on
performance
(Concepts and
exercises)

A technique for CO-2

overcoming or
reducing the
effects of Various
hazards (Solutions
to different
Lecture-18
Hazards) (concepts
and numericals)
Operand forwarding
and Instruction
Lecture -19
scheduling
Flush pipeline,
Branch Prediction,
Delay Slot

Lecture -20

Tutorial (doubt CO-2

clearing) Problem
Solving/Critical
Activity -2 Thinking/Quiz CO-2

Module-3 Concepts of Lecture-21 CO-3

instruction-level
Instruction
parallelism (ILP)
Level Techniques for Lecture-22 CO-3
increasing ILP
Parallelism 09
Dynamic branch
(ILP)
prediction

Loop Lecture-23 CO-3

unrolling(concepts
with Numerical)

Static scheduling Lecture-24 CO-4

With example

Dynamic scheduling Lecture-25 CO-4

Dynamic scheduling
approach
1.Scoreboard
approach (With
Numerical)
Lecture-29

2.Tomasulo’s
approach (With
Numerical)

Lecture-26

Super-scalar & Super Lecture-27 CO-4

pipelined

VLIW processor Lecture-28 CO-4

architecture

Tutorial (DOUBT CO-4

clearing)
Problem
Solving/Critical
Activity-3 CO-4
Thinking/Quiz

Mid sem exam

Module-4 Memory hierarchy Lecture-29 CO-5 09
(Inclusion, Coherence
Hierarchical
and locality
Memory properties)
Technology

Cache memory Lecture-30 CO-5

organization

Block Placement

Block Identification
Block Replacement

Write Strategy
Lecture-31

Cache Memory Lecture-32 CO-5

Performance
evaluation (concepts
and numerical
examples)

Cache Memory Lecture-33 CO-5

Optimization
Techniques (concepts
and numerical
examples)

Reduce miss rate. Lecture-34 CO-5

Larger block size

Larger cache size

Higher associativity

Lecture-35

Reduce miss penalty. Lecture-36 CO-5

Multilevel caches

Priority to Read
Misses over Writes

Reduce hit time. Lecture-37 CO-5

Avoiding address
translation
 Tutorial(Doubt CO-5
clearinf)

Activity-4 CO-5
Problem
Solving/Critical
Thinking/Quiz

Module-5 Taxonomy of Parallel Lecture-38 CO-6 9

Architecture
Multiprocessor

Architecture
Multiprocessor Lecture-39 CO-6
Systems

Centralized Shared-
memory architecture
(Tightly coupled
multiprocessor like
UMA)

Distributed Shared Lecture-40 CO-6

memory architecture
(Loosely coupled
multiprocessor like
NUMA)

Lecture-41

Cache coherence Lecture-42 CO-6

Mechanism

Snooping Lecture-43 CO-6

protocol(Concepts
and numerical
examples)

Directory-based Lecture-44 CO-6

protocol(Concepts
and numerical
examples)

Tutorial(Doubt Lecture-45 CO-6

clearing)

Activity 5 and CO-6

Activity 6
Problem
Solving/Critical
Thinking/Quiz

Previous year Q and Lecture-46

answer discussion
Text Book :
1. John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative
Approach, Morgan Kaufmann.
References Books :
1. John Paul Shen and Mikko H. Lipasti, Modern Processor Design: Fundamentals of
Superscalar Processors, Tata McGraw-Hill.
2. M. J. Flynn, Computer Architecture: Pipelined and Parallel Processor Design, Narosa
Publishing House.
3. Kai Hwang, Advanced Computer Architecture: Parallelism, Scalability,
Programmability, McGraw- Hill.

Dr. Manoj Kumar Mishra

Signature