Week 7

Path Oriented DEcision
Making
(PODEM)
Ganesh C. Patil
Tuesday, November 7, 2023

1
PODEM -- Goel
IBM
(1981)
 New concepts introduced:
 Expand binary decision tree only
around primary inputs
 Use X-PATH-CHECK to test whether
D-frontier still there
 Objectives -- bring ATPG closer to
propagating D (D) to PO
 Backtracing

2
Motivation
 IBM introduced semiconductor DRAM
memory into its mainframes – late
1970’s
 Memory had error correction and
translation circuits – improved
reliability
 D-ALG unable to test these circuits
 Search too undirected
 Large XOR-gate trees
 Must set all external inputs to define output
 Needed a better ATPG tool
3
PODEM High-Level Flow
1. Assign binary value to unassigned PI
2. Determine implications of all PIs
3. Test Generated? If so, done.
4. Test possible with more assigned PIs? If
maybe, go to Step 1
5. Is there untried combination of values on
assigned PIs? If not, exit: untestable fault
6. Set untried combination of values on
assigned PIs using objectives and
backtrace. Then, go to Step 2

4
PODEM-Algorithm

5
PODEM

6
D-Algorithm : Example

7
PODEM : Example

8
PODEM : Value

9
PODEM : Decision Tree

10
Example 3 – Fault s sa1
D
sa1

11
Example 3 – Step 1 s sa1
 Select path s – Y for fault propagation
sa1

12
Example 3 – Step 2 s sa1
 Initial objective: Set r to 1 to sensitize fault
sa1

13
Example 3 -- Step 3 s sa1
 Backtrace from r
sa1

14
 Set A = 0 in implication stack
1
0
sa1

15
 Forward implications: d = 0, X = 1
1
1
0
0
sa1

16
 Initial objective: set r to 1
1
1
0
0
sa1

17
 Backtrace from r again
1
1
0
0
sa1

18
 Set B to 1. Implications in stack: A = 0, B = 1
1
1
0
0
1 sa1

19
 Forward implications: k = 1, m = 0, r = 1, q = 1,
Y = 1, s = D, u = D, v = D, Z = 1
1
1
0
0
1 0 sa1 D 1
1 1
D
D
1

20
Backtrack -- Step 10 s sa1
 X-PATH-CHECK shows paths s – Y and
s – u – v – Z blocked (D-frontier disappeared)
1
1
0
0
sa1

21
Step 11 -- s sa1
 Set B = 0 (alternate assignment)
1
0
0 sa1

22
Backtrack -- s sa1
 Forward implications: d = 0, X = 1, m = 1, r = 0,
s = 1, q = 0, Y = 1, v = 0, Z = 1. Fault not sensitized
1
0
0
0
1
0 1 sa1
1
0
1
0
1

23
Step 13 -- s sa1
 Set A = 1 (alternate assignment)
1
1
sa1

24
Step 14 -- s sa1
 Backtrace from r again
1
1
sa1

25
Step 15 -- s sa1
 Set B = 0. Implications in stack: A = 1, B = 0
1
1
0 sa1

26
Backtrack -- s sa1
 Forward implications: d = 0, X = 1, m = 1, r = 0.
Conflict: fault not sensitized. Backtrack
1
0
1
0
1
0 1 sa1
1
0
1
0
1

27
Step 17 -- s sa1
 Set B = 1 (alternate assignment)
1
1
1 sa1

28
Fault Tested -- Step 18 s sa1
 Forward implications: d = 1, m = 1, r = 1, q = 0,
s = D, v = D, X = 0, Y = D
0
1
1
1
1 1 sa1 D
D
0
D
D
X

29
 D-ALG – First complete ATPG algorithm
 D-Cube
 D-Calculus
 Implications – forward and backward
 Implication stack
 Backup
 PODEM
 Expand decision tree only around PIs
 Use X-PATH-CHECK to see if D-frontier exists
 Objectives -- bring ATPG closer to getting
D (D) to PO
 Backtracing
30
Fault Coverage and Efficiency
# of detected faults
Fault coverage = Total # faults
= # of detected faults
Fault Total # faults -- # undetectable faults
efficiency

31
History of Algorithm Speedups
Algorithm Est. speedup over D-ALG Year
(normalized to D-ALG time)
D-ALG 1 1966
PODEM 7 1981
FAN 23 1983
TOPS 292 1987
SOCRATES 1574 †ATPG System 1988
Waicukauski et al. 2189 †ATPG System 1990
EST 8765 †ATPG System 1991
TRAN 3005 †ATPG System 1993
Recursive learning 485 1995
Tafertshofer et al. 25057 1997

32
Sequential Circuit ATPG
Ganesh C. Patil

33
Sequential Circuits
Huffman Model of a sequential circuit

34
Sequential Circuits
 A sequential circuit has memory in
addition to combinational logic.
 Test for a fault in a sequential circuit is
a sequence of vectors, which
 Initializes the circuit to a known state
 Activates the fault, and
 Propagates the fault effect to a primary output
 Methods of sequential circuit ATPG
 Time-frame expansion methods
 Simulation-based methods

35
Example: A Serial Adder
An Bn
1 1
s-a-0
D
1
1 D
X
Cn
Cn+1
X
Combinational logic 1
Sn X
FF

36
Time-Frame Expansion
An-1 Bn-1 An Bn
Time-frame -1 Time-frame 0
1 1 1 1
s-a-0 D s-a-0
X D D
1 1
Cn-1 1 D X D
Cn 1 1
Cn+1
X
1
Combinational logic Combinational logic 1
Sn-1 Sn
X
D
FF

37
Concept of Time-Frames
 If the test sequence for a single stuck-at
fault contains n vectors,
 Replicate combinational logic block n times
 Place fault in each block
 Generate a test for the stuck-at fault using
combinational ATPG
Vector – n +1 Vector – 1 Vector 0

Fault
Unknown Time- State Time- Time- Next

or given Frame variables frame frame state
Init. state - n+1 -1 0
Comb.
block PO – n +1 PO – 1 PO 0
38
Example for Logic Systems
FF1
B
A FF2
s-a-1

39
Five-Valued Logic (Roth)
0,1, D, D, X
A 0 A 0
s-a-1 s-a-1
D D
X X X
FF1 FF1
X D D
FF2 FF2
B X B X

40
Algebras: Roth’s 5-Valued and Muth’s
9-Valued
Good Failing
Symbol Meaning Machine Machine
D 1/0 1 0
D 0/1 0 1 Roth’s
0 0/0 0 0 Algebra
1 1/1 1 1
X X/X X X
G0 0/X 0 X
G1 1/X 1 X Muth’s
F0 X/0 X 0 Additions
F1 X/1 X 1

41
Nine-Valued Logic (Muth)
0,1, 1/0, 0/1, 1/X, 0/X, X/0, X/1, X
A 0 A X
s-a-1 s-a-1 0/1

0/1 X/1
X 0/X 0/X
FF1 FF1
X 0/1 X/1
FF2 FF2
0/1
B X B 0/1

42
Implementation of ATPG
 Select a PO for fault detection based on drivability
analysis.
 Place a logic value, 1/0 or 0/1, depending on fault type
and number of inversions.
 Justify the output value from PIs, considering all
necessary paths and adding backward time-frames.
 If justification is impossible, then use drivability to
select another PO and repeat justification.
 If the procedure fails for all reachable POs, then the
fault is untestable.
 If 1/0 or 0/1 cannot be justified at any PO, but 1/X or 0/X
can be justified, the the fault is potentially detectable.

43
Drivability Example
The process of selecting an output and activation of paths is based on a
testability measure called drivability
(11, 16)
(10, 15) (22, 17)
(10, 16)
d(0/1) =
8
d(0/1) = 4 s-a-1
d(0/1) = d(1/0) = 32
8
8
d(1/0) =
(5, 9) d(1/0) = 20
(4, 4)
(17, 11)
(CC0, CC1) d(0/1) = 9 (6, 10)
FF d(0/1) = 120
d(1/0) =
8
= (6, 4) d(0/1) = 109 d(1/0) = 27

d(1/0) =
8
CC0 and CC1 are SCOAP combinational controllabilities
d(0/1) and d(1/0) of a line are effort measures for driving

a specific fault effect to that line

44
Complexity of ATPG
 Synchronous circuit -- All flip-flops controlled by clocks; PI and
PO synchronized with clock:
 Cycle-free circuit – No feedback among flip-flops: Test
generation for a fault needs no more than dseq + 1 time-
frames, where dseq is the sequential depth.
 Cyclic circuit – Contains feedback among flip-flops: May
need 9Nff time-frames, where Nff is the number of flip-
flops.
 Asynchronous circuit – Higher complexity!
Smax Time- Time- S3 Time- S2 Time- S1 Time- S0

Frame Frame Frame Frame Frame
max-1 max-2 -2 -1 0
max = Number of distinct vectors with 9-valued elements = 9Nff

45
Cycle-Free Circuits
 Characterized by absence of cycles
among flip-flops and a sequential depth,
dseq.
 dseq is the maximum number of flip-
flops on any path between PI and PO.
 Both good and faulty circuits are
initializable.

46
Cycle-Free Example
Circuit
F2
2
All faults are
F3 testable in
F1 this circuit.
Level = 1 3
F2
2
s - graph
F1 F3 dseq = 3
Level = 1 3

47
Cyclic Circuit Example
Modulo-3 counter
Z
CNT F2
F1
s - graph
F1 F2

48
Modulo-3 Counter
 Cyclic structure – Sequential depth is
undefined.
 Circuit is not initializable. No tests can be
generated for any stuck-at fault.
 After expanding the circuit to 9Nff = 81, or
fewer, time-frames ATPG program calls any
given target fault untestable.
 Circuit can only be functionally tested by
multiple observations.
 Functional tests, when simulated, give no
fault coverage.
49
Adding Initializing Hardware
Initializable modulo-3 counter
Z
CNT F2
F1
s-a-0
s-a-1
CLR
s-a-1 s-a-1 Untestable fault
Potentially detectable faults
s - graph
F1 F2

50
Benchmark Circuits
Circuit s1196 s1238 s1488 s1494
PI 14 14 8 8
PO 14 14 19 19
FF 18 18 6 6
Gates 529 508 653 647
Structure Cycle-free Cycle-free Cyclic Cyclic
Seq. depth 4 4 -- --
Total faults 1242 1355 1486 1506
Detected faults 1239 1283 1384 1379
Potentially detected faults 0 0 2 2
Untestable faults 3 72 26 30
Fault coverage (%) 99.8 94.7 93.1 91.6

Fault efficiency (%) 100.0 100.0 94.8 93.4
Total test vectors 313 308 525 559

51
Thank you !!!

52
Asynchronous Circuit ATPG
Ganesh C. Patil

53
Combinational Loop
Combinational Circuit
Combinational Loop/Asynchronous loop/ loop/
Synchronous latch

54
Asynchronous Circuit
Synchronous Circuit

55
 An asynchronous circuit contains unclocked memory
often realized by combinational feedback.
 Almost impossible to build, let alone test, a large
asynchronous circuit.
 Many large synchronous systems contain small
portions of localized asynchronous circuitry.
 Sequential circuit ATPG should be able to generate
tests for circuits with limited asynchronous parts,
even if it does not detect faults in those parts.

56
Asynchronous Model
CK Synchronous PIs
Combinational
Feedback Paths:
Feedback set
Feedback-free
Combinational
PPI Logic PPO
CK Synchronous POs
System Clocked
Clock, CK Flip-flops
Fast model Feedback

Modeling circuit is
Clock, FMCK delays
Shown in orange.
57
Time-Frame Expansion
Vector k
PI
Feedback Feedback
C C C C
set set
CK FMCK FMCK FMCK PPO
PPI
PO Asynchronous feedback
stabilization
Time-frame Time-frame
-k+1 Time-frame k -k-1

58
Simulation based Methods
 Difficulties with time-frame method:
 Long initialization sequence
 Impossible to guarantee initialization with three-
valued logic (Section 5.3.4)
 Circuit modeling limitations
 Timing problems – tests can cause races/hazards
 High complexity
 Inadequacy for asynchronous circuits
 Advantages of simulation-based methods
 Advanced fault simulation technology
 Accurate simulation model exists for verification
 Variety of tests – functional, heuristic, random
 Used since early 1960s

59
Contest
 A Concurrent test generator for sequential
circuit testing (Contest).
 Search for tests is guided by cost-functions.
 Three-phase test generation:
 Initialization – no faults targeted; cost-function computed
by true-value simulator.
 Concurrent phase – all faults targeted; cost function
computed by a concurrent fault simulator.
 Single fault phase – faults targeted one at a time; cost
function computed by true-value simulation and dynamic
testability analysis.

60
Genetic Algorithms (GAs)
 Theory of evolution by natural selection (Darwin, 1809-82.)
 C. R. Darwin, On the Origin of Species by Means of Natural
Selection, London: John Murray, 1859.
 J. H. Holland, Adaptation in Natural and Artificial Systems, Ann
Arbor: University of Michigan Press, 1975.
 D. E. Goldberg, Genetic Algorithms in Search, Optimization, and
Machine Learning, Reading, Massachusetts: Addison-Wesley, 1989.
 P. Mazumder and E. M. Rudnick, Genetic Algorithms for VLSI Design,
Layout and Test Automation, Upper Saddle River, New Jersey:
Prentice Hall PTR, 1999.
 Basic Idea: Population improves with each generation.
 Population
 Fitness criteria
 Regeneration rules

61
GAs for Test Generation
 Population: A set of input vectors or vector
sequences.
 Fitness function: Quantitative measures of
population succeeding in tasks like
initialization and fault detection (reciprocal to
cost functions.)
 Regeneration rules (heuristics): Members
with higher fitness function values are
selected to produce new members via
transformations like mutation and crossover.

62
Difficulties in Seq. ATPG
 Poor initializability.
 Poor controllability/observability of state
variables.
 Gate count, number of flip-flops, and
sequential
 depth do not explain the problem.
 Cycles are mainly responsible for complexity.

63
Finite State Machines
 A fault in a machine M0 transforms into another machine Mi
with n or fewer states
 A test sequence is a sequence of inputs that distinguishes M0
from each of Mi defined by a fault
 A synchronizing sequence for a sequential machine M is an
input sequence whose application is guaranteed to leave M in
a certain final state irrespective of initial state of M
 A homing sequence for M is an input sequence whose
application makes it possible to determine the final state of M
by observing the corresponding output sequence that M
produces
 A distinguishing sequence is an input sequence whose
application makes it possible to determine the initial state of M
by observing the corresponding output sequence M produces

64
Scan Design
 Circuit is designed using pre-specified design rules.
 Test structure (hardware) is added to the verified
design:
 Add a test control (TC) primary input.
 Replace flip-flops by scan flip-flops (SFF) and connect to form
one or more shift registers in the test mode.
 Make input/output of each scan shift register
controllable/observable from PI/PO.
 Use combinational ATPG to obtain tests for all
testable faults in the combinational logic.
 Add shift register tests and convert ATPG tests into
scan sequences for use in manufacturing test.

65
Scan Design Rules
 Use only clocked D-type of flip-flops for all
state variables.
 At least one PI pin must be available for test;
more pins, if available, can be used.
 All clocks must be controlled from PIs.
 Clocks must not feed data inputs of flip-flops.

66
Correcting a Rule Violation
 All clocks must be controlled from PIs.

Comb.
logic D1 Q
FF Comb.
D2 logic
CK
Comb.
logic
Q
D1
D2 FF Comb.
CK logic

67
Thank you !!!

68

Week 7

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Week 7

Uploaded by

Copyright:

Available Formats

Path Oriented DEcision

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Huffman Model of a sequential circuit

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Vector – n +1 Vector – 1 Vector 0

Unknown Time- State Time- Time- Next

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

s-a-1 s-a-1 0/1

Tuesday, November 7, 2023

Tuesday, November 7, 2023

= (6, 4) d(0/1) = 109 d(1/0) = 27

d(0/1) and d(1/0) of a line are effort measures for driving

Tuesday, November 7, 2023

Smax Time- Time- S3 Time- S2 Time- S1 Time- S0

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Fault coverage (%) 99.8 94.7 93.1 91.6

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Combinational Loop/Asynchronous loop/ loop/

Tuesday, November 7, 2023

Tuesday, November 7, 2023

Tuesday, November 7, 2023