Lecture-7

Memory-2
CSE-2823
Computer Architecture
Dr. Md. Waliur Rahman Miah
Associate Professor, CSE, DUET

1
 Today’s Topic

Memory
Part-2

Ref:
Hennessy-Patterson 5e-Ch-5; 4e-Ch-7
Stallings 8e-Ch-4-5-6
Dr. Md. Waliur Rahman Miah Dept of CSE, DUET 2
 Caches
• By simple example
– assume block size = one word of data
X4 X4

X1 X1

Xn – 2 Xn – 2
Reference to Xn
causes miss so
Xn – 1 Xn – 1 it is fetched from
memory
X2 X2
Xn

X3 X3

a. Before the reference to Xn b. After the reference to Xn

• Issues:
– how do we know if a data item is in the cache?
– if it is, how do we find it?
– if not, what do we do?
• Solution depends on cache addressing scheme…
Dr. Md. Waliur Rahman Miah Dept of CSE, DUET
 General Organization of a Cache
Cache is an array 1 valid bit t tag bits B = 2b bytes
of sets per line per line per cache block
Each set contains
valid tag 0 1 • • • B–1
one or more lines E lines
set 0: •••
per set
Each line holds a valid tag 0 1 • • • B–1
block of data
valid tag 0 1 • • • B–1
S = 2s sets set 1: •••
valid tag 0 1 • • • B–1

•••
valid tag 0 1 • • • B–1
set S-1: •••
valid tag 0 1 • • • B–1

Cache size:
Dr. Md. Waliur Rahman Miah
C = B x E x S data bytes
Dept of CSE, DUET
 Addressing Caches
Address A:
t bits s bits b bits
m-1 0
v tag 0 1 • • • B–1
set 0: •••
v tag 0 1 • • • B–1 <tag> <set index> <block offset>

v tag 0 1 • • • B–1
set 1: •••
v tag 0 1 • • • B–1

•••
The word at address A is in the cache if
v tag 0 1 • • • B–1
set S-1: ••• the tag bits in one of the <valid> lines in
v tag 0 1 • • • B–1 set <set index> match <tag>

The word contents begin at offset

<block offset> bytes from the beginning
Dr. Md. Waliur Rahman Miah of the
Dept blockDUET
of CSE,
 Addressing Caches
Address A:
t bits s bits b bits
m-1 0
v tag 0 1 • • • B–1
set 0: •••
v tag 0 1 • • • B–1 <tag> <set index> <block offset>

v tag 0 1 • • • B–1
set 1: •••
v tag 0 1 • • • B–1

•••
1. Locate the set based on
v tag 0 1 • • • B–1
set S-1: ••• <set index>
v tag 0 1 • • • B–1 2. Locate the line in the set based on
<tag>
3. Check that the line is valid
4. Locate the data in the line based on
Dr. Md. Waliur Rahman Miah Dept<block
of CSE, offset>
DUET
 Direct-Mapped Cache
Simplest kind of cache, easy to build
(only 1 tag compare required per access)
Characterized by exactly one line per set.
set 0: valid tag cache block E=1 lines per set

set 1: valid tag cache block

•••

set S-1: valid tag cache block

Cache size: C = B x S data bytes

Dr. Md. Waliur Rahman Miah Dept of CSE, DUET
 Direct Mapped Cache(1)

• Addressing scheme in direct mapped cache:

– cache block address = memory block address mod cache size
(unique)
– if cache size = 2m, cache address = lower m bits of n-bit
memory address
– remaining upper n-m bits kept as a tag bits at each cache
block
– also need a valid bit to recognize a valid entry

Dr. Md. Waliur Rahman Miah Dept of CSE, DUET

 Direct Mapped Cache(2)

Dr. Md. Waliur Rahman Miah Dept of CSE, DUET

 Accessing Direct-Mapped Caches
Set selection
– Use the set index bits to determine the set of interest.

set 0: valid tag cache block

selected set
set 1: valid tag cache block
•••

set S-1: valid tag cache block

t bits s bits b bits

00001
m-1 0
tag set index block offset
Dr. Md. Waliur Rahman Miah Dept of CSE, DUET
 Accessing Direct-Mapped Caches
Line matching and word selection
– Line matching: Find a valid line in the selected set with
a matching tag
– Word selection: Then extract the word
=1? (1) The valid bit must be set
0 1 2 3 4 5 6 7

selected set (i): 1 0110 b0 b1 b2 b3

(2) The tag bits in the
cache line must =? If (1) and (2), then cache hit
match the tag bits
in the address
t bits s bits b bits
0110 i 100
m-1
tag set index block offset0
Dr. Md. Waliur Rahman Miah Dept of CSE, DUET
 Accessing Direct-Mapped Caches
Line matching and word selection
– Line matching: Find a valid line in the selected set with
a matching tag
– Word selection: Then extract the word

0 1 2 3 4 5 6 7

selected set (i): 1 0110 b0 b1 b2 b3

(3) If cache hit,

block offset selects
starting byte.
t bits s bits b bits
0110 i 100
m-1
tag set index block offset0
Dr. Md. Waliur Rahman Miah Dept of CSE, DUET
 Accessing Direct-Mapped Cache Example1
• Example:
(0) Initial state: (1) Address referred 10110 (miss):
Index V Tag Data Index V Tag Data
000 N 000 N
001 N 001 N
010 N 010 N
011 N 011 N
100 N 100 N
101 N 101 N
110 N 110 Y 10 Mem(10110)
111 N 111 N

Dr. Md. Waliur Rahman Miah Dept of CSE, DUET

 (2) Address referred 11010 (miss): (3) Address referred 10110 (hit):

Index V Tag Data Index V Tag Data

000 N 000 N
001 N 001 N
010 Y 11 Mem(11010) 010 Y 11 Mem(11010)
011 N 011 N
100 N 100 N to CPU

101 N 101 N
110 Y 10 Mem(10110) 110 Y 10 Mem(10110)
111 N 111 N
(4) Address referred 10010 (miss):

Index V Tag Data

000 N
001 N
010 Y 10 Mem(10010)
011 N
100 N
101 N
110 Y 10 Mem(10110)
111 N
Dr. Md. Waliur Rahman Miah Dept of CSE, DUET
 Accessing Direct-Mapped Cache Example2
M=16 byte addresses, B=2 bytes/block,
t=1 s=2 b=1 S=4 sets, E=1 entry/set
x xx x
Address trace (reads):
0 [00002], miss
1 [00012], hit
7 [01112], miss
8 [10002], miss
0 [00002] miss

v tag data
0
1 ?1
0 ?
M[8-9]
M[0-1]

1 0 M[6-7]
Dr. Md. Waliur Rahman Miah Dept of CSE, DUET
 Direct Mapped Cache

Cache with 1024

1-word blocks
byte offset
(least 2 significant bits) is ignored
and
next 10 bits used to index into
cache

Dr. Md. Waliur Rahman Miah Dept of CSE, DUET

 Reference
[1] Patterson, D. A., & Hennessy, J. L. (2014). Computer
organization and design: The hardware/software
interface (5th ed.). Burlington, MA: Morgan Kaufmann
Publishers.

[2] William Stallings, (2010), Computer Organization and

Architecture,(8th Ed), Prentice Hall Upper Saddle River, NJ
07458.

[3] Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Naraig

Manjikian, (2012), Computer Organization and
Embedded Systems (6th Ed), McGraw-Hill, New York, NY
10020.

Dr. Md. Waliur Rahman Miah Dept of CSE, DUET 17