RV 32 I Vs RV 64I – classification is based on integer REGISTER width (32/64)

Whereas other architectures

usually treat their ISA as a single entity, which changes to a new version as instructions are added

over time, RISC-V will endeavor to keep the base and each standard extension constant over time,

and instead layer new instructions as further optional extensions. For example, the base integer

ISAs will continue as fully supported standalone ISAs, regardless of any subsequent extensions.

 memory address computations wraps around and taken modulo 2power XLEN

Purpose of FENCE.I

RV 32 I – has 32 bit wide #32 registers

RV 32 E – 16 numbers of 32 bits registers – 32E is meant for microcontrollers

RV 64 – I – has 64 bit wide #32 registers

R I S U instruction formats; RI U J FORMATS; THEN WE HAVE S U FORMATS AS WELL

Instruction address misaligned exception

Instruction-address-misaligned exceptions are reported on the branch or jump that would

cause instruction misalignment to help debugging, and to simplify hardware design for systems

with IALIGN=32, where these are the only places where misalignment can occur.

Immediate values ARE SIGN EXTENDED

No integer Computational Instructions cause arithmetic exceptions. But overflow checks are done
with other instructions like bltu blt, slti, slt, bne etc.

Typically 12 bit immediates (mostly) and LUI has 20 bits immediates.

FENCE.I Extension

Compressed Instruction Set

Misaligned Atomics

RVWMO

RV TSO

What is our processor behaviour when misaligned

load and store happens? Do we support? Or raise exception
when misaligned load / store happens…..
RV 32 OPCODES + instructions

XLEN = 32 – REGISTER WIDTH

OP-IMM – addi, sltiu, andi,ori,xori, (slli,srli,srai)- shift amount in 5 bits , nop as addi
x0,x0,0

LUI – 20 BITS IMMEDIATE

AUIPC – 20 BITS IMM

OP – add, slt,sltu,and,or,xor,(sll,srl,sub,sra) – shift amount in 5 bits

JAL

JALR

BRANCH

LOAD width indicates 8,16,32

STORE width indicates 8,16,32

MISC-MEM-FENCE

SYSTEM-ECALL, EBREAK

HINT

Zifencei opcodes – MISC-MEM-FENCE.I

RV32 – E – ONLY 16 REGISTERS AND ALL THE OTHER SIMILAR TO RV32E

RV-64 I opcodes + instructions – differences from RV 32 I

XLEN = 64; REGISTER WIDTH

OP-IMM-32 – BASICALLY 32 BITS COMPUTATIONS – addiw,slliw,srliw,sraiw

OP-IMM – slli,srli,srai shift amount in 6 bits for 64 bits registers

AUI

LUIPC

OP – sll,srl,sra – shift amount in 6 bits – 64 bit registers

OP-32-addw,sllw,srlw,subw,sraw – basically 32 bits computations (sign / zero extended in 64 bits

registers) in RV 64 – I

LOAD – width indicates 8,16,32,64

STORE – width indicates 8,16,32,64

HINT

M extension – int mul and divide – Opcodes + instructions

OP – MUL MULH MULHSU DIVU REMU

OP-32 – MULW DIVUW REMUW

A – Extensions

AMO – LR W /D SC W /D - word for 32 BITS and double word for 64 bits – BOTH ARE
IMPLEMENTED FOR RV 64. RV 32 IMPLEMENTS ONLY LR W SC W. In RV 64

Zam

Zicsr – csr extensions

Counters

RVWMO

Ztso

C EXTENSION

THINGS TODO FOR ENABLING C extensions in a RISC-V 64IMAFD

IALIGN

ILEN
16 bit aa =00, 01, 10

32 bits – aa = 11 ONLY

Non-conforming extensions – how to enable

Ignore and don’t provide 16 bit C ISE and use aa=00, 01, 10 as non conforming extensions

Endianness
X0 hardwired to zero

X1 – return address register for a call

X2 – stack pointer

X5 – alternate link register

The optional compressed 16-bit instruction format is designed around the assumption that

x1 is the return address register and x2 is the stack pointer. Software using other conventions

will operate correctly but may have greater code size.

Instruction Address Misaligned Exception – in JAL and JALR case

Instruction Address Misaligned Exception – in conditional branch case – 16 bit instrn support