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Good evening, professors and classmates, this is our project.

First is the minimum requirement implementation. This is the conceptual diagram of our
work.
The main components which are shown in the picture are the Array multiplier, right
shifter and the One adder.
These three components executed sequentially and offering the calculation result of
equation mentioned in the minimum requirement.
Aside from the clk and reset signal, the load is another control signal which will allow the
data transferred from the d to q when load is equal to 1.
When the equal is zero the output can be zero, or last round output. In our design we
used the formal one.

For the multiplier, the reason why we use array multiplier is that it has High Throughput
with low latency. The structure of the array multiplier is quite simple and highly efficient.
Using the n * multiple m-1 full adders can construct the component directly. The code
and conceptual diagram of full adder we designed is shown in the picture above, along
with the
Sample structure of array multiplier. One thing to mentioned is that the half adders in the
figure are replaced by full adder with 0 C input.

For the minimum requirement, divided by four operation can be implemented by simply
right shift 2 digit. The code of right shift is shown above.
As to the add one logic, although we can choose to add a unsigned signal and direct
using adding calculation, we still think it is better to designed the structure, so as to map
the
the vhdl code directly to the circuit. So you will see that code of all the component is our
project never use signed, unsigned type signal and variable and only use integer as the
input to define the
Bit wides of generic component at the design phase.

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 The structure of one adder is simply consist of FA and since one of the add number is 1
the FA design can be simplified into two gates as above.

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The structure of the additional requirement is almost the same as the minimum
requirement, just with some more inputs.
The main differences are these three components are changed largely. The multiplier is
changed to booth multiplier. The right shift support C digit input, and the vector add
allow all Arbitrary value input.
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According to the requirement ,the right shifter need to support n digit for negative and
positive input.
The logic is simple. We designed a right shift loop with one variables x, this variable will
record the times of right shift operation. When the x equal to the C input the right shift
will; stop.
As to the negative and positive input problem. We designed a function called add one.
And if the input value is a negative value, we will inverse the value and using the
function to plus one so as to get the
Primary code of the input. After the shifting, we will conduct the same operation again to
get the complementary codes.

The vector adder almost shares the same structure with the one adder which mentioned
in the minimum requirement.
But this time, one of the add number is not one anymore, which further means that the
Full adder designed can not be simplified in this circumstance.
The structure and code is shown in the picture above.

About the serial input, to reduce the number of input and switch to serial type. We use
the right shifter as the storage register.
For each input which designed a n digits right shifter and the size of shifter is just equal
to the size of the original input.
Then we define 4 input signal with std_logic type to control the input A,B,C,D.
For example, if the signal_a is zero, whenever the new input comes, the right shifter will

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 operate and register state value will be correspondingly shift right one digit with the new
input as the final digit. If the signal_a is one, shift will not execute and then the register
will be frozen and the state value of the register will be kept to prepare for the main logic
calculation.

The code is shown above and we can see that input is the std_logic type.

This is the result of the serial input modification.

For the speed improvement, since we only use the basic type for calculation, we think
we should concentrate on the algorithm to enhance the efficiency.
Therefore, we improve the logic of bit mover component. The original design is to
initiate a variable to record the number of shifting, which is time waste to some extend.
The first reason is that it will introduce a new variable, and the second is that everytime
the variable execute add one operation, there will be a corresponding latency.
Although it just work, but not ideal.
We changed the structure to for loop without introducing any variables and any adding
or comparing operation. The logic is simple, By iteration through all the digit of input C,
If the number x digit of C is 1 then right shit 2 to power of x times can solved the
problem.
As to the fpga, we plan to map the multiplier directly, and the result will shown in the
report.

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