Microelectronics Journal 34 (2003) 767–771

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Solid phase crystallization of amorphous silicon on glass by thin film

heater for thin film transistor (TFT) application
Byoung Dong Kim, Hunjoon Jung*, Gi-Bum Kim, Seung-Ki Joo
School of Materials Science and Engineering, Seoul National University, Gwanwak, Shinrimdond, Seoul 151-744, South Korea
Received 7 February 2003; revised 12 May 2003; accepted 13 May 2003

Abstract
A new process for solid phase crystallization (SPC) of amorphous silicon (a-Si) using thin film heater is reported. With this localized Ti
silicide thin film heater, we successfully crystallized 500 Å-thick a-Si in a few minutes without any thermal deformation of glass substrate.
The size of crystallized silicon grain was abnormally big (30 – 40 mm). Polycrystalline thin film transistors (TFT) fabricated using this unique
thin film heater showed better mobility than those of conventional ones by furnace annealing.
q 2003 Elsevier Science Ltd. All rights reserved.
PACS: 81.05Gc
Keywords: A. Amorphous silicon; B. Solid phase crystallization; B. Thin film heater

1. Introduction In this work, we investigated a unique process for high

temperature SPC of a-Si without any damage on
Recently, according to the rapid progress in flat-panel- the substrate glass using TiSi2 thin film heater, which has
display industry, there has been a growing interest in the very low thermal budget and enables selective area
polycrystalline silicon (poly-Si) process. Compared to a-Si, crystallization.
poly-Si offers significantly higher carrier mobility, so it has
many advantages for device integration, high response rate
TFT’s. Due to the thermal deformation of glass substrate, 2. Experimental
conventional high temperature processing (. 900 8C) could
be used in case of quartz substrate only. Hence, low
In this work, 4 inch in glass wafer (Corning 1737) was
temperature poly-Si processing (LTPS) such as excimer
used as a substrate. 2000 Å-thick a-Si films were deposited
laser annealing (ELA) [1], metal induced crystallization
by low pressure chemical vapor deposition (LPCVD) using
(MIC) [2], and rapid thermal annealing (RTA) [3], Metal
Si2H6 as source gas. The temperature of substrate was
Induced Lateral Crystallization (MLC) [4] lately attracted
450 8C during deposition. Then, 1000 Å-thick Ti film was
considerable attention, and they have been investigated
deposited over a-Si with RF magnetron sputter system. The
intensively. ELA has problems in uniformity and cost. MIC
base pressure was 8 £ 1027 Torr and Ar gas flow rate,
could be done at as low temperature as 450 8C but, metal
working pressure, and RF power were kept 3 sccm,
contamination resident in the films are the sources of
3 mTorr, 50 W, respectively. The sheet resistances of
leakage. RTA and MILC methods are not successful so far
these films were around 15 V per square. For the
in terms of glass compaction, bending and device
fabrications of the thin film heaters, Ti and Si films were
performances)
patterned successively by photolithography. The Ti film was
* Corresponding author. Tel.: þ82-112-880-7442; fax: þ 82-112-887- etched with mixed solution of H2O, HF, HNO3 in 100:3:6
8791. volume ratio. Amorphous silicon was etched by reactive ion
E-mail address: hunjoon1@snu.ac.kr (H. Jung). etch (RIE) using SF6 (50 sccm) and O2 (5sccm) mixed
0026-2692/03/$ - see front matter q 2003 Elsevier Science Ltd. All rights reserved.
doi:10.1016/S0026-2692(03)00151-4
768 B. D. Kim et al. / Microelectronics Journal 34 (2003) 767–771
gases. The RF power and working pressure was 70 W,
50 mtorr, respectively and the etch rate was 25 Å/sec.
Silicide formation was carried out for the thermal
stability of heater by the resistive heating of Ti films for
1 hr, with a constant applied voltage of 200 V. As a result,
there were no changes in resistance any more. The unreacted
Ti films were removed by mixed solution of NH4OH, H2O2
in 50:50 volume ratio.
After silicide formation, a 3000 Å-thick SiO2 film was
deposited by plasma enhance chemical vapor deposition
(PECVD) to prevent reactions between heater and a-Si
using SiH4 and N2O as precursors. Then, 500 Å-thick a-
Si was deposited by LPCVD. A-Si and capping oxide
films above the contact pads of the heaters were etched
successively by photolithography for the appliance of DC
bias to heat the thin film heaters. (Fig. 1).
As shown in the schematic diagram of solid phase
crystallization (SPC) of amorphous silicon by thin film
heater in Fig. 1, the heater has line-shaped features. The
heaters have various line-widths, such as 200, 300, and
400 mm, while the contact-pad to pad lengths were fixed
as 15 mm. There were two 2 £ 2 mm2 size contact pad at
each end of the heater. The heaters were heated
resistively by applying DC bias to the contact pad
using precision probes. We used Agilent 6010A DC
power supply to heat the thin film heaters.
The experiments for SPC of a-Si were made at various
bias voltages, such as 150, 175, and 200 V. After crystal-
lization of a-Si films by thin film heater annealing, the
crystallization was confirmed with the well-known methods
of Secco etching. We used 10:1 diluted Secco etchant with
H2O. It took about 1 min to each unreacted 500 Å-thick a-Si
films completely. The kinetics of the crystallized grains
Fig. 1. Schematic diagram of solid phase crystallization of amorphous
silicon by thin film heater.
Fig. 2. Polycrystalline silicon grain boundary image after Secco etch. The
line-width of the thin film heater used for this sample was 300 mm, bias
voltage was 200 V, and annealing time was 30 s.
were investigated using optical microscope, and SEM.
(Fig. 2– 4).
To investigate the electrical properties of crystallized
poly-Si by thin film heater, TFT were made. After
crystallization, 1000 Å-thick SiO2 film was deposited by
PECVD as gate oxide, and 3000 Å-thick Mo film was
deposited by sputtering as gate metal. Gate metal and gate
oxide was patterned using photolithography to have various
channel widths and lengths from 5 to 1000 um. Source and
drain regions were doped by ion mass doping using B2H6
and PH3 for p-type and n-type transistor, respectively.
3. Results and discussions
The applied powers were calculated by the measurement
of current at constant voltages. The line-widths of the thin
film heaters used in this work were 200, 300, and 400 mm,
respectively, and the input voltages were 150, 175, and
200 V.
The power consumptions can be described as
V2 wt
P¼ ¼ V2 ;
R rl
where P is consumed power, V is applied voltage, R is
the resistance of the thin film heater, W is the width of the
heater, t is thickness of the heater and l is length of the
rectangular heater and r is resistivity of the heater. And
the power consumption per unit area is.
P t
¼ V2 2 :
A rl
According to this equation, if the applied voltages are the
same, the power consumption per unit area will be the same,
regardless of the different line width, because all the factors
except for the line width are the same. So we could control
 B. D. Kim et al. / Microelectronics Journal 34 (2003) 767–771
Fig. 3. The time sequential images of growing polycrystalline silicon grains by thin film heater. Heating time was (a) 20 s, (b) 40 s (c) 60 s, and (d) 80 s. The
line-width of thin film heater was 300 mm, and bias voltage was 175 V.
the temperature of thin film heater by the management of the
applied voltages.
SEM image of the Secco etched poly-Si films annealed for
90 s by the thin film heater having 300 mm line-width at the
biasing voltage of 200 V is shown in Fig. 2. By this result we
can confirm the SPC of a-Si using thin film heater. The largest
grain sizes were around 20 –30 mm, so, the grain growth rates
were about 0.2 –0.33 mm/s. In this study, though the accurate
temperatures of the Si films were not measured, we could
infer from the comparison of our grain-growth rates to
conventional thermal epitaxial crystallization rate reported
in ref. [5]. that the temperature would be 800 –850 8C. No
bending or shrinkage was found in the glass substrate with
this temperature owing to the short and local heating nature.
The thermal budget was minimal because the temperature
rising time and falling time was very short. It is proved that
heating by thin film heater induces no damage to the glass
substrate while effectively crystallizes the amorphous thin
film just above the heater locally.
To investigate the grain growth of the poly-Si, we
observed the transformations of Si films at every 20 s while
heating the 300 mm heater with 175 V. We showed the
results in Fig. 3. These figures have very important
meanings in the mechanisms of SPC. In Fig. 3(a), it can
be seen that there were crystallized regions of about
5 –10 mm size within 20 s annealing. While the sizes of
grains were very large, the density of them was very low.
After additional annealing for 20 s, as shown in Fig. 3(b), it
was clear that the main process was grain growth rather than
nucleation at new site. The grain sizes in Fig. 3(b) were
almost two times larger than those in Fig. 3(a). Generally,
the SPC mechanism of a-Si consists of nucleation and grain
growth. Many micro-twins and grain mismatches exist as
growth continues. So, due to the grain boundaries in the film,
769
the channel mobility decreases in TFT’s Therefore, it is
desirable to crystallize fast with low density of nucleation.
In Crystallization by SPC, the rate of nucleation
formation and crystal growth will depend on the tempera-
ture. Iverson and co-workers [6] showed the activation
energy of nucleation and crystal growth is 5 eV and 3.3 eV,
respectively. Masaki et al. [7] reported similar values with
different preparation method of a-Si films. It means if we
can control the temperature of a-Si precisely, we can induce
crystallization of a-Si while suppressing the nucleation.
It seems that the low nucleation density compared with
the fast grain growth was due to the temperature difference
between at the top and the bottom of the Si film And, the
temperature at the center of the bottom looks higher because
the number of nucleation is constrained at the center as
shown in Fig. 3 (a). Because the nucleation was restricted at
the hot center bottom of the Si film, the density of nuclei
would be very low as a whole.
Fig. 4(b) shows, after annealing for 5 min, SPC was
completed at the upper side of the thin film heater, but at
the lateral side, there is no crystallization of a-Si.
Moreover, after additional annealing for 30 min, there
was no remarkable distinction between Fig. 4(b) and
Fig. 4(c). That is to say, the area in which temperature of
a-Si was hot enough to crystallize a-Si was restricted
only above the heater. This means that most of the heat
from the heater flows upper side rather than lateral side.
According to these results, we suggest the possibilities of
heating specific area by the modification of the
morphology of the heater.
Polycrystalline silicon TFTs were fabricated on the
crystallized region of silicon film by line heater and
transistor performances were characterized as shown in
Fig. 5. (a), and compared with the transistor made
770 B. D. Kim et al. / Microelectronics Journal 34 (2003) 767–771

Fig. 5. I-V characteristics of thin film transistor made by (a) thin film heater,
and (b) furnace annealing at 600C, 20 h: transistor width ¼ 10 mm, and
length ¼ 10 mm, measured for drain voltage 0.1 V, 5.1 V, 10.1 V, 15.1 V
from bottom to top.

Fig. 4. The images of Si films (a) before annealing, (b) after annealing for
5 min, and (c) after annealing for 30 min, at the bias voltage of 200 V. The
line-width of the heater was 200 mm. The current flows from the bottom to
upper directions as shown in (a).

by conventional furnace annealing Fig. 5 (b). Except

crystallization method, all the other processes were done
in the same batch. Mobility of the TFT made by line heater
was measured to be 27.1 cm2/v while mobility of TFT
fabricated by conventional SPC method was 0.9 cm2/v. The
large value of mobility of the TFT by line heater may be the
attributes of abnormally large grain and low defect density.
To prove the grain size effect on the mobility, TFTs of
various line widths were measured and compared in Fig. 6. Fig. 6. Mobility variation of P-type thin film transistors made by thin film
As the width narrows, the mobility increases. This is never heater for channel width 200, 100, 50, 20, 10, 5 mm.
 B. D. Kim et al. / Microelectronics Journal 34 (2003) 767–771
the case in conventional TFTs. Thus, large crystallized
grains by patterned line heater are the main cause for the
high mobility.
4. Conclusions
The unique processing for crystallization of a-Si using
thin film heater was suggested. 500 Å-thick a-Si films were
solid phase crystallized within a few minutes and there were
no thermal damages on the glass substrate at all.
The crystallized region is confined to the right above area
of the thin film heaters. TFTs fabricated on polycrystalline
silicon region by line heater showed higher mobility value
than that of transistor made by conventional furnace annealed
crystallization method. The value of mobility of TFTs
771
fabricated by thin film heater method increase as the width of
channel of transistor decreases.
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