Scribd Logo
Upload

Welcome to Scribd!

  • Ddcolab4 Pes1ug22cs140 Bhavana Baday C

    Uploaded by

    bhavanabaday
    8 views8 pages
    This document is a lab report submitted by a student named Bhavana Baday. It summarizes writing a Verilog program to model an ALU circuit, generating a VVP output and simulation waveform using GTKWave, and verifying the output and waveform with a truth table. The report includes screenshots of the Verilog code, test bench, GTKWave simulation, and a disclaimer signed by the student.

    Original Description:

    Original Title

    DDCOLAB4_PES1UG22CS140_BHAVANA_BADAY_C

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    This document is a lab report submitted by a student named Bhavana Baday. It summarizes writing a Verilog program to model an ALU circuit, generating a VVP output and simulation waveform using GTKWave, and verifying the output and waveform with a truth table. The report includes screenshots of the Verilog code, test bench, GTKWave simulation, and a disclaimer signed by the student.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    8 views8 pages

    Ddcolab4 Pes1ug22cs140 Bhavana Baday C

    Uploaded by

    bhavanabaday
    This document is a lab report submitted by a student named Bhavana Baday. It summarizes writing a Verilog program to model an ALU circuit, generating a VVP output and simulation waveform using GTKWave, and verifying the output and waveform with a truth table. The report includes screenshots of the Verilog code, test bench, GTKWave simulation, and a disclaimer signed by the student.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 8

    Digital Design and Computer Organisation Laboratory

    UE22CS251A
    3rd Semester, Academic Year 2023
    Date: 04-10-2023
    Name: Bhavana Baday SRN: PES1UG22CS140 Section: C

    Week#4 Program Number: 1


    TITLE:
    WRITE A VERILOG PROGRAM TO MODEL THE ALU CIRCUIT.
    GENERATE THE VVP OUTPUT AND SIMULATION WAVEFORM USING
    GTKWAVE. VERIFY THE OUTPUT AND WAVEFORM WITH THE TRUTH
    TABLE.
    I. Verilog Code Screenshot
    Source File
    TEST BENCH
    LIBRARY
    II. GTKWAVE Screenshot
    Disclaimer:
    • The programs and output submitted is duly written,
    verified and executed by me.
    • I have not copied from any of my peers nor from the
    external resource such as internet.
    • If found plagiarized, I will abide with the disciplinary
    action of the University.

    Signature:
    Name: BHAVANA BADAY
    SRN: PES1UG22CS140
    Section: C
    Date: 04-10-2023

    You might also like