DESIGN OF LOW POWER 2.
4GHz CMOS LC OSCILLATORS WITH LOW
PHASE-NOISE AND LARGE TUNING RANGE
Nilakantan Seshan, Jay Rajagopalan * and Kartikeya Mayaram
Department of ECE, Oregon State University, Cowallis, OR 9733 1
*National Semiconductor, Federal Way, WA 98001
ABSTRACT
The design of two 2.4GHz CMOS LC balanced oscillators in a
0.2Spn process for Bluetooth specifications is presented. These
oscillators achieve low phase noise with low power
consumption. At a frequency offset of 3MHz from the 2.4GHz
d e r , the simulated phase noise is - 1 3 2 d B a for both the
oscillatop with a power dissipation of 5-11mW from a 2.5V
power supply. A wide tuning range of 18% is obtained by
means of a PMOS varactor in' conjunction with an array of
switched capacitors.
1. INTRODUCTION
The past decade has seen tremendous g~owth in
wireless communication. The reduction in the c h m e l spacing
and demand for low power, low cost solutions has made the
wireless system design even more challenging [I]. VCOs are
critical to the design of monolithic frequency synthesizers in
wireless handsets. Two important considerations while
designing VCOs are phase noise and tuning range. Outside the
I w p bandwidth of the PLL, the phase noise is determined by
the VCO phase noise. Hence it is imperative to minimize phase
noise of the VCO. In order for the PLL to lock-on to the
reference frequency, a high tuning range is desired. A large
VCO gain (Kvco) makes the oscillator more susceptible to
noise, thereby increasing the phase noise.
In this paper, we present two VCO designs targeted
for Bluetwth specifications. The Bluetooth standard is gaining
acceptance around the world for short and medium range
wireless data communication. Both these oscillators provide
low phase noise with low power consumption and offer a wide
tuning range. Section 2 discusses the various oscillator
topologies. A brief description of the Varactors is given in
Section 3. The VCO design is presented in Section 4, followed
by the simulation results and a comparison with other VCOs in
Section 5. Section 6 highlights some layout techniques crucial
to high frequency oscillator design. Conclusions are presented
in Section 7.
2. VCO TOPOLOGIES
The most popular oscillator topologies comprise of
crosscoupled NMOS or PMOS transistors. The tank in these
0-7803-7448-7/02/$17.00 82002 IEEE IV - 409
oscillators provides considerable attenuation at frequencies
other than the oscillation frequency, thereby giving superior
phase noise performance. A combination of the PMOS and
NMOS cross-coupled pairs gives the complementary oscillator
topology. Fig. I shows the simplified schematics of both the
.
topologies.
VD D
GND GND
(8) (b)
Fig. 1: Oscillator topologies: (a) NMOS oscillator. (b)
Complementaryoscillator.
The simulated phase noise performance of these two
topologies is compared in Fig. 2. It can be observed from Fig. 2
that the complementary topology has better phase noise
performance as compared to the NMOS topology. Although the
complementary topology has more devices than the NMOS
topology, the differential voltage swing is larger for the same
current consumption [2-31 resulting in reduced phase noise. The
two cross-coupled stages in the complementary oscillator
provide the necessary start-up loop gain for smaller values of
current as compared to the NMOS cross-coupled pair. In order
to reduce the up-conversion of the tail current source flicker
noise to phase noise, PMOS transistors are used for biasing as
shown in Fig. 1.
3. VARACTORS
NMOS and PMOS transistors operated in the
accumulation-depletion region exhibit voltage dependent
capacitances [4]. The gate of the transistors is connected to the
oscillator and the control voltage can be applied to either the
bulk terminal or the source-drain terminal. When the control
voltage is applied to the bulk terminal, the gate-bulk
capacitance changes from CO, in the accumulation region to CO,
in series with C d r p b nin the depletion region. Applying the
control voltage to the source-drain terminal causes the
capacitance to change since the device moves from the
depletion mode to the inversion mode of operation, thereby
providing the necessary tuning. The tuning characteristic of the
PMOS varactor for both the cases is shown in Fig. 3.
applied to the bulk as compared to the case when the control is
applied to source-drain terminal. Hence the bulk node was
chosen as the control terminal in the oscillators designed. Since
the bulk terminal needs to be varied,. only a PMOS transistor
can be used for the varactor, as its bulk terminal is available in
an N-well process.
Although the capacitance variation in Fig. 3(a) is
small, high tuning range was achieved by using this varactor in
conjunction with an array of binary weighted capacitors as
described in the next section.

4. VCO DESIGN

The NMOS oscillator and the complementary

oscillator were designed in a 0.25pn process. The NMOS
oscillator core consumed 4.5mA whereas the complementary
one consumed 2.2mA from a 2.5V power supply. The ROSS-
coupled transistors were designed to provide enough loop gain
to start the oscillations. Minimum channel length devices were
used to reduce the parasitic temperature dependent
capacitances. Simulations were performed to observe the effect
of the tail current source noise on phase noise. The tail current
source (M2 in Fig. 1.) was seen to be the most significant
Fig. 2: Comparison of phase noise of NMOS and contributor ofphase noise in the flicker noise region [6].
complementary VCO topologies for identical bias currents Varying the width of the tail current source negligibly
affected the phase noise whereas increasing the length of the
*I
device reduced the flicker noise thereby reducing the phase
I noise. Fig. 4 illustrates the effect of changing the tail source
uo . . . . . . ...............................................
length on phase noise. The tail current source was sized to
...... ..... ................................ reduce the flicker noise upsonversion to phase noise. In order
E,.- to keep the power consumption to a minimum, a 1:IO current
Qc mirror was employed. The inductors were obtained by stacking
3 . .
the metal layers to obtain higher quality factor. The plot of
VIID ..... . : ..... ..:.. . . . inductor quality factor versus frequency is shown in Fig. 5 .
.. ..
No

2% -3,s -1 *., 0 0.D 3 I., 2

Vgb (Volts.)

........................ ......
(a)
......... .............................

.........

................

0.5 3.3 *.,

Lmgth (Mlcron)

Fig. 4 Effect of changing the length of the tail current source on

phase noise.

The varactors used in VCOs should be capable of

(h)
Fig. 3: PMOS varactor tuning characteristics. (a) Contol voltage
applied to bulk. (b) Control voltage applied to source-drain.
It can be seen from Fig. 3 that the tuning
characteristics is smoother for the varactor with the control
providing a high tuning range with low VCO gain (Kvco =
dddVc). A large VCO gain will amplify any noise coupling to
the control node and hence will deteriorate the phase noise
performance. Since the PMOS varactor is capable of providing
a small tuning range, an array of binary weighted switched
capacitors was used [SI. A tuning range of 15-20% was
targeted. The simplified schematic of the varactor circuit is
shown in Fig. 6. The capacitors controlled by the switches

IV - 410
provide the coarse tuning whereas the PMOS varactor provides
the necessq fine tuning. The small tuning range of the PMOS
varactor maintains a small Kvco, whereas the overall tuning
range is large due to the switched capacitors. To ensure
continuous frequency tuning over process, voltage and
temperature variations, the fine tuning range in simulation was
assumed to be 2-3 times the coarse tuning step (i.e. LSB of
coarse tuning).
Fig. 5: Quality factor of the inductors used in the two VCOs.
TO
vco
Fig. 6 Binary weighted switched capacitor array with PMOS
varactor.
The sizing of the switches is also critical. The thermal
noise of the switches when they are ON degrades the phase
noise. Increasing the size of the switch to reduce the ON
resistance increases the capacitance when the switch is OFF.
This causes the tuning characteristics of the oscillator to
change. Hence a .trade-off is necessary to decide the switch
sizes. The oscillator tuning characteristics for the NMOS
oscillator is shown in Fig. 7. Similar characteristics were
obtained for the complementary structure.
. .. .
2.3
-2 -1.5 -1 *.I 0 0.n I ,.a
ConbDl vo1t.p. 0 in the two sides of the oscillator will cause an unbalance in the
Fig. 7: Tuning characteristics ofthe NMOS oscillator.
5. SIMULATION RESULTS
SpectreRF was used for the phase noise simulations.
Table. 1 summarizes the results obtained for both of the
oscillators along with the Bluetooth specifications. It can be
ohserved from the Table. 1 that the wmplementary VCO
achieves almost the same phase noise performance for nearly
Bluetooth Simulations Simulations
Specs NMOS VCO Comp. VCO
Table. 2 compares these two oscillators with some
other oscillators published iwliterature. A commonly accepted
quantity used for comparing various oscillators is the figure of
merit (FOM) that is given below:
FOM = IOloglo(Frequency) - Phasenoise - lOIoglo(Power)
Table. 2: Comparison of various oscillator performances.
(NMOS and Comp: This work, At Tuning range in MHz)
Considering the fact that the oscillators are purely
CMOS, they show better performance than those previously
published in literature when both, FOM and tuning range, are
considered.
6. LAYOUT TECHNIQUES
One important consideration during the layout of the
oscillators is the metal width. The resonating tank causes the
current in the tank to be Q times larger. Hence the metal lines
connecting the tank components need to be sufficiently large to
withstand the large currents [IZ].
Another issue with any differential circuit is the
I synmetty between the two halves of the circuit. Any asymmetry
I
tank causing the center frequency to change. Since the
resistance of the metal lines degrades the quality factor of the
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tank, utmost care has to be taken to see that the metal lines are
not unnecessarily long.
The resistance is further reduced by using the topmost
metal layer due to low resistivity or by stacking the top two
metal layers. Contacting the gates of the cross-coupled pair on
both ends reduces the gate resistance by half, thereby improving
the tank quality factor. The resistors and capacitors can be
surrounded by dummies to improve the matching between them.
All these factors have been taken into account while
laying out the two oscillators. Fig. 8 shows the layouts of the
NMOS and the complementary oscillator. It can be observed
that both the layouts are completely symmetric. The switched
capacitor bank is laid out such that the linear gradients along
the wafer cause minimum mismatch. All transistors are
interdigitated to minimize the gradient errors. These oscillators
are being fabricated in a 0.25pn process.
7. CONCLUSIONS
The design of CMOS LC VCOs for Bluetooth
specifications has been presented. These VCOs are capable of
providing large tuning range with low phase noise and low
power consumption. Two different VCO topologies have been
compared and the complementary structure has better phase
noise performance than the NMOS structure. The
complementary VCO performs better than those published in
literature when both, FOM and tuning range are considered.
8. ACKNOWLEDGEMENTS
The authors would like to thank CDADIC for supporting this
work and National Semiconductor for fabricating the chip. They
also thank Jeff Huard, Kim Wong, Mike Schwartz and Bijoy
Chatterjee for numerous discussions.

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Fig. 8: VCO Iayouts. (a) NMOS topology. (b) Complementary [I21 T. H. Lee, The Design of CMOS Radio-Frequency
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