kanji@nitsikkim.

vlsilab Kanji CSAmp_RL90 schematic 14:51:16 Fri Dec 8 2023

dB20(VF("/Out")/VF("/Vin")):phaseDegUnwrapped(VF("/Out")/VF("/Vin")) Fri Dec 8 14:48:11 2023

Name
7.78
dB20(gain)

(dB)

-0.425
190.0
phaseDeg
Phase (deg)

69.7
0 1 2 3 4 5 6 7 8 9 10 11
10 10 10 10 10 10 10 10 10 10 10 10
freq (Hz)

Transient Response Fri Dec 8 14:48:11 2023

Name Vis
5.87
/Vin
V (mV)

-5.87
-171.8
/Out
V (mV)

-198.4
0.0 5.0 10.0
time (ms)

Printed on Page 1 of 2
by kanji
kanji@nitsikkim.vlsilab Kanji CSAmp_RL90 schematic 14:51:16 Fri Dec 8 2023

AC Response Fri Dec 8 14:48:11 2023

Name Vis
2.39
/Vin
/Out

Mag (V)

0.874
0 1 2 3 4 5 6 7 8 9 10 11
10 10 10 10 10 10 10 10 10 10 10 10
freq (Hz)

DC Response Fri Dec 8 14:48:11 2023

Name Vis
6.0
/Vin

/Out
V (V)

0.0

-6.0
-5.0 0.0 5.0
dc (V)

Printed on Page 2 of 2
by kanji