Data Sheet
May 1998
T7697 3.3 V E1 Seven-Channel Line Interface
Features
■ Seven fully integrated E1 line interfaces
■ On-chip transmit pulse shaping with low-
impedance line drivers for both 75 Ω and 120 Ω
loads
■ Receive equalization for up to 11 dB of cable loss
with –18 dB signal-to-interference immunity
■ Ultralow power consumption
■ For use in systems that are compliant with ITU-T
G.703, G.732, G.735-9, G.775, G.823-4, and I.431
■ Fine-pitch (19.7 mil spacing), surface-mount pack-
age, 100 pins
■ –40 °C to +85 °C operating temperature range
Applications
■ SONET/SDH multiplexers
■ Asynchronous multiplexers (M13)
■ Digital access cross connects (DACS)
■ Channel banks
■ Digital radio base stations, remote wireless mod-
ules
■ PBX interfaces
Description
The T7697 line-interface device, designed for use in
E1/CEPT applications, is an integrated seven-
channel analog line interface that digitizes incoming
negative and positive pulses on the receive side, and
converts the digital data from the system side to
bipolar pulses on the line. The T7697 provides the
interface function with very low power consumption.
The receiver performs the equalization and slicing
functions necessary to convert the analog line signal
to a digital bit stream. Equalization circuitry in the
receiver guarantees high input sensitivity and a high
level of interference immunity.
The transmit pulse generator is implemented with
low-impedance output drivers that provide shaped
waveforms to the transformer, guaranteeing template
conformance. The device will interface to both
twisted-pair and coaxial cable with line impedances
of 75 Ω or 120 Ω.
The line interfaces can work with or without clock.
When the clock is available, the transmit pulse gener-
ator will be used to control the output pulse width.
Otherwise, it will be bypassed and the input data to
the transmitter is required to have accurate timing.
The time delay for declaring analog loss of signal is
generated by a self-timing circuit without any clocks.
No off-chip components are required for full interface
functionality except for power supply bypass and line
coupling networks. This device is intended for appli-
cations that require a high number of interfaces per
board such as in synchronous and asynchronous
multiplexers.
 Data Sheet
T7697 3.3 V E1 Seven-Channel Line Interface May 1998

Description (continued)

Block Diagram

The T7697 block diagram is shown in Figure 1. Only a single line interface is shown here for illustration purposes.
In general, the pin names in this document are referenced as shown below. However, the pins on the seven chan-
nels will have a suffix on their names corresponding to their channel number.
In Figure 1, the pin ALOS denotes analog loss of signal, and NOCLKN is active-low if there is no transmit clock
available to the line interfaces. The pin TCLK/SELN is used for a transmit clock with NOCLKN ¦ 0. Otherwise, when
NOCLKN = 0, TCLK/SELN is used as a select for the transformer turns ratio. The other pins are the inputs and out-
puts of the receiver and the transmitter, respectively.

ALOS ALOS
ALOS
DETECTOR DELAY

RTIP RPD
RECEIVER
SLICER
RRING EQUALIZER RND

PEAK
DETECTOR
NOCLKN

TDM

TTIP PRE- PULSE TPD

LINE
DRIVER DRIVER GENERATOR
TRING TND

TIMING TCLK/SELN

5-4695(F)r.3

Figure 1. Block Diagram (Single Channel)

2 Lucent Technologies Inc.

Data Sheet
May 1998 T7697 3.3 V E1 Seven-Channel Line Interface

Pin Information
The preliminary pinout for the T7697 is shown in Figure 2.

TCLK1/SELN

TCLK7/SELN

TCLK6/SELN
GNDX17
TRING1

TRING7

TRING6
GNDX1

GNDX7

GNDX6

GNDX6
ALOS1

ALOS6
VDDX1

VDDX7

VDDX6
TTIP1

TTIP7

TTIP6
TND1

TND7

TND6
TPD1

TPD7

TPD6
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

RPD1 1 75 RPD6
RND1 2 74 RND6
T T T NOCLKN
VDDD1 3 73

ALOS7 4 72 GNDD1
RPD7 5 71 RTIP6
RND7 6
R R R 70 RRING6
RTIP1 7 69 RTIP7
RRING1 8 68 RRING7
VDDA1 9 67 VDDA67
GNDA1 10 CHANNEL 1 CHANNEL 7 CHANNEL 6 66 GNDA2
VDDA23 11 65 VDDA45
RRING2 12 64 RRING5
CHANNEL 2

CHANNEL 5

RTIP2 13 63 RTIP5
GNDX2 14 62 GNDX5
TTIP2 15 61 TTIP5
VDDX2 16 T R R T 60 VDDX5
TRING2 17 59 TRING5
GNDX23 18 58 GNDX45
TRING3 19 57 TRING4
CHANNEL 3

CHANNEL 4

VDDX3 20 T R R T 56 VDDX4
TTIP3 21 55 TTIP4
GNDX3 22 54 GNDX4
RTIP3 23 53 RTIP4
RRING3 24 52 RRING4
TCLK3/SELN 25 51 TCLK4/SELN

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
TCLK2/SELN

TESTN

TCLK5/SELN
ALOS3

ALOS2

ALOS5

ALOS4
TND3
TPD3

RPD3
RND3
TPD2
TND2

RND2
RPD2

VDDD2

RPD5
RND5

TND5
TPD5
RND4
RPD4

TPD4
TND4
GNDD2

5-4696(F).ar.4

Figure 2. Pin Diagram

Lucent Technologies Inc. 3

 Data Sheet
T7697 3.3 V E1 Seven-Channel Line Interface May 1998

Pin Information (continued)

The pin descriptions for the T7697 are given in Table 1.

Table 1. Pin Descriptions

Pin Symbol* Type† Name/Description

1 RPD1 O Positive Receive RZ Output.
35 RPD2
29 RPD3
47 RPD4
41 RPD5
75 RPD6
5 RPD7
2 RND1 O Negative Receive RZ Output.
34 RND2
30 RND3
46 RND4
42 RND5
74 RND6
6 RND7
3 VDDD1 P Power Supply (3.3 V ± 5%) for Digital Circuitry in Channels 1, 6, and 7.
Power Supply (3.3 V ± 5%) for Digital Circuitry in Channels 2, 3, 4, and
37 VDDD2 P
5.
4 ALOS7 O Analog Loss of Receive Signal.
36 ALOS2
28 ALOS3
48 ALOS4
40 ALOS5
76 ALOS6
100 ALOS1
7 RTIP1 I Positive Bipolar Receive Input.
13 RTIP2
23 RTIP3
53 RTIP4
63 RTIP5
71 RTIP6
69 RTIP7
8 RRING1 I Negative Bipolar Receive Input.
12 RRING2
24 RRING3
52 RRING4
64 RRING5
70 RRING6
68 RRING7
9 VDDA1 P Power Supply (3.3 V ± 5%) for Analog Circuitry in Channel 1.
11 VDDA23 P Power Supply (3.3 V ± 5%) for Analog Circuitry in Channels 2 and 3.
65 VDDA45 P Power Supply (3.3 V ± 5%) for Analog Circuitry in Channels 4 and 5.
67 VDDA67 P Power Supply (3.3 V ± 5%) for Analog Circuitry in Channels 6 and 7.
10 GNDA1 P Ground Reference for Analog Circuitry in Channels 1, 2, and 3.
66 GNDA2 P Ground Reference for Analog Circuitry in Channels 4, 5, 6, and 7.
14 GNDX2 P Ground Reference for Line Drivers in Channel 2.
18 GNDX23 P Ground Reference for Line Drivers in Channels 2 and 3.
22 GNDX3 P Ground Reference for Line Drivers in Channel 3.
54 GNDX4 P Ground Reference for Line Drivers in Channel 4.
58 GNDX45 P Ground Reference for Line Drivers in Channels 4 and 5.
* The number suffix of the symbol indicates channel number.

4 Lucent Technologies Inc.

Data Sheet
May 1998 T7697 3.3 V E1 Seven-Channel Line Interface

† P = power, I = input, and O = output.

Lucent Technologies Inc. 5

 Data Sheet
T7697 3.3 V E1 Seven-Channel Line Interface May 1998

Pin Information (continued)

Table 1. Pin Descriptions (continued)

Pin Symbol* Type† Name/Description

62 GNDX5 P Ground Reference for Line Drivers in Channel 5.
80, 84 GNDX6 P Ground Reference for Line Drivers in Channel 6.
88 GNDX7 P Ground Reference for Line Drivers in Channel 7.
92 GNDX17 P Ground Reference for Line Drivers in Channels 1 and 7.
96 GNDX1 P Ground Reference for Line Drivers in Channel 1.
15 TTIP2 O Positive Bipolar Transmit Output.
95 TTIP1
21 TTIP3
55 TTIP4
61 TTIP5
81 TTIP6
89 TTIP7
16 VDDX2 P Power Supply (3.3 V ± 5%) for Line Drivers.
94 VDDX1
20 VDDX3
56 VDDX4
60 VDDX5
82 VDDX6
90 VDDX7
17 TRING2 O Negative Bipolar Transmit Output.
93 TRING1
19 TRING3
57 TRING4
59 TRING5
83 TRING6
91 TRING7
25 TCLK3/SELN I Transmit Clock (2.048 MHz ± 50 ppm) When System Clock is Available.
97 TCLK1/SELN Transformer Turns Ratio (N) Select for No Clock Mode (NOCLKN = 0):
33 TCLK2/SELN TCLK = 1 for N = 2 and TCLK = 0 for N = 2.42/1.91.
51 TCLK4/SELN
43 TCLK5/SELN
79 TCLK6/SELN
87 TCLK7/SELN
26 TND3 I Negative Transmit Input.
98 TND1
32 TND2
50 TND4
44 TND5
78 TND6
86 TND7
27 TPD3 I Positive Transmit Input.
99 TPD1
31 TPD2
49 TPD4
45 TPD5
77 TPD6
85 TPD7
38 TESTN I Global Input Pin for Test.
39 GNDD2 P Ground Reference for Digital Circuitry in Channels 2, 3, 4, and 5.
72 GNDD1 P Ground Reference for Digital Circuitry in Channels 1, 6, and 7.
73 NOCLKN I Global Input Pin to Indicate No System Clock Available When
NOCLKN = 0.
* The number suffix of the symbol indicates channel number.
† P = power, I = input, and O = output.

6 Lucent Technologies Inc.

Data Sheet
May 1998 T7697 3.3 V E1 Seven-Channel Line Interface

Functional Description

Receiver

Data Recovery

The receive line-interface transmission format of the device is bipolar alternate mark inversion (AMI). The receive
dual-rail (RPD/RND) digital outputs are sliced data in return-to-zero (RZ) format. The receiver operates with high
interference immunity, utilizing an equalizer to restore fast rise/fall times following maximum cable loss. The signal
is then peak-detected and sliced to produce digital representations of the data.

Receiver Alarm

An analog loss of signal (ALOS) detector monitors the incoming signal amplitude. If the input amplitude drops
below a voltage that is approximately 20 dB below the nominal pulse amplitude, the ALOS detector output
becomes active (ALOS = 1). The slicer outputs are clamped to their inactive state when ALOS is active. A typical
hysteresis of 4 dB is provided to eliminate ALOS chatter. The device requires more than 10 bit pulses and less than
255 bit pulses to detect analog loss of signal (compliant with ITU-T G.775). No clock is needed for the ALOS,
detector, or data recovery.
The performance of the receiver is specified in Table 2.

Table 2. Receiver Specifications

Parameter Min Typical Max Unit Spec

Analog Loss of Signal:
Threshold to Assert 23 20 17.5 dB1 —
Threshold to Clear 17.5 16 13.5 dB1 —
Time Delay2 10 — 255 Bit ITU-T G.775
Hysteresis — 4 — dB —
Maximum Sensitivity3 11 13.5 — dB ITU-T G.703
Return Loss4:
51 kHz to 102 kHz 14 — — dB
ITU-T G.703
102 kHz to 2.048 MHz 20 — — dB
2.048 MHz to 3.072 MHz 16 — — dB
1. Below the nominal pulse amplitude of 3.0 V for 120 ¾ and 2.37 V for 75 ¾ applications using Lucent
transformer 2664AK or 2664AJ and components with values in Figure 4 and Table 5.
2. The time interval required to declare the ALOS.
3. Amount of cable loss for which the receiver will operate error free in the presence of a –18 dB interference
signal summing with the intended signal source.
4. Using Lucent transformer 2664AK or 2664AJ and components with values in Figure 4 and Table 5.

Lucent Technologies Inc. 7

 Data Sheet
T7697 3.3 V E1 Seven-Channel Line Interface May 1998

Functional Description (continued)

Transmitter

Output Pulse Generation

The transmitter operates in two modes depending on the availability of a transmit clock (TCLK). If a TCLK is avail-
able with NOCLKN = 1, which is the default state for the pin NOCLKN, the transmitter accepts positive and negative
NRZ data at TPD/TND and converts them to balanced bipolar signals (AMI format) at TTIP/TRING. Otherwise,
without a TCLK (NOCLKN = 0), the transmitter only accepts RZ data with pulse width 244 ns ± 5% for processing,
and the output pulse width is based on the input pulse width. The pulses are driven on the line by low-impedance
output drivers. These pulses conform to the CEPT pulse templates as shown in Figure 3.
If the inputs to the transmitter are NRZ data with a clock, the output pulse shapes are controlled by the on-chip
pulse-width controller (timing) and the pulse generator (see Figure 1). The pulse-width controller produces the nec-
essary timing signals to accurately control the transmit pulse widths, thus eliminating the need for tightly controlled
transmit clock duty cycle that is usually required in discrete implementations. The amplitudes of these pulse shapes
are controlled by the pulse generator. Due to the low power supplies used, two different settings for the output
pulse amplitudes are available for use with different transformer turns ratios. Table 3 shows these settings.

2 69 n s

(2 4 4 + 2 5)

20 %

1 0%

V = 1 00 %
1 94 ns
1 0%
(2 44 – 5 0)
N O M IN A L P U L S E

20 %

50 %

2 44 ns

2 19 ns

(2 44 – 2 5)

1 0% 10%
0 %

1 0% 1 0%

2 0%

4 88 ns

(2 4 4 + 2 4 4)

5-3145(C)r.8

Figure 3. ITU-T G.703 Pulse Template

8 Lucent Technologies Inc.

Data Sheet
May 1998 T7697 3.3 V E1 Seven-Channel Line Interface

Functional Description (continued)

Transmitter (continued)

If a transmit clock is not available, the inputs to the transmitter will be used to control the output pulse width. There-
fore, these inputs must be RZ data with an accurate pulse width (244 ns ± 5%) and the on-chip timing circuit will
not be used. The amplitudes of the output pulses are controlled by the same pulse generator as described on page
7.
The output pulse amplitudes of the transmitter are the same for the both 75 Ω and 120 Ω loads. Two different net-
works are used for the different loads so that the output return loss is adequate and the output pulse amplitudes on
the loads are equal to 2.37 V for 75 Ω and 3.0 V for 120 Ω, respectively. A detailed discussion is given in the Exter-
nal Line Termination Circuitry section of this data sheet.

Table 3. Settings for the Pulse Amplitude Generator

Transformer Turns Ratios N

NOCLKN TCLK/SELN
120 ¾ 75 ¾
1 TCLK 2.42 1.91
0 1 2 2
0 0 2.42 1.91

Transmit Driver Monitor (For NOCLKN = 1 Only)

If a transmit clock is available (NOCLKN = 1), a transmit driver monitor (TDM) is implemented to protect the line
driver. TDM detects two conditions: a nonfunctional link due to faults on the primary of the transmit transformer,
and periods of no data transmission.
If one of the transmitter's line drivers (TTIP or TRING) is shorted to the power supply or ground, or when TTIP and
TRING are shorted together, the internal circuitry protects the device from damage and excessive power supply
current consumption by 3-stating the output drivers. The monitor detects faults on the transformer primary, but
transformer secondary faults may not be detected. The monitor operates by comparing the line pulses with the
transmit inputs. If the TDM has put the driver in a 3-state condition, after 32 transmit clock cycles the transmitter is
powered up in its normal operating mode. The drivers attempt to correctly transmit the next data bit. If the error per-
sists, TDM remains set to eliminate chatter and the transmitter is internally protected for another 32 transmit clock
cycles. This process is repeated until the error is removed and the TDM is deactivated.
The second monitoring function activates during periods of no data transmission if 32 consecutive zeros are
detected. TDM is deactivated immediately on the detection of a single pulse.

Lucent Technologies Inc. 9

 Data Sheet
T7697 3.3 V E1 Seven-Channel Line Interface May 1998

Functional Description (continued)

Transmitter (continued)

The performance of the transmitter is specified in Table 4.

Table 4. Transmitter Specifications

Parameter Min Typ Max Unit Specification

Output Pulse Amplitude on Load:
75 ¾ 2.13 2.37 2.61 V
120 ¾ 2.7 3.0 3.3 V
Output Pulse Width at Line Side of 219 244 269 ns
Transformer1
Output Pulse Width at Device Pins 224 244 264 ns ITU-T G.703
TTIP and TRING1
Positive/Negative Pulse Imbalance:
Pulse Amplitude –4 ±1.5 4 %
Pulse Width2 –4 ±1 4 %
Zero Level (percentage of pulse –5 0 5 %
amplitude)
Return Loss3:
51 kHz to 102 kHz 9 — — dB CH-PTT
102 kHz to 2.048 MHz 15 — — dB
2.048 MHz to 3.072 MHz 11 — — dB
1. For input data with a clock or RZ data with the pulse width 244 ns, using Lucent transformer 2664AK or 2664AJ.
2. For input data with a clock or RZ data with the equal input pulse widths.
3. For the transmit series impedance RT = 7.5 ¾ with load resistor RL = 75 ¾, output load voltage VL = 3 V, and transformer turns
ratio N = 1.91 (Lucent transformer 2664AK); or RT = 6.5 ¾ with load resistor RL = 120 ¾, output load voltage VL = 3 V, and
transformer turns ratio N = 2.42 (Lucent transformer 2664AJ). See Table 5 for details.

10 Lucent Technologies Inc.

Data Sheet
May 1998 T7697 3.3 V E1 Seven-Channel Line Interface

Functional Description (continued)

External Line Termination Circuitry

The transmit and receive RTIP/RRING and TTIP/TRING connections provide a matched interface to the cable (ter-
minating impedance matches the characteristic impedance of the cable). The diagram in Figure 4 shows the
appropriate external components to interface to the cable for a single transmit/receive channel, with Table 5 sum-
marizing the component values based on the specific application. Figure 5 also shows the connection of the appro-
priate external components with a transformer turns ratio of 2, which is indicated in Table 6. Note that, for the
different transformer turns ratio shown in Tables 5 and 6, the TCLK pin must be set as shown in Table 3.

EQUIPMENT
INTERFACE

RECEIVE DATA TRANSFORMER RR

RTIP
CC
Z EQ RP RS
RR
RRING
1:N

DEVICE
(1 CHANNEL)

TRANSMIT DATA RT
TTIP

RL
RT
TRING
N:1

5-3693(C).dr.1

Figure 4. External Line Termination Circuitry

Table 5. Termination Components in Figure 4 per Application*

Symbol Name Cable Type Unit
75 ¾ 120 ¾
Coaxial Twisted
Pair
ZEQ Equivalent Line Termination 75 120 ¾
Tolerance ±4 ±4 %
CC Center Tap Capacitor 0.1 0.1 µF
RP Receive Primary Impedance 200 200 ¾
RR Receive Series Impedance 143 698 ¾
RS Receive Secondary Impedance 147 365 ¾
RL Transmit Load Termination† 75 120 ¾
N Transformer Turns Ratio 1.91 2.42 —
RT Transmit Series Impedance 7.5 6.5 ¾
Output Voltage on Load RL 2.37 3 V
Return Loss at 2.048 MHz‡ 15 15 dB
* Resistor tolerances are ±1%. Transformer turns ratio tolerances are ±2%.
† A ±5% tolerance is allowed for RL.
‡ A ±5% tolerance is allowed for RT. The return loss was measured with Lucent transformers 2664AK for 75 ¾ and 2664AJ for 120 ¾.

Lucent Technologies Inc. 11

 Data Sheet
T7697 3.3 V E1 Seven-Channel Line Interface May 1998

Functional Description (continued)

External Line Termination Circuitry (continued)

EQUIPMENT
INTERFACE

RECEIVE DATA TRANSFORMER RR

RTIP
CC
Z EQ RP RS
RR
RRING
1:N

DEVICE
(1 CHANNEL)

TRANSMIT DATA RT
TTIP

RL
RT
TRING
N:1

5-3693(C).dr.1
Note: Notice the polarity of the transformer.

Figure 5. Second Choice for External Line Termination Circuitry

Table 6. Termination Components in Figure 5 per Application*

Symbol Name Cable Type Unit
75 ¾ 120 ¾
Coaxial Twisted
Pair
ZEQ Equivalent Line Termination 75 120 ¾
Tolerance ±4 ±4 %
RS Receive Secondary Impedance 18.75 30 ¾
RL Transmit Load Termination† 75 120 ¾
N Transformer Turns Ratio 2 2 —
RT Transmit Series Impedance 9.6 9.6 ¾
Output Voltage on Load RL 2.37 3 V
Return Loss at 2.048 MHz‡ 15 13 dB
* Resistor tolerances are ±1%. Transformer turns ratio tolerances are ±2%.
† A ±5% tolerance is allowed for RL.
‡ A ±5% tolerance is allowed for RT.

Power Supply Bypassing

External bypassing is required for all channels. A 1.0 µF capacitor must be connected between VDDX and GNDX of
each channel. Also, a 0.1 µF capacitor must be connected between V DDA and GNDA. Ground plane connections
are required for GNDX and GNDA. The need to reduce high-frequency coupling into the analog supply (VDDA) may
require an inductive bead to be inserted between the power plane and the VDDA pin of every channel.
Capacitors used for power supply bypassing should be placed as close as possible to the device pins for maximum
effectiveness.

12 Lucent Technologies Inc.

Data Sheet
May 1998 T7697 3.3 V E1 Seven-Channel Line Interface

Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.

Table 7. Absolute Maximum Ratings

Parameter Min Max Unit

dc Supply Voltage Range –0.5 6.5 V
Storage Temperature –65 125 °C
Maximum Voltage (digital pins) with Respect to V DDD — 0.5 V
Minimum Voltage (digital pins) with Respect to GNDD –0.5 — V
Maximum Allowable Voltages (RIP[1—7], RIN[1—7]) with — 0.5 V
Respect to VDD
Minimum Allowable Voltages (RIP[1—7], RIN[1—7]) with –0.5 — V
Respect to GND

Recommended Operating Conditions

Table 8. Recommended Operating Conditions

Parameter Symbol Min Max Unit

Ambient Temperature TA –40 85 °C
Power Supply VDD 3.135 3.465 V

Power Dissipation
Device power specification includes power to the line for a specified data ones density.

Table 9. Per-Channel Power Specifications

Parameter Typical1 Unit

Normal Operation2 (50% 1s density) 75 mW
Normal Operation2 (100% 1s density) 120 mW
1. Power dissipation for a typical device at 3.3 V and 25 °C.
2. Per-channel (receive and transmit paths) power.

Lucent Technologies Inc. 13

 Data Sheet
T7697 3.3 V E1 Seven-Channel Line Interface May 1998

Timing Characteristics
The logic interface characteristics are shown in Table 10. All buffers in this device use CMOS levels.

Table 10. Logic Interface Characteristics

Parameter Symbol Test Conditions Min Max Unit

Input Voltage
Low VIL — GNDD 1 V
High VIH — VDD – 1 VDD V
Input Leakage IL — — 1 µA
Output Voltage
Low VOL –5 mA GNDD 0.5 V
High VOH 5 mA VDD – 1 VDD V
Input Capacitance CI — — 3 pF
Load Capacitance CL — — 50 pF

The digital system interface timing is specified in Table 11 and shown in Figure 6. Note that the requirements for
the data (TPD/TND) rise/fall time are for no clock mode only.

Table 11. Interface Clock/Data Timing

Symbol Parameter Min Typ Max Unit

tTCLTCL Average TCLK Clock Period — 488 — ns
tTDC TCLK Duty Cycle 30 — 70 %
tTDVTCL Transmit Data Setup Time 50 — — ns
tTCLTDX Transmit Data Hold Time 40 — — ns
tTCH1TCH2 Clock Rise Time (10% to 90%) — — 40 ns
tTCL2TCL1 Clock Fall Time (90% to 10%) — — 40 ns
tTDH1TDH2 Data Rise Time (10% to 90%) — — 20 ns
tTDL2TDL1 Data Fall Time (90% to 10%) — — 20 ns

tTCLTCL tTCH1TCH2

TCLK

tTDVTCL tTCL2TCL1
tTCLTDX
TPD
OR
TND

A. Clock Mode
tTDH1TDH2

TPD
OR
TND
tTDL2TDL1
B. No Clock Mode
5-4698(F)r.3

Figure 6. Interface Data Timing

14 Lucent Technologies Inc.

Data Sheet
May 1998 T7697 3.3 V E1 Seven-Channel Line Interface

Outline Diagram

100-Pin TQFP

Dimensions are in millimeters.

16.00 ± 0.20
14.00 ± 0.20

PIN #1 IDENTIFIER ZONE

100 76

1 75

14.00
± 0.20

16.00
± 0.20

25 51

26 50

DETAIL A DETAIL B
1.40 ± 0.05

1.60 MAX
SEATING PLANE
0.08
0.05/0.15
0.50 TYP

1.00 REF

0.25 0.106/0.200
GAGE PLANE

SEATING PLANE 0.19/0.27

0.45/0.75 0.08 M

DETAIL A DETAIL B
5-2146(F)r.15

Lucent Technologies Inc. 15

T7697 3.3 V E1 Seven-Channel Line Interface Preliminary Data Sheet
Interactive Terminal Transmission Convergence May 1998

Ordering Information

Device Code Package Temperature Comcode

(Ordering Number)
T - 7697 - - - TL - DB 100-Pin TQFP –40 °C to +85 °C 107688244

DS98-229TIC Replaces DS97-170TIC to

Incorporate the Following Updates
1. Title corrected.
2. Page 11, Figure 4, External Line Termination Cir-
cuitry, replaced transformer.

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Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No
rights under any patent accompany the sale of any such product(s) or information.

Copyright © 1998 Lucent Technologies Inc.

All Rights Reserved
Printed in U.S.A.

May 1998
DS98-229TIC (Replaces DS97-170TIC)
Printed On
Recycled Paper