SECOND GENERATION SWITCHED-CURRENT SIGNAL PROCESSING

John B. Hughes, Ian C. Macbeth, Douglas M. Pattullo

Philips Research Laboratories,

Redhill, England

ABSTRACT

This paper describes a switched-current integrator configuration configuration needs augmenting with additional devices t o
with greatly improved sensitivity to transistor mismatch. Forward diminish the errors due to MOSFET imperfections, such as
Euler, Backward Euler and bilinear-z mappings are described as threshold voltage and gain mismatch, non-zero drain
well as an integrator which responds to the derivative of the input conductance and charge-injection. In this configuration, the
current A universal integrator configuration is developed which current-gain errors of each current store add t o give the loop-gain
performs an identical algorithm to a well known
switched-capacilor univei-sal integrator. It may be uqed to
translate known switched-c:ap;~citor filter topologies into
switched-current counterparts. as demonstrated by the sirnulation
of a 6Ih order low-pass filter

INTRODUCTION

Current domain sampled.-dsl;i techniques are receiving

considerable attention, finding application in both general signal
processing [1.2,3,4] and A-E / D-A conversion [5,6]. Potentially,
1 B : A
current domain operation offers greater ease for algebraic
manipulation of signals, IOWI?~voltage operation and simpler IC
processing than voltage domain operation (i.e.
switched-capacitors) A family of switched-current integralor \I J \I J
cells for building larger systems, eg. filters, was described in ail
i .
if .
.‘i,
earlier paper [ I ] and was developed subsequently [2] into a circuit
configuration for a universal integrator. This performed ail
identical algorithm to a well known switched-capacitor
counterpart. and could be used to map known switched-capacitor
filter structures into equivalent switched-current arrangements
1 1 B : A : 1
121. In this paper, some shoitconiings of that circuit configuration
are discussed and ari improved integrator configuration is (b)
proposed
Fig. 1 First generation switched-current integrator (a) current
FIRST GENERATION SWITCHED-CURRENT INTEGRATOR store ( t i ) integrator

The switched-current integraior pi-oposed in [ I ] is shown iii Fig.1. error. Cascoding helps by virtually eliminating channel
It is based on the current slore shown in Fig. l(a). With swilcli shortening effects and by reducing output conductance. while
S closed it is simply a current tnirror and output current, lo , is nulling schemes, such as Ihe ufie of dummy switches. reduce
mirrored from the input current, I. When switch S opeiis. the charge-injection. However, mismatch between the transistors
oulput current iii T, is sustained by the voltage stored on Cox. forming the current stores inevitably produces random errors in
Fig. l ( b ) is formed by casc:ading oppositely phased 11-channel and the loop-gain and while they can be reduced by enlarging ihe
p-channel current slores to produce a unit delay and then feeding transistor areas, they impose a limit t o the accuracy of the
the delayed output, if , back to the input The integrator s o integrator.
formed has the following response in the z-domain,
The influence of these randoin errors on the integrator’s
frequency response is dependent on the value of B Consider a
biquad made from bilinear-z damped and lossless integrators
which corresponds to a Forward Euler mapping. If E-1, then It can be shown that,
ideally. the loop-gain is unify and the integrator is l o s s l ~ s swith
a gain determined by A . If R < 1 , the loop-gain is less than unity
and the integrator is damped. In practice this simple circuit
0 1990 IEEE
CH2868-8/9o/oooO-zsOS$l.~

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 where wn is the radian cut-off frequency, ,T, is the clock period
and Q is the quality factor. The sensitivity of wo/Q to B is given
by
S"OIQ = ._-&
(1 - B2)
As wnTcK/Q-+ 0 , B + 1 and Sp'Q-+ - W . Clearly, the integrator
shown in Fig. 1 can result in filters which are highly sensitive to
transistor mismatch and is ill-suited t o designs having a clock
frequency which is very much higher than the filter cut-off
frequency, or having a high quality factor.
SECOND GENERATION SWITCHED-CURRENT INTEGRATORS
The proposed integrator, which overcomes the aforementioned
shortcoming of the earlier integrator, is based on the alternative
current store shown in Fig 2(a). When the switch 5 is closed, ihe
io
Fig. 2 Second generation switched-current integrator (a) current
store (b) delay cell (c) delay cell with feedback (cl) iiitegiator
2806
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transistor To is diode-connected and can sink input current.
When the switch is opened, the current in transistor To is
sustained by the voltage stored on CO, , and becomes an output
current. A scaled outpui current may be produced using
transistor T, (having a different aspect ratio). It should be noled
that the output current from To is available only when S opens
while that from T, is available with S open o r closed
Next, consider the delay cell shown in Fig. 2(b). The switches are
operated by a two-phase non-overlapping clock, 0 ,/ 0,, where
rp, precedes &. On phase rp, of sampling period (n-I) the input
signal current, i(n-I), and the bias current. J, , sum at node N and
a current, J, + i(n - 1) , flows into T, which is diode-connected.
On the next phase rp, (of sampling period (n)), the current stored
in T, and the bias currents, J, and J, , flow into T, which is
diode-connected and so the current in T, is given by
+ +
I, = J, J, - (J, i(n - 1)) = J, - i(n - 1). The current at output X
is J, - I, = J, - I, = J, - (J, - i(n - 1)). For unity gain, J, = J, = J,
and so the output current at X is io(n) = i(n - 1) , the input current
from the previous sampling period. On the next phase @, , n
similar current flows at output Y .
In Fig. 2 (c). an integrator is formed by connecting the output Y to
the input summing node, N . By inspection, the parallel
combination of the r$, and Q2 switches may be replaced by n
short circuit t o yield the structure shown in Fig. 2(d) It is readily
shown that the transfer function is given by
Az-'
H(z) = -__ (4)
1 - z-'
which corresponds to a Forward Euler mapping for a Iossless
integrator.
A damped integrator is shown in Fig. 3. It contains an extra
feedback stage (T, and current source) which is weighled n,, and
the output stage is weighted U,. On phase I$, , T, and T, art?
connected in parallel and th.e current they receive is stiarerl
between them. On phase 0, , these currents are stored but only
that current stored in T, is Ted back t o the summing node 111 this
way, the loop-gain is rnade equal to 1/(1 + u p ) and the z-domairi
transfer response is given by
1 : 1 : a4 : a1
Fig. 3 Damped integrator (Forward Eulerl
whwc A, = a l / ( l fa,) anti B = l/(l
t 06).Clearly, this is :vie
same as that given in equation ( I ) , i.e. it is a Forward Euler
damped integrator,
Fig. 4 shows an integrator which differs from that shown in Fig. 3
only in that the input current is sampled on phase @, instead of
phase @, On phase @ I , the input current enters T, (being
diode-connected), and the output current, io , is mirrored
immediately. Analysis of this circuit gives the following z-domain
iransfer characteristic
Fig. 6 is a universal integrator configuration made from the
superposition of Forward and Backward Euler and feed-forward
inputs. The input currents are weighted U , ,uz and a3 ,
accomplished by scaling the weights of the output stages
supplying these currents, and the output stage has unit weight.
By superposition of equations (5),(6) and (7) the z-domain output
current is given by

where A, , A,, A, and B are as defined in equations (5),(6) and (7).

where A, = oJ(1 + a 4 ) ,which corresponds to the Backward Euler

mapping of a damped integrator.

a1
a2
i0
a3 3- I I I
I+
I I ,
i0

1 : i : a 4 : 1

T3
Fig. 6 Universal switched-current integrator

A bilinear-z integrator may be formed by setting

i,(z) = - i2(z)= i(z) , i3(z) = 0 and A, = A, = A. The z-domain
Fig. 4 Damped integralor (Backward Euler) transfer response then becomes,

Fig. 5 shows an integrator in which the input current, i3 , is led

directly to the summing node. On phase rpz,the input current has
value ir(n - 1) and flows in T, , while on phase it has value
i,(n) and flows in TI Of couise, on phase @ I , the stored current
from T, also flows into TI giving an effective input sirlnai in
T, of i,(n) - i,(n - 1) and so the iclamped integrator is effectively
driven by the derivative of the input signal. Analysis gives the
z-domain transfer response
(7)
where A, = aJ(1 + U,,). Note that when B = 1/(1 +(I,)= 1
(lossless), the input signal is merely inverted and scaled. Clearly.
the direct input connection gives the integrator a feed-forward
capability.
DISCUSSION OF INTEGRATOR PERFORMANCE
The new style of integrator cornprises a lossless integralor
feedback loop (transistors T, and T, , Fig.6) with extra feedback
(transistor T, ) to produce damping. This is in contrast with Iiie
first-generation switched-current integrator (Fig. 1) which
combined the feedback paths. It is more akin to ihe
switched-capacitor integrator (Fig.7) which has a IossIc!ss
integrator (op. amp. and capacitor C) to which is added exlra
feedback (switched-capacitor, a&) to produce damping.

Fig. 5 Feed-forward damped integrator Fig. 7 Universal swiiched-capacitor integrator

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 Consider the lossless integrator loop. The current stores. simulation of a 6Ih order low-pass filter built from biquad sections
T, and T, , both sink and source current with single transistors using the new switched-current integrator.
and so random errors due to transistor mismatch do not occur.
However, systematic errors can arise through channel length
modulation and switch charge- injection. Channel length
modulation effects can be virtually eliminated by cascode [1.4] or
servo techniques [3,5] to hold Vdp constant.

Charge-injection effects are reduced in this structure for the

following reasons. When the (p, switch opens, the current stored
in T, has an error of -g,dV, , where dV,, is the voltage
disturbance at the gate of T, due to charge-injection. This
produces an error in the output signal current from T, (sunk by
T, ) of +gm26V,,,. When the (p, switch opens, the current stored on
T, acquires an error of -g,dV, , giving a total error in ihe
loop-gain due to charge-injection of g,dV, - g,,dV,, Under
small signal conditions, gm,=gm2and dV,,,=dV,,, , giving
negligible loop-gain error due to charge-injection. With large
signals, cancellation of these errors is not complete hilt lhe
loop-gain charge injection error is less than that of the earlier
integrator which summed the individual errors.

Reconsidering the biquad discussed previously (using bilinear-z

lossless and damped integrators) but with the new integrator
configuration, it can be shown that

Frequency (MHZ)

and the sensitivity of w,/Q to a4 is given by

Fig. 8 Simulated transfer characteristic of a 6Ih order low-pas>

filter (0.5dB ripple, 5MHz cut-off frequency, 20MHz clock
frequency)
As w,T,,/Q + 0 , ad+ 0 and S:$Q + 1. Clearly, the new
integrator is much less sensitive to random transistor
REFERENCES
mismatches.
[ I ] J.B.Hughes, N.C.Bird, I.C.Macbeth, "Switched-Currents - A
FILTER SYNTHESIS
New Technique for Analogue Sampled-Data Signal Processing".
IEEE International Symposium on Circuits and Systems. 1989.
The universal switched-current integrator performs an algorithm pp.1584-1587
in the current domain which is identical with that performed in the
voltage domain by the well known universal switched-capacitor [2] J B Hughes, 1 C Macbeth, D M Pattullo, "Switched-Curienl
integrator of Fig. 7. It may therefore be used to derive Filters ", IEE Proceedlngs Part G. No 2 April 1990
switched-current filter Structures directly froin known
switched-capacitor filter structures in the manner described in [3] D.Vallencourt, Y.P Tsividis, S.Daubert, "Sampled-Current
[Z]. As an example, a sthorder Ctiebyshev low-pass filter (0 5dR Circuits", IEEE International Symposium on Circuits and Syslerns.
ripple, 5MHz cut-off frequency, 20MHz clock frequency) rnade 1989, pp.1592-1595
from three biquad sections was designed with the new integrator
configuration using the approach and filter topology described in [4] G.Wegmann, E.A.Vittoz. "Veiy Accurate Dynarnic Current
121. The resulting filter was then simulated using an in-house Mirrors ", Electronics Letters, Vo1.25, No.10 ,May 1989. pp.644-64fi
switched-capacitor CAD package The simulated response of this
filter design using ideal components (i.e. no parasitics, etc.) is [5] D G.Nairn. C.A.T.Salama, "Ratio-Independent Currenl-Mode
shown in Fig. 8. This clearly demonstrates that the new Algorithmic Analog-to-Digital Converters", IEEE International
integrators are performing their algorithms correctly Symposium on Circuits and Systems, 1989, pp.250-253

[6] W.Groeneveld, H.Schouwenaars. H.Termeer, "A

CONCLUSIONS
Self-Calibration Technique for High-Resolution D/A Converters".
An improved switched-current integrator has been described. It IEEE International Solid-state Circuits Conference, 1989. pp '22-23
has the advantages over an earlier configuration of simpler circuit
structure, lower sensitivity to transistor mismatch and reduced
switch charge-injection errors. A universal integrator was
developed which performed either lossless or damped integration
with Backward Euler, Forward Euler or bilinear-z mapping.
depending on the input switch arrangement. A direct input
connection causes the integrator to respond to the signal's
derivative, giving it a feed-forward capability. These attributes
make the integrator algorithmically equivalent to a well known
universal switched-capacitor integrator and enable known
switched-capacitor filters to be readily transposed into equivalent
switched-current structures. This was demonstrated by Ihe

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