Bloque 2 Parte2 OGV

Section 2.
3: AMPLIFIERS USING SEVERAL TRANSISTORS
• Cascode amplifiers configurations.
• Techniques to increase the amplifier gain.

Section 2.3: AMPLIFIERS USING SEVERAL TRANSISTORS
Description:
1. This section describes some of the basic topologies commonly
used to implement amplifiers composed by several transistors.
2. Adding transistors allows to obtain equivalent transistors having
better performance (current gain, input/output impedance) as
compared with single separated transistors.
3. Cascode implementation is presented as a way to increase the
output resistance (thus increasing gain in configurations Gm-Rout).
4. The problems arising from the concatenation of cascode stages
will be presented and the active cascode topology will be
introduced as a solution.
The objectives of this section are:
1. Learn to identify common multiple transistor topologies and to estimate gains

and impedances in complex circuits.
2. Identify cascode stages and understand how they work.

Bloque 2.3: AMPLIFICADORES CON TRANSISTORES COMPUESTOS
Básica:
[Sedr91], [Sedr00], [Fons94], [Geig90], [Gray93], [Lake94], [Unbe89],

[Kenn88], [Robe75]: Referencias más generales para ampliar y profundizar
en los contenidos tanto teóricos como prácticos de la asignatura.
Muchos ejemplos y problemas que pueden contribuir a aclarar
conceptos, despertar el interés por la asignatura y estimular el esfuerzo
personal del alumno. Estos libros aportan otra visión complementaria a los
apuntes desarrollados de la asignatura, pero son básicos e importantes
para su comprensión y estudio.
Complementaria:
[Allen87], [Greg86], [Alva89], [Isma94], [Elma94], [Bult91], [Wang90],

[Saku95]: Referencias que ofrecen la posibilidad a los alumnos de
abordar aspectos nuevos, que si bien no se tratan explícitamente en la
asignatura, podrían resultarles útiles en otras materias de la licenciatura
referidas a la rama de electrónica. Libros de consulta para aclarar
cuestiones y profundidad en conceptos.
Introduction
Most of the integrated amplifiers (see figure at the top of the slide) increase their
gain by cascading stages with low complexity (see figures at the bottom of the
slide) that provide either voltage gain, current gain or some improvement related
to impedance.
It is, of course, possible to study these complex amplifiers considering all the
transistors at the same abstraction level. However, the best wat to proceed is to
learn to identify some common structures that, once known, help us to simplify in
a great manner their analysis.
In CMOS technologies, configurations aimed to increase the transistor input
impedance have no sense, since this is a natural property of this kind of devices.
In this section, we will learn to identify some of these common structures to allow
us to understand how complex circuits work by inspection.
Cascode Amplifiers
The word cascode appeared for the first time in the area of vacuum tubes to
refer to cascade connections that connected the anode of one stage to the
cathode of the following one.
John M. Miller. “Dependence of the input impedance

of a three-electrode vacuum tube upon the load in the
plate circuit” Scientific Papers of the Bureau of
Standards, vol. 15, no. 351, 1920
John L. Stewart. Circuit Theory and Design. Wiley,

New York, 1956, text in page 363:
“The cascode amplifier is important because it
has small circuit noise and a reasonably high Lawrence B. Arguimbau and Richard B. Alder.
gain... It consists of two tubes which may be Vacuum-Tube Circuits and Transistors. Wiley, New
either triodes or pentodes, with triodes best for York, 1956, Figure in page 91.
low noise…”
The importance of this configuration is that allows a significant increase of the

output resistance of the amplifiers (also the gain) without introducing large
capacitive loads in the output nodes, thus enabling high frequency operation.
It is especially indicated in applications where it is important to desensitize the

output nodes of current sources from variations at the supply voltage.
MOS Cascode Amplifiers
rinc  
 1 
g mc  g m1  1  
 1  ( g m2  g mb 2  g ds 2 )  ro1 
g mc  g m1
g m 2  g mb 2 g  g mb 2
roc  ro 2  ro1   ro1  m 2  ro1  Avc  ro1
g ds 2 g ds 2
MOS cascode configuration is a composite transistor in Common Source-

Common Gate connection.
The corresponding small signal model is shown in the slide.
It is clear that the input resistance is that of the transistor M1 (practically infinite).
To obtain the equivalent transconductance we need to measure the short-

circuited output current (R = 0).
To evaluate the output resistance, we need to cancel the input (Vi = 0) and the
load resistance (R = ∞) and then measure changes at the output current as a
function of changes at the output voltage.
CS-CG configuration vs CS single transistor
CS-CG
g m 2  g mb 2
rinc   g mc  g m1 roc 
g ds 2
 ro1
Three results can be obtained if we compare the CS-CG and CS configurations:
1.- The input impedance is the same for both topologies.
2.- The transconductance is also almost the same.
3.- The output impedance is A times larger in the CS-CG configuration, being A
the voltage gain of the cascode transistor.
MOS Cascode Amplifier frequency response
Circuit to analyse including parasitic and load capacitances
Notice that the pole is due to the

parallel connection between the
cascode output resistance and
the load, and to the parallel
connection between the output
capacitor and the Cgd of the
cascode transistor.
1
f 3 dB 
 C L  C gd 2 
2 c 

 Lg  g o 
In summary:
Gain is increased at the cost of decreasing the frequency position of the first pole.
It is important to show up that the GB does not change!

Techniques to increase Gain: Active Cascode
As shown before, each cascode stage

increases the output resistance
VBIAS
according to (see fig. (a)): M2
MN
g  g mb 2
roc  m 2  ro1 M1
VBN
g ds 2 MN-1
Vin VBN-1
It seems logic to think that using several M…
a
cascode stages, the increase of the VB…
output resistance (thus, the gain) will M3
be further magnified (see fig (b)). VB2 VB1
M3 M2
VB1 VB1
g  g mb 2 g m 3  g mb 3 M2
r  m2
o
c
  ro1 Vin
M1
g ds 2 g ds 3
M1
Vin
and more, and more (see fig. (c)) …
c
In modern technologies, thus kind of procedure is not feasible because of the

continuous reduction of the supply voltage levels and the resulting reduction of
the output signal range as we increase the number of cascode stages.
It is possible to increase the output impedance of the cascode stage adding a

feedback loop around the cascode transistor. This is commonly know as Active
Cascode configuration.
The Active cascode configuration uses

one amplifier that creates a negative
feedback loop around the cascode
transistor.
If this amplifier is perfectly ideal (infinite

gain), the input voltage VBIAS, is exactly
VBIAS
copied at the drain of transistor M1.
Then, since the drain of M1 keeps a

constant value that does not depend on
the output voltage level, the output
impedance of this system is infinite.
Of course, it is impossible to design an

infinite gain amplifier. What happens
then?
Using the low frequency small signal model

where the amplifiers has:
• finite gain
• infinite input impedance
• Zero output impedance
Notice that:
v gs2  v g 2  vs2   a  vds1  vds1

  ( a  1) vds1
The circuit is exactly the same that a
cascode configuration with only one
difference: gm2 is scaled by a factor (a+1).
Thus:
rinc  
g m 2 (a  1)  g mb 2
roc   ro1  (a  1)  roCasc
g  g m1
c
m g ds 2
Some important comments:
1. The active cascode configuration meets the output resistance and

transconductance characteristics of a simple cascode.
2. The ourput resistance is (a+1) times larger than that of the simple cascode.
3. These improvements are valid only at those frequencies where the amplifiers
keeps its constant gain. This means that this configuration is valid for are smaller
frequency range as compared with a simple cascode.
4. BE careful with the dynamic behaviour of the amplifier: the feedback loop can
provoke unstable output results.
Stage 2.4: DIFFERENTIAL AMPLIFIERS
 Common differential amplifier stages. Large signal characteristic.
 Small signal characteristic: gain, input and output resistances, CMRR.
 Transistor mismatch.
 Frequency response and Slew-Rate.
 High gain differential amplifiers: composite transistors used as load and

folded configurations.
Section 2.4: DIFFERENTIAL AMPLIFIERS
Description:
• Differential pair configuration is one of the stages most used in

analog circuit design.
• In this section we will study different amplifiers topologies

commonly used in CMOS technologies
The objectives of this section are:
• Learn how transistors can be used to build basic analog circuits.
• Define the differential amplifier concept.
• Study and understand the differential amplifier behaviour.

Differential Amplifiers: General concepts
The differential pair or the differential pair configuration is one of the most used blocks at analog
integrated circuit design.
Single output v o  k1 vi1  k2 vi2 vid  vi1  vi2

vi1
v  vid ( vi1  vi2 )
+ Amplifier vo v o  k1 ( id  vicm )  k2 (  vicm ) vicm 
2 2 2
vi2 - (linear network) v
v o  (k1  k2 ) id  (k1  k2 ) vicm
v o  Ad vid  Acm vicm 2
Differential Common mode

gain Gain
In the real world, the output will not

Ideally speaking, any signal only depend on the differential input vid,
that is common to both inputs but also on the common mode signal, vicm.
should not cause any effect
on th eoutput signal.
Differential Amplifiers: General concepts
The differential pair or the differential pair configuration is one of the most used blocks at analog
integrated circuit design.
Single output v o  k1vi1  k2 vi2 vid  vi1  vi2

vi1
v  vid ( vi1  vi2 )
+ Amplifier vo v o  k1( id  vicm )  k2 (  vicm ) vicm 
2 2 2
vi2 - (linear network) v
v o  (k1  k2 ) id  (k1  k2 ) vicm
v o  Ad vid  Acm vicm 2
Differential Common Mode

gain gain
Differential
Differential output v od gain
v od  v o1  v o2 Ad 
vo1 vid
vi1 + Amplifier
( v o1  v o 2 ) v ocm
vi2 - (linear network)
vo2 v ocm  Acm 
Common mode
2 vicm
gain
The definitions in the slide are used to apply the superposition theorem thus
allowing an easy way to analyse different inputs separately while they are
applied simultaneously to the same input nodes.
MOS Differential Amplifier
NMOS differential pair basic configuration: two matched
transistors Q1 and Q2, with common sources and fed by a
constant current I.
vod  vo1  vo2
vod  vD1  vD2  0
Basic Operation: (a)

First case:
(a) Both gate terminals connected to a common vS  vCM  vGS
mode voltage, vCM:
I where vGS is the voltage
• suppose Q1 and Q2 are in SAT. vD1  vD2  VDD  R that corresponds to a
• Q1 and Q2 are matched and I is assumed to 2 D drain current I/2
be an ideal current source with infinite output
resistance. I
vGS  VT 
• Current I is divided by two at each branch: k´n (W / L)
iD1=iD2=I/2.
I is divided equally at both branches independently of the common mode voltage

value (of course, it is assumed that the transistors are in SAT region).
The differential pair does not respond to changes in the common mode voltage:
the drain voltages do not change, also.
The Common Mode Input Range is the range of vCM for which the differential
pair works properly:
Max value will be given by the requirement that both Q1 and Q2 are in SAT
region:
𝑉_𝐷1 𝑉_𝐺1 𝑉_𝑇 → 𝑉_𝐶𝑀𝑚𝑎𝑥 𝑉_𝑇 𝑉_𝐷𝐷 𝐼/2 𝑅_𝐷
Min value will be given by the minimum voltage across the current source I
that implies a correct operation:
𝑉_𝐶𝑀𝑚𝑖𝑛 𝑉_𝑆𝑆 𝑉_𝐶𝑆 𝑉_𝑇 √ 𝐼/ 𝑘_𝑛^´ 𝑊⁄𝐿
Where 𝑉_𝐶𝑆 is the required voltage through the current source.
NMOS differential pair basic configuration: two matched
transistors Q1 and Q2, with common sources and fed by a
constant current I.
vod  vo1  vo2
vod  vD1  vD2
Basic Operation: (b)

Second case:
(b) Aplying a differential input voltage, vid:
• we set Q2 gate to ground. vid  0  vod  vD1  vD2  0
• then apply a signal vid at the gate of Q1.
vid  0  vod  vD1  vD2  0
• Then: vid=vGS1-vGS2.
Notice that the differential pair certainly responds
• If vid>0 => vGS1>vGS2 => iD1>iD2 and vD1>vD2.
to differential mode signals giving a differential
• If vid<0 => vGS1<vGS2 => iD1<iD2 and vD1<vD2. output signal between the drains.
It is useful to know the value of 𝑉_𝑖𝑑 that causes that the whole current, 𝐼,
passes through only one of the transistors.
In the positive direction, this happens when 𝑉_𝐺𝑆1 reaches a value that
corresponds to 𝑖_𝐷1 𝐼 and when 𝑉_𝐺𝑆2 decreases to the value 𝑉_𝑇
(𝑉_𝑆 𝑉_𝑇):
𝑖_𝐷1 𝐼 𝑘^′/2 𝑊⁄𝐿 _1 𝑉_𝐺𝑆1 𝑉_𝑇 ^2→𝑉_𝐺𝑆1 𝑉_𝑇 √ 2𝐼⁄ 𝑘^´ 𝑊⁄𝐿 _1
𝑉_𝑖𝑑𝑚𝑎𝑥 𝑉_𝐺𝑆1 𝑉_𝑆 √ 2𝐼⁄ 𝑘^´ 𝑊⁄𝐿 _1 ⇒ √ 2𝐼⁄ 𝑘^´ 𝑊⁄𝐿 _1
𝑉_𝑖𝑑 √ 2𝐼⁄ 𝑘^´ 𝑊⁄𝐿 _1
In the negative direction this happens when Q1 is in CUT and I flows only through
Q2:
𝑉_𝑖𝑑𝑚𝑖𝑛 √ 2𝐼⁄ 𝑘^´ 𝑊⁄𝐿 _2 ⟹ √ 2𝐼⁄ 𝑘^´ 𝑊⁄𝐿 _2 𝑉_𝑖𝑑 √ 2𝐼⁄ 𝑘^´
𝑊⁄𝐿 _2
vod  vo1  vo2

vod  vD1  vD2
(b) vod  2IRD

I is proportional The differential output
Basic Operation: voltage is proportional to
to the
Second case: differential input the differential input
voltage, vid. signal, vid.
(b) Aplying a differential input voltage, vid:
• we set Q2 gate to ground. To use the pair as a lineal amplifier, we need
• then apply a signal vid at the gate of Q1. to keep the differential input, vid small:
• Then: vid=vGS1-vGS2. • Current at Q1 will increase: I/2+I.
• If vid>0 => vGS1>vGS2 => iD1>iD2 and vD1>vD2. • Current at Q2 will decrease: I/2-I.
• If vid<0 => vGS1<vGS2 => iD1<iD2 and vD1<vD2. • A voltage IRD will appear at one drain node
and - IRD at the other.
I W v (v / 2)2
iD1   k I ( id ) 1  id
2 L 2 W
I / kn ( )
L
I W v (v / 2)2
iD2   k I ( id ) 1  id
2 L 2 W
I / kn ( )
L
At the Operating Point:

vid=0 y vGS1=vGS2=VGS.
I k
Large Signal Operation:  (W / L)(VGS  VT )2
2 2
k v (vid / 2)2
iD1  (W / L)(vGS1  VT )2 I 1
2
Q1 and Q2 in iD1   ( id ) 1 
SAT, 2 VGS V T 2 (VGS V T )2
k differential pair
iD2  (W / L)(vGS2  VT )2 perfectly
2 matched and I 1 v (vid / 2)2
channel length iD2   ( id ) 1 
vGS1  vGS2  vid modulation not 2 VGS V T 2 (VGS V T )2
taken into
iD1  iD2  I account: =0.
The equations for 𝑖_𝐷1 and 𝑖_𝐷2 are a function of the differential input signal,
𝑣_𝑖𝑑 𝑉_𝐺𝑆1 𝑉_𝐺𝑆2.
I k
 (W / L)(VGS  VT )2
2 2
I 1 v (vid / 2)2
iD1   ( id ) 1 
2 VGS V T 2 (VGS V T )2
I 1 v (vid / 2)2
iD2   ( id ) 1 
2 VGS V T 2 (VGS V T )2
We can obtain the normalized graphics for the
currents at the MOS differential pair:
Large Signal Operation:

k
iD1  (W / L)(vGS1  VT )2 Q1 and Q2 in
2 SAT,
k differential pair
iD2  (W / L)(vGS2  VT )2 perfectly
2 matched and
channel length
vGS1  vGS2  vid modulation not
taken into
iD1  iD2  I account: =0.
• If 𝑣_𝑖𝑑 0, both currents are equal to 𝐼⁄2

• If 𝑣_ 𝑖𝑑 0, 𝑖_𝐷1 increases and 𝑖_𝐷2 decreases in the same amount, thus
keeping constant the value 𝑖_𝐷1 𝑖_𝐷2 𝐼.
• The whole current flows through Q1 when 𝑣_𝑖𝑑 reaches the value √2
𝑉_𝐺𝑆 𝑉_𝑇 .
• If 𝑣_ 𝑖𝑑 0, 𝑖_𝐷2 increases and 𝑖_𝐷1 decreases in the same amount, thus
keeping constant the value 𝑖_𝐷1 𝑖_𝐷2 𝐼.
• The whole current flows through Q2 when 𝑣_𝑖𝑑 reaches the value √2
𝑉_𝐺𝑆 𝑉_𝑇 .
For SMALL vid (lineal amplification):
I I v
iD1   ( id )
2 VGS V T 2
I I v
iD2   ( id )
2 VGS V T 2
I v
I  iD1  iD2  ( id )
VGS V T 2
Large Signal Operation:

k
iD1  (W / L)(vGS1  VT )2
2
k
iD2  (W / L)(vGS2  VT )2
2
vGS1  vGS2  vid
iD1  iD2  I
MOS Differential Amplifier: Small Signal Operation
Applying the common mode and the differential mode concepts:
This new circuit presents some symmetry properties
that simplifies the analysis by applying the
superposition theorem to the differential mode and
common mode inputs independently.
Valid for the small signal model, when the amplifier

is biased at its Operating Point.
vG1=VCM-vid/2 vG2=VCM+vid/2
VCM is the common mode DC +vid/2 -vid/2

voltage within the common mode
range of the differential amplifier.
Typically, this voltage will be the
polarization value.
RSS es the Output Resistance of the biasing current

source
Differential Mode: If we also consider the

output resistances of Q1
y Q2
Circuit for the small

signal analysis
+vid/2 0V -vid/2
Equivalent
Circuit
The differential amplifier

is excited by a
differential signal vid that
is applied in a
complementary (push-pull
or balanced) fashion
RSS is the Output Due to the symmetry, Biased at

Resistance of the biasing the voltage at the I/2
current source common source is cero.
The current through 𝑅_𝑆𝑆 will be zero. Therefore it will not play any role regarding
the differential gain.
From the equivalent circuit we can obtain the following equations:

𝑉_𝑜1 𝑔_𝑚 𝑅_𝐷∥ 𝑟_𝑜 𝑣_𝑖𝑑⁄2
𝑉_𝑜2 𝑔_𝑚 𝑅_𝐷∥ 𝑟_𝑜 𝑣_𝑖𝑑⁄2
Then:
𝐴_𝑑 𝑣_𝑜/𝑣_𝑖𝑑 𝑉_𝑜2 𝑉_𝑜1 /𝑣_𝑖𝑑 𝑔_𝑚 𝑅_𝐷∥𝑟_𝑜
That is the differential gain.
Common Mode: By symmetry, both

circuits are equivalents
where both transistors
Q1 and Q2 are biased
with a source current
I/2 having a source
resistance 2RSS.
Biased at
I/2
The Not considering the effect of ro, the voltage gain of

amplifier is both identical circuits is:
excited using v o1 v RD
a common  o2  
vicm vicm 1
mode input  2RSS
signal vicm. gm
Usually RSS>>1/gm so we can approach:
RSS is the Output Resistance v o1 v R

of the biasing current source  o2   D
vicm vicm 2RSS
(a) If the output of the differential pair is taken “single-endedly”:

|𝐴_𝐶𝑀 | 𝑅_𝐷/ 2𝑅_𝑆𝑆 , |𝐴_𝐷 | 1/2 𝑔_𝑚 𝑅_𝐷⇒𝐶𝑀𝑅𝑅 |𝐴_𝐷/𝐴_𝐶𝑀 | 𝑔_𝑚 𝑅_𝑆𝑆
(b) If the output of the differential pair is taken “differentially”:
|𝐴_𝐶𝑀 | 𝑣_𝑜2 𝑣_𝑜1 /𝑣_𝑖𝑐𝑚 0, |𝐴_𝐷 | 𝑣_𝑜2 𝑣_𝑜1 /𝑣_𝑖𝑑 𝑔_𝑚
𝑅_𝐷⇒𝐶𝑀𝑅𝑅 |𝐴_𝐷/𝐴_𝐶𝑀 | ∞
Effect of mismatch
Offset Input voltage at the MOS differential pair:

Imagine the MOS basic differential pair with both
inputs connected to ground:
• If both branches are perfectly matched (Q1 = Q2
and RD1=RD2=RD). Then, the current I is divided
equally between Q1 and Q2 and Vo will be zero.
• however, real circuits are affected by mismatches
that generate a DC output voltage, Vo, even when
both inputs are connected to ground.
• Vo is called offset output voltage.

• The offset input voltage, VOS, is the
quantity VOS=Vo/Ad.
I • if we apply a voltage -VOS at the input
I1  I2 
2 of the differential amplifier, then the
Vo  0 output voltage will be zero.
•We need to take into account that the offset voltage comes from mismatch
between devices. Thus, its polarity is not known a-priori.
•Three factors contribute to the DC offset voltage at the differential pair:
mismatch at the load resistances, mismatch because of W/L and mismatch
related to VT.
Effect of mismatch
Offset Input voltage at the MOS differential pair:
Example: mismatch due to W/L at Q1

and Q2:
W W 1 W
     
L
 1 L 2  L 
W W 1 W
     
 L 2 L 2  L 
Currents are not equally divided
between Q1 and Q2:
I I  (W / L) 
I1    
2 2  2( W / L ) 
I I  (W / L) 
I2    
Calculating: 2 2  2( W / L ) 
 V   ( W / L ) 
VOS   OV  
 2  ( W / L ) 
VOV  I / kn ´( W / L )
Frequency response of the Differential Amplifier
Consider the variation with frequency of the
differential mode gain, the common mode
gain and the CMRR.
Half
Analysis of the MOS differential pair with common
resistive load: mode circuit
This impedance plays a key

role in the calculation of
The important thing is the common mode gain and
the impedance between the CMRR.
node S and ground.
RSS is the output resistance of the
Transistor QS provides the current source QS and CSS is the total
biasing current (it could be capacitance between node S and ground,
part of a current mirror) including capacitances Cdb and Cgd from
QS, as well as Csb1 and Csb2.
We first analyse the
differential gain
gain and the CMRR.
Ad(s)=Vo/Vid.
Half
Vo AM

Vsig s Using Miller´s Theorem
1
H
|Ad| |AM|
AM   gm RL ´
H 1
fH  
2 2CinRsig
Cin  Cgs  Cgd (1  gm RL ´) fH f
Now, we analyse the
common mode gain
gain and the CMRR.
"single-endedly"
Half
Acm(s)=Vocm/Vicm.
Although this circuit has

many transistor parasitic
capacitances Cgs, Cgd and
Cdb we will only consider
CSS/2.
CSS/2 with 2RSS form a real zero in the common mode gain
function at a frequency much smaller than the remaining poles
and zeroes. This zero will be dominant in the frequency
response of the Acm and the CMRR.
Solving the half common mode circuit we get:

𝐴_𝐶𝑀 𝑠 𝑅_𝐷/ 2𝑍_𝑆𝑆 1/2 𝑅_𝐷 1/𝑅_𝑆𝑆 𝑠𝐶_𝑆𝑆
The common mode gain shows a zero on the negative real axis of the s-plane at
a frequency: 𝑤_𝑧 1/ 𝑅_𝑆𝑆 𝐶_𝑆𝑆
This frequency is by far smaller than the other poles and zeroes of the circuit.
gain and the CMRR.
In summary:
• common mode gain increases +6dB/octave
(20dB/decade) starting from a relatively small
frequency value.
• Acm shows high frequency poles.
• fz is important because it is the frequency at
which the CMRR of the differential amplifier
begins to decrease.
Slew-Rate
The Slew Rate is a non-linear dynamic effect of amplifiers. It

represents the inability of the amplifier to follow fast input dVo
signal changes. It is defined as the maximum speed of change
SR 
of the output voltage.
dt max
•It is due to different sources, however, we can state that it is due to the limitation in the
maximum current that the amplifier is able to provide to one of the capacitors that exist in its
structure (either internal or associated to the load).
• It is usually measured in V/s.
Example:
dV I
Vo=VD1-VD2 • If VG1=VDD and VG2=0 => o  
CL dt CL
dV I
• If VG1=0 and VG2=VDD => o 
dt CL
Differential amplifier with active load
MOS differential pair (Q1 y Q2) loaded using a current mirror (Q3 y Q4):
To see how this circuit operates we first take a look

at the quiescent state with both inputs connected to
a DC voltage equal to the common mode equilibrium
value, that is 0V:
Assuming perfect matching, the biasing current is

divided by half between Q1 and Q2.
Q1 drain current (I/2) feeds Q3 which acts as the input of the loading current
mirror. A replica of this current is given by the output transistor of the mirror, Q4.
At the output node both I/2 currents are perfectly balanced. Then, there is zero
current leaving the circuit towards a virtual next stage (or to a load).
Also, if Q4 is perfectly matched with Q3, then its drain voltage will follow that of
Q3, thus resulting in an output voltage equal to 𝑉_𝐷𝐷 𝑉_𝑆𝐺3.
Now, we consider the circuit fed by a differential input

signal vid and we will analyse its small signal operation
(eliminating the biasing and the current source I):
• there exists a virtual ground at the

common source node of Q1 and Q2.
• Q1 will drive a drain current i=gm1vid/2
• Q2 will drive the same current but with
different sign -i.
• Q1 drain current attacks the input of the
mirror Q3-Q4, the mirror operates then
providing that current at the drain of Q4.
• Now, at the output node we have two
currents, each one with value I, that are
summed to provide an output current with
value 2i.
The output resistances, ro, of all
transistors have been ignored.
This factor 2 at the output node comes from the action of the current mirror that
converts the signal to a single-ended format (that is, between output and ground)
without loosing gain.
If a load resistance is connected at this output node, the current 2i will flow
through it generating the output voltage vo.
If no load resistance is added, the output voltage will be given by the output
current 2i and the output resistance of the circuit itself.

To calculate the Differential Gain:

• We need to consider the effect of the output resistances of all the transistors.
• Since the circuit is no longer symmetric, it is not possible to use the technique
based in the half differential circuit as before.
• We will first derive the shortcircuited transconductance 𝐺_𝑀 𝑖_0/𝑣_𝑖𝑑 and
then, the output resistance Ro.
• The differential gain Will be, then, GMRo.
The calculation of the transconductance is left as an exercise. Considering

𝑔_𝑚3 𝑔_𝑚4 and 𝑔_𝑚1 𝑔_𝑚2 𝑔_𝑚, the result should be: 𝐺_𝑀 𝑔_𝑚.

The calculation of the Output Resistance, 𝑅_𝑜 𝑣_𝑥⁄𝑖_𝑥 is also left as an exercise.
Using the circuit in the slide you should obtain 𝑅_𝑜 𝑟_𝑜2∥𝑟_𝑜4, considering that
𝑔_𝑚1 𝑔_𝑚2 𝑔_𝑚 and that 𝑔_𝑚2≫1.
Differential Gain: Ad=vo/vid=GMRo=gm(ro2//ro4)

When ro2=ro4=ro, Ad=(1/2)gmro=Ao/2 where Ao is the intrinsic gain of the MOS transistor.
Common mode Gain and CMRR:

Although the output is "single-ended", the differential amplifier with active load has a very low
common mode gain and, thus, a corresponding, high CMRR.
We can use these figures to calculate

the common mode gain of the differential
amplifier with active load:
vo 1
Acm   
vicm 2gm 3RSS
Ad
CMRR   gm (ro2 // ro 4 ) [2gm 3RSS ]
Acm
CMRR  ( gm ro )( gm RSS )
ro2  ro 4  ro
gm 3  g m
To achieve a high CMRR we can select an implementation of the biasing source

current I with a high output resistance (a Cascode current source or a Wilson
current source already studied)
Composite transistors used as load and folded configurations
CMOS amplifiers provide a gain that is generated by a current, proportional to the

differential input voltaje gm(V+-V-), that flows through the output resistance of a
simple current mirror Rout.
The output resistance of the simple current mirror can be improved (increased) using
more complex structures (Wilson, Cascode, double Cascode, Widlar, etc.). According to
this the gain can also be improved simply by using better mirrors as the load of the
differential pair.
In all the mentioned cases, to improve the output resistance of the circuit means
improving the gain of the amplifier.
Of course, there is a price to pay:
1. Output swing reduction

2. Common Mode Range reduction
3. Maximum frequency of operation reduction
4. New poles appear that make more difficult the analysis and can be the cause
for instability
5. Power consumption increase (due to biasing circuitry for the mirrors)
6. Area increase because of extra circuitry
Composite transistors used as load and folded configurations
In the figure you can see what is known

as a MOS amplifier with telescopic
cascode load. The design of this (and
others) circuit requires:
1. Finding a symbolic expression for

the small signal gain of the circuit. VCP
Vo
the maximum and minimum output VCN
voltage required to ensure that all

V+ V-
the transistors are operating in
SAT region. IBIAS

the maximum and minimum input
SAT region.
Transistores Compuestos como Carga y Configuraciones Plegadas
In the figure you can see what is known as a

MOS amplifier with folded cascode load
(or simply a folded cascode amplifier).
The design of this circuit requires:

the small signal gain of the circuit.
VCP
the maximum and minimum output
Vo
VCN
IBIAS
SAT region.

the maximum and minimum input
SAT region.
One of the main limitations of increasing the number of cascode stages is the
significant reduction of the input and output voltage ranges. This is particularly
critical in modern CMOS technologies due to the continuous reduction in the
biasing voltages. To solve this limitations the so-called folded structures as shown
in the slide, have been developed.

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Section 2.

3: AMPLIFIERS USING SEVERAL TRANSISTORS

• Cascode amplifiers configurations.

• Techniques to increase the amplifier gain.

The objectives of this section are:

1. Learn to identify common multiple transistor topologies and to estimate gains

2. Identify cascode stages and understand how they work.

[Sedr91], [Sedr00], [Fons94], [Geig90], [Gray93], [Lake94], [Unbe89],

[Allen87], [Greg86], [Alva89], [Isma94], [Elma94], [Bult91], [Wang90],

John M. Miller. “Dependence of the input impedance

John L. Stewart. Circuit Theory and Design. Wiley,

The importance of this configuration is that allows a significant increase of the

It is especially indicated in applications where it is important to desensitize the

MOS cascode configuration is a composite transistor in Common Source-

To obtain the equivalent transconductance we need to measure the short-

Three results can be obtained if we compare the CS-CG and CS configurations:

1.- The input impedance is the same for both topologies.

2.- The transconductance is also almost the same.

Circuit to analyse including parasitic and load capacitances

Notice that the pole is due to the

It is important to show up that the GB does not change!

As shown before, each cascode stage

In modern technologies, thus kind of procedure is not feasible because of the

It is possible to increase the output impedance of the cascode stage adding a

The Active cascode configuration uses

If this amplifier is perfectly ideal (infinite

Then, since the drain of M1 keeps a

Of course, it is impossible to design an

Using the low frequency small signal model

v gs2  v g 2  vs2   a  vds1  vds1

Some important comments:

1. The active cascode configuration meets the output resistance and

 Common differential amplifier stages. Large signal characteristic.

 Small signal characteristic: gain, input and output resistances, CMRR.

 Frequency response and Slew-Rate.

 High gain differential amplifiers: composite transistors used as load and

• Differential pair configuration is one of the stages most used in

• In this section we will study different amplifiers topologies

The objectives of this section are:

• Learn how transistors can be used to build basic analog circuits.

• Define the differential amplifier concept.

• Study and understand the differential amplifier behaviour.

Single output v o  k1 vi1  k2 vi2 vid  vi1  vi2

Differential Common mode

In the real world, the output will not

Single output v o  k1vi1  k2 vi2 vid  vi1  vi2

Differential Common Mode

Basic Operation: (a)

I is divided equally at both branches independently of the common mode voltage

Basic Operation: (b)

vod  vo1  vo2

(b) vod  2IRD

• Then: vid=vGS1-vGS2. • Current at Q1 will increase: I/2+I.

At the Operating Point:

Large Signal Operation:

• If 𝑣_𝑖𝑑 0, both currents are equal to 𝐼⁄2

For SMALL vid (lineal amplification):

Large Signal Operation:

Valid for the small signal model, when the amplifier

VCM is the common mode DC +vid/2 -vid/2

RSS es the Output Resistance of the biasing current

Differential Mode: If we also consider the

Circuit for the small