US010866283B2

( 12 ) Schat
United States Patent ( 10 ) Patent No.: US 10,866,283 B2
(45 ) Date of Patent : Dec. 15 , 2020

( 54) TEST SYSTEM WITH EMBEDDED TESTER 5,600,788 A * 2/1997 Lofgren GOIR 31/318536
714/31
( 71 ) Applicant: NXP B.V., Eindhoven (NL ) 5,968,191 A * 10/1999 Thatcher GO1R 31/31723
714/723
5,991,909 A * 11/1999 Rajski GO1R 31/31813
( 72 ) Inventor: Jan -Peter Schat , Hamburg ( DE ) 714/729
6,000,051 A * 12/1999 Nadeau - Dostie
( 73 ) Assignee : NXP B.V., Eindhoven (NL ) GO1R 31/31855
327/144
( * ) Notice : Subject to any disclaimer, the term of this 6,011,387 A * 1/2000 Lee GOIR 31/318536
324 /73.1
patent is extended or adjusted under 35 6,311,300 B1 * 10/2001 Omura GOIR 31/31724
U.S.C. 154 ( b ) by 110 days . 714/724
6,381,717 B1 * 4/2002 Bhattacharya
( 21 ) Appl. No .: 16 /203,855 GOIR 31/318533
712/227
( 22 ) Filed : Nov. 29 , 2018 6,587,979 B1 * 7/2003 Kraus G11C 29/46
714/702
(65 ) Prior Publication Data ( Continued )
US 2020/0174070 A1 Jun . 4 , 2020 OTHER PUBLICATIONS
( 51 ) Int . Ci. Chakraborty, T. , “ A Practical Approach to Comprehensive System
GOIR 31/3185 ( 2006.01 ) Test & Debug Using Boundary Scan Based Test Architecture ” ,
GOIR 31/3167 ( 2006.01 ) International Test Conference, Lecture 3.2 , IEEE 2007 .
GOIR 31/3187 ( 2006.01 ) (Continued )
( 52 ) U.S. CI .
CPC . GOIR 31/318536 ( 2013.01 ) ; GOIR 31/3167 Primary Examiner — Joseph D Torres
( 2013.01 ) ; GOIR 31/3187 ( 2013.01 ) ; GOIR
31/31855 (2013.01 ) ; GOIR 31/318552 ( 57 ) ABSTRACT
(2013.01 ) ; GOIR 31/318555 (2013.01 ) A test system is provided . The test system includes a printed
( 58 ) field of Classification Search circuit board ( PCB ) and a plurality of integrated circuits
CPC GO1R 31/318536 ; GO1R 31/3167 ; GOIR (ICs ) mounted on the PCB . A first IC of the plurality
31/3187 includes a first test circuit having a first test access port
See application file for complete search history. ( TAP ) controller. A second IC of the plurality includes a
second test circuit having a second TAP controller and an
( 56 ) References Cited embedded tester having a test data output coupled to a test
U.S. PATENT DOCUMENTS data input of the first TAP controller by way of a link circuit .
The embedded tester is configured to provide test control
5,428,624 A * 6/1995 Blair GOIR 31/318547 signals to the first TAP controller and the second TAP
324/ 762.02 controller.
5,477,545 A * 12/1995 Huang GOIR 31/318541
324/ 762.02 20 Claims , 3 Drawing Sheets
200 264
78
-258 206 - 259 -260 208 -261 -262 210 -263
202
246 216 250 226 254 236
220 230 240
248 -218 252 -228 256 238

214 LOGIC 224 LOGIC 234 LOGIC

212 222 232
TAP TAP TAP
TDOT
242
270
TDI TDO1_TD12 TDO2_D13 V
TMS ??
1???
TESTER HOTTRST V
204 244 TDO
28
 US 10,866,283 B2
Page 2

( 56 ) References Cited OTHER PUBLICATIONS

U.S. PATENT DOCUMENTS Haberl, O. , “ Self Testable Boards with Standard IEEE 1149.5
6,686,759 B1 * 2/2004 Swamy GOIR 31/318558 Module Test and Maintenance ( MTM ) Bus Interface ” , IEEE 1994 .
324/ 750.15
Hunt, C. , “ Lead- free Solders and PCB Finish Effects on Solder Joint
6,836,866 B2 * 12/2004 Nolles GO1R 31/3187 Reliability ”, 2006 Electronics Systemintegration Technology Con
714/728 ference, IEEE 2006 .
6,901,543 B2 * 5/2005 Dorsey GO1R 31/318522 IEEE Standards Association , “ IEEE Standard for Test Access Port
324 /750.3 and Boundary - Scan Architecture ” , IEEE 1149.1 , pp . 13-23 , May 13 ,
6,981,191 B2 * 12/2005 Dorsey GO1R 31/3187 2013 .
714/733 IEEE Standards Association, “ IEEE Standard for a Mixed -Signal
6,996,760 B2 * 2/2006 Dorsey GOIR 31/318516 Test Bus” , IEEE 1149,4 , pp . 11-16 , Mar. 18 , 2011 .
714/718 IEEE Standards Association , “ IEEE Standard for Boundary -Scan
7,096,398 B1 * 8/2006 Mukherjee GO1R 31/31705 Testing of Advanced Digital Networks ” , IEEE 1149.6 , pp . 11-41 ,
714/733 2015 .
7,409,612 B2 8/2008 Van De Logt et al. IEEE Standards Association , “ IEEE Standard for Reduced - Pin and
7,958,479 B2 6/2011 Chakraborty et al.
2002/0040458 A1 * 4/2002 Dervisoglu .... GOIR 31/318505 Enhanced - Functionality Test Access Port and Boundary - Scan Archi
714/729 tecture ” , IEEE 1149.7 , pp . 36-67 , Feb. 10 , 2010 .
2002/0095633 A1 * 7/2002 Pillkahn GO1R 31/318555 IEEE Standard Association , “ IEEE Standard for Access and Control
714/734 of Instrumentation Embedded within a Semiconductor Device ” ,
2004/0059959 A1 * 3/2004 Ozawa GO1R 31/31724 IEEE 1687 , pp . 19-56 , 2014 .
2008/0052582 Al 2/2008 Jun et al .
714/30 Lee , N. , “ PCB Engineering for Improving Temperature Cycling
2011/0113298 A1 * 5/2011 Van Den Eijnden Reliability of Lead - free Solder Ball Joint” , IEEE 24th International
GO1R 31/31855
Symposium on the Physical and Failure Analysis of Integrated
714/727 Circuits ( IPFA ), pp . 1-6 , 2017 .
2011/0148456 Al 6/2011 Mooyman - Beck et al . Portolan , M. , “ Accessing 1687 Systems Using Arbitrary Protocols ” ,
2011/0179325 A1 7/2011 Gupta et al. International Test Conference, IEEE 2016 .
2012/0290890 A1 * 11/2012 Van Den Eijnden Tian , X. , “ Reliability, Thermal Anaiysis and Optimization Wirabil
GOIR 31/318538 ity Design of Multi- Layer PCB Boards ” , 2002 Proceedings Annual
714/727 Reliability and Maintainability Symposium , EEEE 2002 .
2013/0328583 A1 * 12/2013 Wada GOIR 31/2884
324 /750.3
2015/0123696 A1 5/2015 Bhogela et al .
2018/0172761 Al 6/2018 Van Beers et al . * cited by examiner
U.S. Patent Dec. 15 , 2020 Sheet 1 of 3 US 10,866,283 B2

- 150
ET 142
136 140 LOGIC 132 TDO
.
TDOT
110
138 134
TAP
152
27 24 22 76 27 ??
-148

108
1
126
130 LOGIC 122 TDO2_TD13
124
128 1
.
FIG
TAP

-146

106
116 120 LOGIC 112 TDO1_TD2 144
118 114
TAP
TDI TMS
ITCKII
TRST
tot
102 160

100 TESTER 104

U.S. Patent Dec. 15 , 2020 Sheet 2 of 3 US 10,866,283 B2

263
ET 242
210
236 240 LOGIC 232 TDO
.
TDOT
-238 234
262 254
TAP
256
.. 27 27 22 22 27 ??
264 -261

208
226 230 LOGIC 222 TDO2_TD13
228 224
260 FIG
2
.
TAP
250
252
-259

206
216 220 LOGIC 212 TDO1_TDI2 244
218 214
-258 TAP
246 248
TDI TMS
ITCKII
TRST
tot
202 270

200 TESTER 204

U.S. Patent Dec. 15 , 2020 Sheet 3 of 3 US 10,866,283 B2

TRST TCK TMS TDO ER OR

ER OR REG 312

COMPARE 310

DRIVE DATA 306 EXP CTDATA 308 3

.
FIG

COUNTER 304

CONTROL 302

300
START CLOCK TDOT
 US 10,866,283 B2
1 2
TEST SYSTEM WITH EMBEDDED TESTER An external tester 104 may be connected at a tester
connection port 160 of PCB 102 in a factory test environ
BACKGROUND ment to provide test signals during factory testing . External
tester 104 includes outputs for providing test data in (TDI ) ,
Field 5 test mode select (TMS ) , test clock ( TCK) , and test reset
(TRST ) signals. External tester 104 also includes an input
This disclosure relates generally to test systems , and more for receiving a test data out (TDO ) signal. While in a factory
specifically, to a test system with an embedded tester. test mode , external tester 104 may provide a serial data
stream by way of the TDI output signal to the first IC 106
Related Art 10 of a scan chain formed by the daisy -chained interconnected
ICs 106-110 . In turn , external tester 104 receives a resulting
Today's electronic systems are reaching new levels of data stream from the last IC of the scan chain by way of the
sophistication and complexity. Such systems may include TDO signal and compares received data with expected data .
multiple integrated circuits interconnected on a printed When a mismatch occurs, an error may be detected .
circuit board , for example . Each integrated circuit generally 15 System 100 may include a plurality of ICs mounted on
requires rigorous testing before being assembled onto the PCB 102. In this embodiment, system 100 includes ICs
printed circuit board . Once assembled as a system , inter 106-110 configured in a daisy chain arrangement which
accommodates boundary scan testing by way of serially
connections between the integrated circuits and the printed connected input and output test data signal lines (e.g. , TDI
circuit board are confirmed by way of factory testing . 20 and TDO ) . ICs 106 and 108 may be any type of IC which
However, any latent defects can remain undetected . includes a logic circuit block 112 , 122 , a test access port
BRIEF DESCRIPTION OF THE DRAWINGS
( TAP ) controller 114 , 124 , and a boundary scan circuit block
116 , 126. IC 110 may be any type of IC which includes a
logic circuit block 132 , a TAP controller 134 , a boundary
The present invention is illustrated by way of example 25 scan circuit block 136 , and an embedded tester ( ET ) 142 .
and is not limited by the accompanying figures, in which like Logic circuit blocks 112 , 122 , 132 may include any
references indicate similar elements. Elements in the figures number or type of logic circuits such as a microprocessor,
are illustrated for simplicity and clarity and have not nec- microcontroller, digital signal processor, timer, serial com
essarily been drawn to scale . munication , state machine, volatile and / or non - volatile
FIG . 1 illustrates, in block diagram form , an example 30 memory (e.g. , static random -access memory (SRAM ),
board level test system in accordance with an embodiment. dynamic random - access memory (DRAM ), flash , etc.) con
FIG . 2 illustrates, in block diagram form , another example troller, or any combinations thereof. For example, IC 106
board level test system in accordance with an embodiment. may be characterized as a microprocessor device with logic
FIG . 3 illustrates, in block diagram form , an example circuit 112 including a microprocessor, IC 108 may be
embedded tester in accordance with an embodiment. 35 characterized as memory device with logic circuit 122
including memory control logic , and IC 110 may be char
DETAILED DESCRIPTION acterized as a system -on - chip ( SoC ) device with logic circuit
132 including a controller, memory , and peripherals.
Generally , there is provided , a board level test system for Test signal lines couple test control signals to and from
in -application boundary scan testing . The system includes a 40 each IC of the chain including ICs 106-110 . The TMS , TCK ,
plurality of integrated circuits ( ICs ) mounted on a printed and TRST signal lines include a first connection at corre
circuit board ( PCB ) and configured in a daisy chain arrange- sponding inputs of TAP controllers 114 , 124 , and 134 , and
ment. One IC of the plurality includes an embedded tester a second connection at port 160. The TDI signal line
which sends test commands to other ICs of the chain by includes a first connection at a corresponding input of TAP
driving test control signals when an external tester is not 45 controller 114 of the first IC 106 of the chain , a second
connected to the system . The embedded tester provides a test connection at an output of link circuit 144 , and a third
data stream to a next IC in the chain by way of a link circuit . connection at port 160. The TDO1_TDI2 signal line
When an external tester is connected to the system , outputs includes a first connection at a test data out (TDO1 ) output
of the embedded tester are configured in a high impedance of TAP controller 114 of the first IC 106 of the chain and a
state so that the external tester can drive the test control 50 second connection at a corresponding test data in ( TDI2 )
signals unimpeded. input of TAP controller 124 of the second IC 108 of the
FIG . 1 illustrates, in block diagram form , an example chain . The TDO2_TDI3 signal line includes a first connec
board level test system 100 in accordance with an embodi- tion at a test data out ( TDO2 ) output of TAP controller 124
ment. System 100 includes a printed circuit board (PCB ) of the second IC 108 of the chain and a second connection
102 , a plurality of integrated circuits (ICs ) 106-110 mounted 55 at a corresponding test data in ( TD13 ) input of TAP control
on the PCB 102 , a plurality of test signal lines ( e.g. , TDI , ler 134 of the third IC 110 of the chain . The TDO signal line
TMS , TCK , TRST, TDO ) and a bus 152 interconnecting ICs includes a first connection at an output of the third IC 110 of
106-110 , and a link circuit 144. PCB 102 may be formed as the chain , a second connection at an input of link circuit 144 ,
a multi -layer PCB having a plurality of conductive layers and a third connection at port 160 .
( e.g. , metal ) separated by dielectric material (e.g. , FR - 4 ) . 60 Link circuit 144 is coupled in the path from the TDO
Bus 152 can be any type of bus for communicating and output of IC 110 to the TDI input of IC 106. Link circuit 144
transferring any type of information such as data, address , is configured to allow transfer of the test data output signal
instructions, control signals (e.g. , reset, mode , and clock TDO from the output of IC 110 to the TDI input of TAP
signals ), analog signals, and the like . Bus 152 is formed at controller 114 of IC 106 when the external tester 104 is not
least in part as one or more conductive paths or traces on the 65 connected to the PCB 102. In this embodiment, link circuit
PCB 102. ICs 106-110 are bi - directionally connected to bus 144 includes a resistor having a first terminal coupled at the
152 by way of respective connection lines 146-150 . TDO signal line and a second terminal coupled at the TDI
 US 10,866,283 B2
3 4
signal line . The resistor may be in a range of 1 k ohms to 10k an error indication is generated . The boundary scan test may
ohms. In other embodiments, link circuit 144 may include be performed at power-up and / or reset of system 100. The
other circuit elements (e.g. , a diode or a MOSFET ) config- boundary scan test may also be performed concurrently with
ured to allow transfer the TDO signal to the TDI input when the normal application operation of system 100 by sampling
the external tester 104 is not connected to the PCB 102 . 5 logic values of I /O signals that go through the boundary scan
ET 142 is embedded within IC 110 and configured to circuits 116 , 126 , and 136 and outputting the sampled values
provide test commands by way of test control signals when by way of the TDOx_TDIy chain (where x refers to an IC
the PCB 102 is not connected to the external tester 104. For in the chain and y refers to the next IC in the chain) .
example , when system 100 is in the field (e.g. , in applica- FIG . 2 illustrates, in block diagram form , another example
tion ) and PCB 102 not connected to the external tester 104 , 10 board level test system 200 in accordance with an embodi
the ET 142 serves as the “ in the field ” tester and is ment. System 200 includes a PCB 202 , a plurality of ICs
configured to perform JTAG (IEEE 1149.1 compliant) 206-210 mounted on the PCB 202 , a plurality of test signal
boundary scan testing of ICs 106-110 and the connections lines ( e.g. , TDI , TMS , TCK , TRST, TDO ) and a bus 264
between ICs 106-110 and the bus 152 , for example . In this interconnecting ICs 206-210 , and a link circuit 244. PCB
embodiment, the ET 142 includes an input to receive a test 15 202 may be formed as a multi- layer PCB having a plurality
data out signal TDOT from TAP controller 134 and outputs of conductive layers (e.g. , metal) separated by dielectric
to drive the TMS , TCK , TRST, and TDO signal lines when material (e.g. , FR - 4 ) . Bus 264 can be any type of bus for
the external tester 104 is not connected to PCB 102. A test communicating and transferring any type of information
data out signal TDO is provided to the test data in TDI input such as data , address, instructions, control signals ( e.g. ,
of the first IC 106 of the chain by way of link circuit 144 and 20 reset, mode , and clock signals ), analog signals, and the like .
coupled TDO and TDI labeled signal lines . In this embodiment, bus 264 may be characterized at least in
When the external tester 104 is connected to PCB 102 and part as an analog test bus ( ATB ). Bus 264 is formed at least
performing a boundary scan test , for example, the test data in part as one or more conductive paths or traces on the PCB
out signal TDO from IC 110 is provided to the external tester 202. ICs 206-210 are connected to bus 264 by way of
104. The test data out signal TDOT from the TAP controller 25 respective connection lines 258-263 .
134 is routed to the ET 142 by way of signal line labeled An external tester 204 may be connected at a tester
TDOT, then routed to the TDO signal line in a feedthrough connection port 270 of PCB 202 in a factory test environ
or bypass manner . ET 142 outputs for driving TMS , TCK , ment to provide test signals during factory testing . External
TRST signals are in a high impedance state allowing the tester 204 includes outputs for providing test data in (TDI ) ,
external tester 104 to drive the corresponding signal lines 30 test mode select (TMS ) , test clock ( TCK) , and test reset
unimpeded. (TRST ) signals. External tester 204 also includes an input
TAP controllers 114 , 124 , and 134 are coupled to bound- for receiving a test data out (TDO ) signal. While in a factory
ary scan circuits 116 , and 136 by way of respective test mode , external tester 204 may provide a serial data
command signal lines 118 , 128 , and 138. Logic circuits 112 , stream by way of the TDI output signal to the first IC 206
122 , and 132 are coupled to respective connection lines 35 of a scan chain formed by the daisy -chained interconnected
146-150 by way of respective internal connection lines 120 , ICs 206-210 . In turn , external tester 204 receives a resulting
130 , and 140 and boundary scan circuits 116 , 126 , and 136 . data stream from the last IC of the scan chain by way of the
In a normal application mode of system 100 , boundary scan TDO signal and compares received data with expected data .
circuits 116 , 126 , and 136 are transparent to the normal When a mismatch occurs, an error may be detected .
function and communication of signals between respective 40 System 200 may include any number of ICs mounted on
logic circuits 112 , 122 , and 132 and bus 152. In a boundary PCB 202. In this embodiment, system 200 includes ICs
scan test mode , for example, TAP controllers 114 , 124 , and 206-210 configured in a daisy chain arrangement which
134 are configured to receive respective test data in ( e.g. , accommodates boundary scan testing by way of serially
TDI , TD01_TDI2 , TDO2_TDI3 ) , test mode select ( e.g. , connected input and output test data signal lines (e.g. , TDI
TMS ) , test clock ( e.g. , TCK) , and test reset (e.g. , TRST ) 45 and TDO ) . ICs 206 and 208 may be any type of IC which
signals. In the test mode, the TAP controllers 114 , 124 , and includes a logic circuit block 212 , 222 , a test access port
134 are configured to provide command signals to respective ( TAP ) controller 214 , 224 , a boundary scan circuit block
boundary scan circuits 116 , 126 , and 136 to control digital 216 , 226 , and an analog circuit block 246 , 250. IC 210 may
signals transferred between respective logic circuits 112 , be any type of IC which includes a logic circuit block 232 ,
122 , and 132 and bus 152 . 50 a TAP controller 234 , a boundary scan circuit block 236 , an
Basic functionality of an in the field boundary scan test is analog circuit block 254 , and an embedded tester (ET ) 242 .
described by way of the following example . ET 142 pro- Logic circuit blocks 212 , 222 , 232 may include any
vides test control signals to configure the boundary scan number or type of logic circuits such as a microprocessor,
circuit 116 to control output signals 146 of IC 106 and to microcontroller, digital signal processor, timer, serial com
configure boundary scan circuits 126 and 136 to receive 55 munication, control logic , state machine , volatile and / or
these output signals. The TDO output of ET 142 provides a non - volatile memory controller, or any combinations
stream of test data by way of link circuit 144 to the TDI input thereof. Analog circuit blocks 246 , 250 , and 254 include
of TAP controller 114. In turn , a resulting test data stream analog I /O pins coupled to bus 264 by way of connection
TDO1_TDI2 is shifted from the test data output of TAP lines 258 , 260 , and 262. Analog circuit blocks 246 , 250 , and
controller 114 and received by the test data input of TAP 60 254 include analog boundary test circuits and may include
controller 124. In turn , a resulting data stream TDO2_TDI3 any number or type of analog circuits such as analog - to
is shifted from the test data output of TAP controller 124 and digital converter, digital -to - analog converter, PLL , bias cir
received at the test data input of TAP controller 134. In turn , cuit , voltage and / or current reference circuit, current mirror,
a resulting data stream TDOT is shifted from the test data amplifier, filter, and so on . For example, IC 206 may be
output of TAP controller 134 and received at the correspond- 65 characterized as a processor device with analog circuit block
ing input of ET 142. When the ET 142 detects a mismatch 246 including a voltage reference circuit , IC 208 may be
between the received data stream TDOT and expected data , characterized as memory device with analog circuit block
 US 10,866,283 B2
5 6
250 including a bias circuit, and IC 210 may be character-
ized as a system -on -chip ( SoC ) device with analog circuit
block 254 including an analog -to -digital converter.
Test signal lines couple test control signals to and from
each IC ofthe chain including ICs 206-210 . The TMS , TCK ,
and TRST signal lines include a first connection at corre-
sponding inputs of TAP controllers 214 , 224 , and 234 , and
a second connection at port 270. The TDI signal line
includes a first connection at a corresponding input of TAP
controller 214 of the first IC 206 of the chain , a second
connection at an output of link circuit 244 , and a third
connection at port 270. The TDO1_TDI2 signal line
includes a first connection at a test data out (TDO1 ) output
of TAP controller 214 of the first IC 206 of the chain and a
second connection at a corresponding test data in ( TDI2 )
input of TAP controller 224 of the second IC 208 of the
chain . The TDO2_TD13 signal line includes a first connec-
tion at a test data out ( TDO2 ) output of TAP controller 224
of the second IC 208 of the chain and a second connection
at a corresponding test data in (TDI3 ) input of TAP control-
ler 234 of the third IC 210 of the chain . The TDO signal line
includes a first connection at an output of the third IC 210
of the chain , a second connection at an input of link circuit
244 , and a third connection at port 270 .
Link circuit 244 is coupled in the path from the TDO
output of IC 210 to the TDI input of IC 206. Link circuit 244
is configured to allow transfer of the test data output signal
TDO from the output of IC 210 to the TDI input of TAP
controller 214 of IC 206 when the external tester 204 is not
connected to the PCB 202. In this embodiment, link circuit
244 includes a resistor having a first terminal coupled at the
TDO signal line and a second terminal coupled at the TDI
signal line . The resistor may be in a range of 1 k ohms 10k
ohms, for example. In other embodiments, link circuit 244
may include other circuit elements ( e.g. , a diode or a
MOSFET ) configured to allow transfer the TDO signal to
the TDI input when the external tester 204 is not connected
to the PCB 202 .
ET 242 is embedded within IC 210 and configured to
provide test commands by way of test control signals when 40
the PCB 202 is not connected to the external tester 204. For
example, when system 200 is in the field (e.g. , in applica-
tion ) and PCB 202 is not connected to the external tester
204 , the ET 242 serves as the “ in the field ” tester and is
configured to perform JTAG IEEE 1149.1 compliant bound-
ary scan testing as well as IEEE 1149.4 compliant analog
boundary testing of ICs 206-210 . In this embodiment, the
ET 242 includes an input to receive a test data out signal
TDOT from TAP controller 234 and outputs to drive the
TMS , TCK , TRST, and TDO signal lines when the external
tester 204 is not connected to PCB 202. A test data out signal
TDO is provided to the test data in TDI input of the first IC
206 of the chain by way of link circuit 244 and coupled TDO
and TDI labeled signal lines .
When the external tester 204 is connected to PCB 202 and
performing a boundary scan test , for example, the test data
out signal TDO from IC 210 is provided to the external tester
204. The test data out signal TDOT from the TAP controller
234 is routed to the ET 242 by way of signal line labeled
TDOT, then routed to the TDO signal line in a feedthrough
or bypass manner . ET 242 outputs for driving TMS , TCK ,
TRST signals are in a high impedance state allowing the
external tester 204 to drive the corresponding signal lines
unimpeded.
TAP controllers 214 , 224 , and 234 are coupled to bound-
ary scan circuits 216 , 226 , and 236 by way of respective
command signal lines 218 , 228 , and 238 and analog circuit
blocks 246 , 250 , and 254 by way of respective command
signal lines 248 , 252 , and 256. Logic circuits 212 , 222 , and
232 are coupled to connection lines 259 , 261 , and 263 by
way of respective internal connection lines 220 , 230 , and
5 240 and boundary scan circuits 216 , 226 , and 236. In a
normal application mode of system 200 , analog boundary
test circuits of analog circuit blocks 246 , 250 , and 254 are
transparent to the normal function and communication of
analog signals between respective analog circuits of analog
10 circuit blocks 246 , 250 , and 254 and bus 264. In an analog
boundary test mode , for example, TAP controllers 214 , 224 ,
and 234 are configured to receive respective test data in
(e.g. , TDI , TD01_TDI2 , TDO2_TD13 ) , test mode select
(e.g. , TMS ) , test clock ( e.g. , TCK) , and test reset ( e.g. ,
15 TRST) signals . In the test mode , the TAP controllers 214 ,
224 , and 234 are configured to provide command signals to
respective analog boundary test circuits of analog circuit
blocks 246 , 250 , and 254 to control analog signals trans
ferred between respective analog circuit blocks 246 , 250 ,
20 and 254 and bus 264. For example, a voltage or current value
may be transferred from analog circuit block 246 and routed
to analog circuit block 254 by way of bus 264 and respective
connection lines 258 and 262 .
Basic functionality of an in the field analog boundary test
25 is described by way of the following example. ET 242
provides test control signals to configure the analog bound
ary test circuits of analog circuit block 246 to control output
signal 258 of IC 206 and to configure analog boundary test
circuits of analog circuit blocks 250 and 254 to receive the
30 output signal 258 by way of respective input signal lines 260
and 262. The TDO output of ET 242 provides a stream of
test data by way of link circuit 244 to the TDI input of TAP
controller 214. In turn , a resulting test data stream
TDO1_TDI2 is shifted from the test data output of TAP
35 controller 214 and received by the test data input of TAP
controller 224. In turn , a resulting data stream TDO2_TDI3
is shifted from the test data output of TAP controller 224 and
received at the test data input of TAP controller 234. In turn ,
a resulting data stream TDOT is shifted from the test data
output of TAP controller 234 and received at the correspond
ing input of ET 242. When the ET 242 detects a mismatch
between the received data stream TDOT and expected data ,
an error indication is generated . The boundary test may be
performed at power-up and / or reset of system 200. The
45 boundary test may also be performed concurrently with the
normal application operation of system 200 by sampling
analog values of 1/0 signals that go through the analog
boundary test circuits of analog circuit blocks 246 , 250 , and
254 .
50 FIG . 3 illustrates, in block diagram form , an example
embedded tester (ET ) 300 in accordance with an embodi
ment. ET 300 is a representative embedded tester for ET 144
in system 100 and ET 244 in system 200 as depicted in FIG .
1 and FIG . 2 respectively . ET 300 includes control circuit
55 302 , counter circuit 304 , drive data circuit 306 , expect data
circuit 308 , compare circuit 310 , and error register circuit
312 .
Control circuit 302 includes inputs to receive a start signal
labeled START and a clock signal labeled CLOCK . The
60 START and CLOCK signals may be provided by a host IC
( e.g. , IC 110 , IC 210 ) in which ET 300 is embedded . Control
circuit 302 includes control circuitry (e.g. , state machine,
processor, etc.) configured to provide test reset signal TRST,
test clock signal TCK , and test mode select signal TMS at
65 outputs labeled TRST, TCK , and TMS respectively. Control
circuit 302 also provides control signals to counter 304 and
error register 312 .
 US 10,866,283 B2
7 8
Counter 304 includes an input coupled to receive the second IC mounted on the PCB , the second IC including : a
control signal from control circuit 302. Counter 304 serves second test circuit configured for boundary scan testing ; and
as a time base for shifting data. Counter 304 provides an an embedded tester having a test data output coupled to a test
output signal for the drive data circuit 306 and the expect data input of the first test circuit by way of a link circuit , the
data circuit 308. Drive data circuit 306 includes a memory 5 embedded tester configured to provide test commands by
and / or circuitry for generating a test data stream . The test way of test control signals. The link circuit may be config
data stream includes a pattern of data bits shifted out based ured to allow transfer of an output signal from the test data
on an output signal of counter 304. The shifted test data output to the test data input of the first test circuit when an
stream is provided as test data out signal TDO at the output external PCB tester is not connected to the PCB . The link
labeled TDO and is received at a test data in TDI input ( e.g. , 10 circuit may include a resistor having a first terminal coupled
TAP controller 114 , 214 ) . Expect data circuit 308 includes a at the test data output and a second terminal coupled at the
memory programmed with a predetermined pattern of test data input. The system may further include an intercon
expected data bit values . The expect data bits are shifted out nect bus coupled to the first IC and to the second IC , the
based on an output signal of counter 304 . interconnect bus formed on the PCB . The interconnect bus
Compare circuit 310 includes a first input coupled to 15 may include a first signal line coupled to a first analog pin
receive the shifted expect data stream and a second input of the first IC and to a second analog pin of the second IC .
coupled to receive the test data out stream from the last IC The first signal line may be characterized as an analog test
of the chain ( e.g. , TDOT from TAP controller 134 , 234 ) . bus and wherein a voltage or current value may be routed
Compare circuit 310 includes circuitry for comparing the from the first IC to the second IC by way of the analog test
incoming test data out stream with the expect test data 20 bus . The interconnect bus may further include a second
stream . When the compare circuit 310 detects a mismatch , signal line coupled to a first logic block and a first boundary
an error may be indicated by way of an output signal at an scan logic of the first IC and coupled to a second logic block
output of the compare circuit 310 . and a second boundary scan logic of the second IC . The first
Error register 312 includes a first input coupled to receive IC may be configured to transfer a first logic value to the
the output signal of the compare circuit 310 and a second 25 second IC by way of the second signal line during normal
input coupled to receive a control signal from the control operation.
circuit 302. The error register 312 includes circuitry con- In yet another embodiment, there is provided , a test
figured to store the error indication received from the system including a printed circuit board (PCB ) ; a plurality of
compare circuit 310 and to provide an error flag output integrated circuits (ICs ) mounted on the PCB , a first IC of
signal at an output labeled ERROR . 30 the plurality including : a first test circuit having a first test
In one embodiment, there is provided, a test system access port ( TAP ) controller ;and a second IC of the plurality
including a printed circuit board (PCB ) ; a plurality of including: a second test circuit having a second TAP con
integrated circuits (ICs ) mounted on the PCB , a first IC of ller ; and an embedded tester having a test data output
the plurality including: a first test circuit having a first test coupled to a test data input of the first TAP controller by way
access port ( TAP ) controller, and a second IC of the plurality 35 of a link circuit , the embedded tester configured to provide
including : a second test circuit having a second TAP con- boundary scan test commands by way of test control signals
troller; and an embedded tester having a test data output to the first TAP controller and the second TAP controller.
coupled to a test data input of the first TAP controller by way The link circuit may be configured to allow transfer of an
of a link circuit, the embedded tester configured to provide output signal from the test data output to the test data input
test control signals to the first TAP controller and the second 40 of the first TAP controller when an external PCB tester is not
TAP controller. The link circuit may be configured to allow connected to the PCB . The embedded tester may be further
transfer of an output signal from the test data output to the configured to provide boundary scan test commands com
test data input of the first TAP controller when an external pliant with the IEEE 1149.1 standard .
PCB tester is not connected to the PCB . The link circuit may By now it should be appreciated that there has been
include a resistor having a first terminal coupled at the test 45 provided , a board level test system for in -application bound
data output and a second terminal coupled at the test data ary scan testing . The system includes a plurality of inte
input of the first TAP controller. The system may further grated circuits ( ICs ) mounted on a printed circuit board
include a bus coupled to the first IC and to the second IC , the (PCB ) and configured in a daisy chain arrangement. One IC
bus formed at least in part on the PCB . The bus may include of the plurality includes an embedded tester which sends test
a signal line coupled to a first logic block and a first 50 commands to other ICs of the chain by driving test control
boundary scan logic of the first IC and coupled to a second signals when an external tester is not connected to the
logic block and a second boundary scan logic of the second system . The embedded tester provides a test data stream to
IC . The first boundary scan logic may be coupled to the first a next IC in the chain by way of a link circuit . When an
TAP controller and the second boundary scan logic may be external tester is connected to the system , outputs of the
coupled to the second TAP controller. The first IC may be 55 embedded tester are configured in a high impedance state so
configured to transfer a first logic value to the second IC by that the external tester can drive the test control signals
way of the signal line during normal operation . The first unimpeded.
logic value may be sampled by the first boundary scan logic Because the apparatus implementing the present inven
or the second boundary scan logic in response to a sample tion is , for the most part, composed of electronic compo
command provided by way of the test control signals. The 60 nents and circuits known to those skilled in the art, circuit
sampled first logic value may be transferred to the embedded details will not be explained in any greater extent than that
tester by way of the corresponding first TAP controller or considered necessary as illustrated above , for the under
second TAP controller. standing and appreciation of the underlying concepts of the
In another embodiment, there is provided, a test system present invention and in order not to obfuscate or distract
including a printed circuit board (PCB ) ; a first integrated 65 from the teachings of the present invention .
circuit ( IC ) mounted on the PCB , the first IC including: a Although the invention is described herein with reference
first test circuit configured for boundary scan testing ; and a to specific embodiments, various modifications and changes
 US 10,866,283 B2
9 10
can be made without departing from the scope of the present 8. The system of claim 7 , wherein the sampled first logic
invention as set forth in the claims below. Accordingly, the value is transferred to the embedded tester by way of the
specification and figures are to be regarded in an illustrative corresponding first TAP controller or second TAP controller.
rather than a restrictive sense , and all such modifications are 9. A test system comprising:
intended to be included within the scope of the present 5 a printed circuit board (PCB ) ;
invention . Any benefits, advantages, or solutions to prob a first integrated circuit (IC ) mounted on the PCB , the first
lems that are described herein with regard to specific IC comprising:
embodiments are not intended to be construed as a critical, a first test circuit configured for boundary scan testing ;
and
required , or essential feature or element of any or all the 10 a second IC mounted on the PCB , the second IC com
claims . prising :
Furthermore, the terms “ a ” or “ an , ” as used herein , are a second test circuit configured for boundary scan
defined as one or more than one . Also , the use of introduc testing; and
tory phrases such as " at least one ” and “ one or more ” in the an embedded tester having a test data output coupled to
claims should not be construed to imply that the introduction 15 a test data input of the first test circuit by way of a
of another claim element by the indefinite articles “ a ” or link circuit, the link circuit comprising a resistor
“ an ” limits any particular claim containing such introduced having a first terminal coupled at the test data output
claim element to inventions containing only one such ele and a second terminal coupled at the test data input,
ment, even when the same claim includes the introductory the embedded tester configured to provide test com
phrases “ one or more ” or “ at least one ” and indefinite 20 mands by way of test control signals .
articles such as “ a ” or “ an .” The same holds true for the use 10. The system of claim 9 , wherein the link circuit is
of definite articles. configured to allow transfer of an output signal from the test
Unless stated otherwise, terms such as “ first ” and “ sec data output to the test data input of the first test circuit when
ond ” are used to arbitrarily distinguish between the elements an external PCB tester is not connected to the PCB .
such terms describe . Thus, these terms are not necessarily 25 11. The system of claim 9 , further comprising an inter
intended to indicate temporal or other prioritization of such connect bus coupled to the first IC and to the second IC , the
elements . interconnect bus formed on the PCB .
12. The system of claim 11 , wherein the interconnect bus
What is claimed is : comprises a first signal line coupled to a first analog pin of
1. A test system comprising : 30 the first IC and to a second analog pin of the second IC .
a printed circuit board (PCB ) ; 13. The system of claim 12 , wherein the first signal line
a plurality of integrated circuits (ICs ) mounted on the is characterized as an analog test bus and wherein a voltage
PCB , a first IC of the plurality comprising : or current value is routed from the first IC to the second IC
a first test circuit having a first test access port ( TAP ) by way of the analog test bus .
controller; and 35 14. The system of claim 12 , wherein the interconnect bus
a second IC of the plurality comprising: further comprises a second signal line coupled to a first logic
a second test circuit having a second TAP controller; block and a first boundary scan logic of the first IC and
and coupled to a second logic block and a second boundary scan
an embedded tester having a test data output coupled to logic of the second IC .
a test data input of the first TAP controller by way of 40 15. The system of claim 14 , wherein the first IC is
a link circuit , the link circuit comprising a resistor configured to transfer a first logic value to the second IC by
having a first terminal coupled at the test data output way of the second signal line during normal operation.
and a second terminal coupled at the test data input 16. A test system comprising:
of the first TAP controller, the embedded tester a printed circuit board (PCB ) ;
configured to provide test control signals to the first 45 a plurality of integrated circuits ( ICs ) mounted on the
TAP controller and the second TAP controller. PCB , a first IC of the plurality comprising:
2. The system of claim 1 , wherein the link circuit is a first test circuit having a first test access port ( TAP )
configured to allow transfer of an output signal from the test controller; and
data output to the test data input of the first TAP controller a second IC of the plurality comprising:
when an external PCB tester is not connected to the PCB . 50 a second test circuit having a second TAP controller ;
3. The system of claim 1 , further comprising a bus and
coupled to the first IC and to the second IC , the bus formed an embedded tester having a test data output coupled to
at least in part on the PCB . a test data input of the first TAP controller by way of
4. The system of claim 3 , wherein the bus includes a a link circuit, the link circuit comprising a resistor
signal line coupled to a first logic block and a first boundary 55 having a first terminal coupled at the test data output
scan logic of the first IC and coupled to a second logic block and a second terminal coupled at the test data input,
and a second boundary scan logic of the second IC . the embedded tester configured to provide boundary
5. The system of claim 4 , wherein the first boundary scan scan test commands by way of test control signals to
logic is coupled to the first TAP controller and the second the first TAP controller and the second TAP control
boundary scan logic is coupled to the second TAP controller. 60 ler .
6. The system of claim 4 , wherein the first IC is config- 17. The system of claim 16 , wherein the link circuit is
ured to transfer a first logic value to the second IC by way configured to allow transfer of an output signal from the test
of the signal line during normal operation . data output to the test data input of the first TAP controller
7. The system of claim 6 , wherein the first logic value is when an external PCB tester is not connected to the PCB .
sampled by the first boundary scan logic or the second 65 18. The system of claim 16 , wherein the embedded tester
boundary scan logic in response to a sample command is further configured to provide boundary scan test com
provided by way of the test control signals. mands compliant with the IEEE 1149.1 standard .
 US 10,866,283 B2
11 12
19. The system of claim 16 , further comprising an inter
connect bus coupled to the first IC and to the second IC , the
interconnect bus formed on the PCB .
20. The system of claim 19 , wherein the interconnect bus
comprises a first signal line coupled to a first analog pin of 5
the first IC and to a second analog pin of the second IC .