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Dell Inspiron 3501 Compal Bullseye TGL LA-K034P Rev 1.00 (A00) Схема
Dell Inspiron 3501 Compal Bullseye TGL LA-K034P Rev 1.00 (A00) Схема
2021-03-08
TGL CPU QS TGL CPU Base-U REV : 1.0 (A00)
UC1 UC1
SA0000DRS1L SA0000DXG0L
QS_I3@ PENTIUM@
@ : Un-pop Component
S IC A31 FH8069004531502 QVBG B1 3G S S IC A31 FH8069004531802 QVBK B1 2G S UMA@ : not Support external Graphic card
UC1
SA0000DRR1L UC1
SA0000DXH0L
N3@/V3@ : Inspiron/Vostro
QS_I5@ MSFT@/NMSFT@ : MSFT SKU / Normal SKU
CELERON@
S IC A31 FH8069004530601 QVBD B1 2.4G S
S IC A31 FH8069004531901 QVBS B1 1.8G S
G3@ : Support G3 sharing SPI topology
UC1
SA0000DRG1L
CNV@ : Support CNVi function
2
S5LID@/LID@ : Support S5 LID power up Function/Normal LID close 2
QS_I7@
S IC A31 FH8069004529905 QVBA B1 2.8G S TGL CPU R3 ES_I3@/ES_I5A@/ES_I5B@/QS_I7@ : TGL-U QS Sample
STG@ : C10_gate control VCCSTG
UC1
SA0000DTV2L I2CTCH@/USBTCH@ : Touch Screen support I2C signal / USB signal
R3_I3@
BASE@/PREM@ : Pentium,Celeron/i3,i5,i7
S IC FH8069004531602 SRK08 B1 3G A31 ! I2CPAD@/PS2PAD@ : EC use I2C touch PAD signal(or PS2)
UC1
JP@/JUMP@/PJP@ : JUMP
SA0000DTU2L 100@/1000@ : 10/100 LAN / Giga-LAN
R3_I5@ PRO@/ICPRO@ : only LCDVDD protection/Hinge up protection Support
S IC FH8069004531301 SRK05 B1 2.4G A31 !
EMI@/ESD@/RF@ : EMI, ESD and RF Component
UC1 @EMI@/@ESD@/@RF@ : EMI, ESD and RF Un-POP Component
SA0000DTT2L
CMC@ : XDP Component
3
R3_I7@
S IC FH8069004530104 SRK02 B1 2.8G A31 !
CONN@ : Connector Component 3
KBBL@ : KB Backlight
TPM@/NTPM@ : HW TPM/SW TPM
750_CTPM@ : 750 and china TPM
DAZ part number CTPM@/ST_CTPM@ : China TPM/ST China TPM
DAZ2XB00101 - GCE FFS@ : Free Fall Sensor
DAZ2XB00102 - TRIPOD TYPEC@/NTYPEC@ : Support TypeC/non-TypeC
DAZ2XB00103 - HSB TYPEC@EMI@/TYPEC@ESD@: EMI, ESD ,TypeC Component
DAZ2XB00104 - TMT LBIST@/LBIST@RF@ : LBIST for LCD monitor
Layout Dell logo TP@/CMC@TP@ : Test Point/XDP Test Point
DISPCB@/UMAPCB@ : PCB MB
4 4
Security Classification
2018/04/01
Compal Secret Data
2019/04/01 Title
Compal Electronics, Inc.
COPYRIGHT 2014 Issued Date Deciphered Date
ALL RIGHT RESERVED
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
REV: X01 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
PWB: 9HTP8 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-K034P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 08, 2021 Sheet 1 of 101
A B C D E
A B C D E
Block Diagram
DDR4
SODIMM A
DDR4 3200MHz Channel A
1 P23 1
DDR4
SODIMM B
DDR4 3200MHz Channel B
P24
USB2.0 x 1
Port 1 (USB3.0 Type-A)
USB3.0 x 1 Gen1
eDP connector eDP 1.2 Intel CPU P71
P38 TGL Lake-U 4+2
USB2.0 x 1
HDMI connector , 1.4b DDI x 4 Port 3 (USB3.0 Type-A)
P40 USB3.0 x 1 Gen1
P71
50 x 25 mm
USB3.0 x 2 Gen1
2
USB Type-C 2
Connector
USB2.0 x 1 (Port8)
P50
TPS25814 USB2.0 x 1
P50 BT with WLAN
PCIe x 1 / CNVi
P52
2.5" SATA x 1
HDD/SSD
P67
RTC
# FFS SMBus
2CH SPEAKER
(2CH 2W/4ohm) SPI #dTPM
TI Audio Amplifier NPCT750
LRCLK / SCLK /SDIN
TAS5825M Reserve P66
P55
Cirrus Audio Routing Controller HDA
I2C
CS8409 G3 Sharing SPI ROM PS/2
Topology 16 MB + 8MB
RING2/SLEEVE
Cirrus Audio Codec P6~18
LRCLK / SCLK /SDIN
P54 P9
HP_R/L
CS42L42
P55
Universal Jack
eSPI
P55
4
SMSC KBC 1515 4
MEC1515H
Battery RTC P58
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 2 of 101
A B C D E
5 4 3 2 1
POWER STATES
Signal SLP SLP SLP ALWAYS SUS RUN
USB 2.0 DESTINATION
CLOCKS
State
S3# S4# S5# PLANE PLANE PLANE
1 USB2.0 port1 Board ID & Model ID Table
A A
Note : VCCIN_AUX only down to 0V while SLP_S0# is asserted. On S3 mode, it only can down to 1.1V.
Security Classification
2018/04/01
Compal Secret Data
2019/04/01 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 3 of 101
5 4 3 2 1
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5 4 3 2 1
0ohm 0805
(RA1) +5V_PVDD
SY6288D20AAC USB_EN#
(UU1) +USB3_VCC
0ohm 0603
(RA3) +5V_AVDD
SY6288D20AAC
(UU2) USB_EN# +USB2_VCC 0ohm 1206
D (RS32) +5V_HDD D
Adapter/Battery/19V
CPU PWR
GPU PWR
PJP301 JPC3
Peripheral Device PWR
SY8286BRAC BAS40C +3VS_SSD
(PU301) +3VLP (D1) +RTC_CELL
FUSE 0.5A_13.2V
ALWON -->EN_3V (F7) +TP_VDD
ADAPTER ENLDO_3V5V
+RTC_VCC
0 ohm 0402
(RA6) +3V_DVDD
+PWR_SRC
+19V_VIN (+19VB) LCD_VCC_TEST_EN
+3VALWP +RTC_CELL_VBAT G2895ALK21U or EDP_VDD_EN
to EC (U4)Hinge up PROC +LCDVDD (2)
C
CHARGER CHARGER LCD_VCC_TEST_EN
C
PJP2501 PJP2502
RT9059GSP SIO_SLP_S4#
(PU2501) +2.5VP +2.5V_MEM
DZ1
+2.5V_PG
PJPM01
RT8207PGQW +2.5V_PG PJPM02
(PUM01) +1.2VP +1.2V_DDR
0.6V_DDR_VTT_ON PJPM03
IMVP_VR_ON_EN +0.6VSP +0.6V_DDR_VTT
RT3612EBGQW +VCCIN
A
(PUZ1) A
1.8V_PRIM_PG
RT6543AGQW
(PUG1) +VCCIN_AUX
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power MAP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 4 of 101
5 4 3 2 1
5 4 3 2 1
Power Up Sequence
G3 to S0
CHR Output B+
EC Input ACAV_IN
D D
EC Output EN_3V/EN_5V
VR Output +3VALW
VR Output +5VALW
VR Output POK
VCCDSW_EN_GPIO
tPCH05
PCH Input +3VALW_DSW tPCH04
VR Output 1.8V_PRIM_PG
VR Output +VCCST_CPU
VR Output +2.5V_MEM
B B
VR Output +2.5V_PG
VR Output +1.2V_DDR
VR Output 1.2V_VTT_PWRGD
VR Output +0.6V_DDR_VTT
+VCCSTG_CPU
+3VS
+5VS
VR Output +VCCIN
VR Output IMVP_VR_PG
tCPU10
tCPU16
VR Output PCH_PWROK tPCH08
tPLT05
EC Output SYS_PWROK
tPCH33
PCH Output PCH_PLTRST#
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Platform Power Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 5 of 101
5 4 3 2 1
5 4 3 2 1
D D
UC1A
AC2 REV 1.6 AY2
AC1 DDIA_TXP_3 TCP0_TXRX_P1 AY1
AD2 DDIA_TXN_3 TCP0_TXRX_N1 BB1
AD1 DDIA_TXP_2 TCP0_TXRX_P0 BB2
AF1 DDIA_TXN_2 TCP0_TXRX_N0 AM5
<38> EDP_TXP1 AF2 DDIA_TXP_1 TCP0_TX_P1 AM7
<38> EDP_TXN1 AG2 DDIA_TXN_1 TCP0_TX_N1 AT7
<38> EDP_TXP0 AG1 DDIA_TXP_0 TCP0_TX_P0 AT5
+3VS eDP <38> EDP_TXN0
AJ2
DDIA_TXN_0 TCP0_TX_N0
TCP0_AUX_P
AP7
AP5
<38> EDP_AUXP DDIA_AUX_P TCP0_AUX_N
AJ1
<38> EDP_AUXN DDIA_AUX_N AT2
RC4031 1 2 2.2K_0402_5% CPU_DP1_CTRL_CLK DN4 TCP1_TXRX_P1 AT1
DT6 GPP_E22/DDPA_CTRLCLK/DNX_FORCE_RELOAD TCP1_TXRX_N1 AU1
RC4032 2 1 2.2K_0402_5% CPU_DP1_CTRL_DATA GPP_E23/DDPA_CTRLDATA TCP1_TXRX_P0 AU2
EDP_HPD DR5 TCP1_TXRX_N0 AD5
<38> EDP_HPD GPP_E14/DDSP_HPDA/DISP_MISCA TCP1_TX_P1 AD7
T12 TCP1_TX_N1 AH7
<40> CPU_DP1_P3 DDIB_TXP_3 TCP1_TX_P0
T11 AH5
<40> CPU_DP1_N3 DDIB_TXN_3 TCP1_TX_N0
Y11 AF7
<40> CPU_DP1_P2 DDIB_TXP_2 TCP1_AUX_P
Y9 AF5
+3VALW_PCH HDMI <40>
<40>
CPU_DP1_N2
CPU_DP1_P1
T9
P9
DDIB_TXN_2
DDIB_TXP_1
TCP1_AUX_N
BF1
<40> CPU_DP1_N1 DDIB_TXN_1 TCP2_TXRX_P1
V11 BF2
<40> CPU_DP1_P0 DDIB_TXP_0 TCP2_TXRX_N1
V9 BE2
KB_DET# <40> CPU_DP1_N0 DDIB_TXN_0 TCP2_TXRX_P0
RC1 1 2 100K_0201_5% BE1
AB9 TCP2_TXRX_N0 BD7
RC2 1 2 10K_0201_5% USB_OC1# AD9 DDIB_AUX_P TCP2_TX_P1 BD5
DDIB_AUX_N TCP2_TX_N1 AY5
RC3 1 2 10K_0201_5% USB_OC2# DM29 TCP2_TX_P0 AY7
C <40> CPU_DP1_CTRL_CLK GPP_H16/DDPB_CTRLCLK/PCIE_LNK_DOWN TCP2_TX_N0 C
DK27 BB5
<40> CPU_DP1_CTRL_DATA GPP_H17/DDPB_CTRLDATA TCP2_AUX_P BB7
CPU_DP1_HPD DG43 TCP2_AUX_N
EDP_HPD <40> CPU_DP1_HPD GPP_A18/DDSP_HPDB/DISP_MISCB/I2S4_RXD
RC5 1 2 100K_0201_5% BK1
DG47 TCP3_TXRX_P1 BK2
RC7 1 @ 2 100K_0201_5% USB_OC1# KB_DET# DJ47 GPP_A21/DDPC_CTRLCLK/I2S5_TXD TCP3_TXRX_N1 BJ2
<63> KB_DET# GPP_A22/DDPC_CTRLDATA/I2S5_RXD TCP3_TXRX_P0 BJ1
DU8 TCP3_TXRX_N0 BM7
TBT_0_LSX_RX Strap Pin DV8 GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD TCP3_TX_P1 BM5
RC338 1 @ 2 100K_0201_5% BKLT_IN_CPU GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD TCP3_TX_N1 BH5
DF6 TCP3_TX_P0 BH7
TBT_1_LSX_RX Strap Pin DD6 GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD TCP3_TX_N0 BK5
Pull Low with eDP Side GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD TCP3_AUX_P BK7
DN23 TCP3_AUX_N
TBT_2_LSX_RX Strap Pin DM23 GPP_D9/ISH_SPI_CS#/DDP3_CTRLCLK/TBT_LSX2_TXD/GSPI2_CS0# AN2 TCRCOMP_DP RC8 1 2 150_0201_1%
GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/TBT_LSX2_RXD/GSPI2_CLK TC_RCOMP_P AN1 TCRCOMP_DN
DK23 TC_RCOMP_N
GPIO DEVICE CONTROL TBT_3_LSX_RX Strap Pin DN21 GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/TBT_LSX3_TXD/GSPI2_MISO M8 DSI_DE_TE RC9 1 2 100K_0201_5%
GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/TBT_LSX3_RXD/GSPI2_MOSI DSI_DE_TE_2
USB_OC0# USB Port (MB) TP@ TP190 1 PAD~D GPP_A17 DF43 AB1 DDI_RCOMP RC10 1 2 150_0201_1%
CPU_DP1_HPD RC4194 1 @ 2 0_0201_5% CPU_DP1_HPD_R DF45 GPP_A17/DISP_MISCC/I2S4_TXD DDI_RCOMP
USB_OC1# USB Port (IO) DF47 GPP_A19/DDSP_HPD1/DISP_MISC1/I2S5_SCLK CE4 DISP_UTILS 1 TP1
GPP_A20/DDSP_HPD2/DISP_MISC2/I2S5_SFRM DISP_UTILS/DSI_DE_TE_1 PAD~D
USB_OC2# TYPE-C USB_OC1# DH52 TP@
<73> USB_OC1# USB_OC2# GPP_A14/USB_OC1#/DDSP_HPD3/I2S3_RXD/DISP_MISC3/DMIC_CLK_B1
DK45
<50> USB_OC2# GPP_A15/USB_OC2#/DDSP_HPD4/DISP_MISC4/I2S4_SCLK
USB_OC3# NA
DM8
<38> EDP_VDD_EN BKLT_IN_CPU DN8 EDP_VDDEN
DEVSLP0 HDD <10> BKLT_IN_CPU DG10 EDP_BKLTEN
<38> EDP_BKLT_CTRL EDP_BKLTCTL
DEVSLP1 NA
DEVSLP2 M.2 SSD @ TGL-U_BGA1449
BKLT_IN_EDP 2 @ 1 BKLT_IN_CPU
<38> BKLT_IN_EDP RC339 0_0201_5%
B
R-short 0831 B
1
1
RC11 RC270 RC12 RC272
@ 4.7K_0201_5% @ 4.7K_0201_5% @ 4.7K_0201_5% @ 4.7K_0201_5%
2
2
2
2
2
1
1
TBT LSX #0 PINS VCCIO CONFIGURATION TBT LSX #1 PINS VCCIO CONFIGURATION TBT LSX #2 PINS VCCIO CONFIGURATION TBT LSX #3 PINS VCCIO CONFIGURATION
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P006 - TGL-U(1/13)TCSS,EDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 6 of 100
5 4 3 2 1
5 4 3 2 1
DIMM TYPE BOOT STRAP 3 BOOT STRAP 2 BOOT STRAP 1 Reserved Reserved
GPP_H2 (Weak internal PD 20K) GPP_H1 (Weak internal PD 20K) GPP_H0 (Weak internal PD 20K) GPP_F7 (Weak internal PD 20K) GPP_F10 (Weak internal PD 20K)
1 : Interleave
This is bit 3 of a total of 4-bit encoded pin straps for This is bit 2 of a total of 4-bit encoded pin straps for This is bit 1 of a total of 4-bit encoded pin straps for
0 : Non-Interleave boot configuration. boot configuration. boot configuration.
+1.05V_VCCSTG
+1.05V_VCCST
1
RC35
RC30 1 2 1K_0201_5% H_CATERR# 1K_0201_5%
UC1U
RC33 1 2 1K_0201_5% H_THERMTRIP# REV 1.6
2
H_CATERR# M7 K4 SOC_XDP_TRST#
PECI_EC_R CATERR# PROC_TRST# SOC_XDP_TMS SOC_XDP_TRST# <79>
BK9 B9
<58> PECI_EC_R H_PROCHOT#_R PECI PROC_TMS SOC_XDP_TDO SOC_XDP_TMS <79>
RC37 1 2 499_0201_1% E2 D12
<16,58,82,84,88> H_PROCHOT# H_THERMTRIP# M5 PROCHOT# PROC_TDO A12 SOC_XDP_TDI SOC_XDP_TDO <79> PU on P.79
THRMTRIP# PROC_TDI SOC_XDP_TCK0 SOC_XDP_TDI <79>
B6
CPU_POPI_RCOMP PROC_TCK SOC_XDP_TCK0 <79>
@EMI@ RC38 2 1 49.9_0201_1% CT39
0.1U_0201_25V6K 2 1 CC730 H_THERMTRIP# RC39 2 1 49.9_0201_1% PCH_OPI_RCOMP CB9 PROC_POPIRCOMP D8 SOC_XDP_TCK0
RC40 2 @ 1 49.9_0201_1% A_PCH_OPIICCOBS CW12 PCH_OPIRCOMP PCH_JTAGX A9 SOC_XDP_TMS +VCCSTG_CPU
0.1U_0201_25V6K 2 1 CC731 H_PROCHOT#_R RC41 2 @ 1 49.9_0201_1% A_PCH_OPIICCCTL CM39 TP_1 PCH_TMS E12 SOC_XDP_TDO
TP_2 PCH_TDO B12 SOC_XDP_TDI
@EMI@ DBG_PMODE Strap Pin DF4 PCH_TDI A7 PCH_JTAG_TCK1
<79> DBG_PMODE DBG_PMODE PCH_TCK PCH_JTAG_TCK1 <79>
1
Strap setting in Page 79 H4 SOC_XDP_TRST#
EMI request,Place near CPU side. <38> TS_DET#
TS_DET#
TOUCH_PAD_INT#
DB42
DB41 GPP_B4/CPU_GP3
PCH_TRST#
C11 XDP_PREQ#
RC43
1K_0201_5%
TOUCH_SCREEN_PD# GPP_B3/CPU_GP2 PROC_PREQ# XDP_PREQ# <79>
RC279 1 @ 2 0_0201_5% TOUCH_SCREEN_PD#_R DF8 D11 XDP_PRDY#
<10,38> TOUCH_SCREEN_PD# MEM_INTERLEAVED GPP_E7/CPU_GP1 PROC_PRDY# XDP_PRDY# <79>
DU5
2
GPP_E3/CPU_GP0 G1 Strap Pin CPU_EAR
GPP_H2 Strap Pin DF31 EAR_N/EAR_N_TEST_NCTF
GPP_H2
1
GPP_H1 Strap Pin DV32 DT15 Strap Pin GPP_F7 @
GPP_H0 Strap Pin DW32 GPP_H1 GPP_F7 DR15 RC44
GPP_H0 GPP_F9 DT14 Strap Pin GPP_F10 1K_0201_5%
C GPP_F10 C
DJ27
GPP_H19/TIME_SYNC0
2
Stall reset sequence after PCU PLL
RC395 @ TGL-U_BGA1449
1 @ 2 TOUCH_PAD_INT# lock until de-asserted:
<58,63> TOUCHPAD_INTR# 1 = (Default) Normal Operation; No stall.
+3VS
0_0201_5%
R-short 0831 0 = Stall.
ESD@
RC36 1 @ 2 10K_0201_5% TOUCH_PAD_INT# H_PROCHOT# CC944 1 2 0.1U_0201_10V6K
ESD@
H_PROCHOT# CC945 1 2 0.1U_0201_10V6K
UC1T
+VCCIO_OUT Follow PDG REV 1.6
CFG15 T15 A51 RSVD_TP_7 PAD~D 1 TP@ TP2
CFG14 Strap Pin V17 CFG_15 RSVD_TP_7 B51 RSVD_TP_8 PAD~D 1 TP@ TP3
CFG13 U15 CFG_14 RSVD_TP_8
RC4147
RC4146
1
1
2
2
1K_0201_5%
1K_0201_5%
CFG11
CFG10
CFG12
CFG11
K11
K12
CFG_13
CFG_12
CFG_11
RSVD_TP_9
RSVD_TP_10
C1
D2
RSVD_TP_9
RSVD_TP_10
PAD~D 1
PAD~D 1
TP@
TP@
TP4
TP5
Non-I2CTCH --> RC295 pop
RC4145 1 2 1K_0201_5% CFG9 CFG10 K9 +3VALW_PCH
RC4143 1 2 1K_0201_5% CFG3 CFG9 T17 CFG_10 CP39 RSVD_TP_11 PAD~D 1 TP@ TP6
RC4142 1 2 1K_0201_5% CFG2 CFG8 K7 CFG_9 RSVD_TP_11 CU40 RSVD_TP_12 PAD~D 1 TP@ TP7
RC4141 1 2 1K_0201_5% CFG1 CFG7 Strap Pin H7 CFG_8 RSVD_TP_12 AK9 TS_DET# 100K_0201_5% 1 2 RC295
CFG6 K8 CFG_7 RSVD_12
CFG5 H9 CFG_6 AH9
B B
CFG4 Strap Pin E6 CFG_5 RSVD_13
RC4177 1 @ 2 1K_0201_5% CFG0 CFG3 H5 CFG_4 DW6
CFG_3 RSVD_14
@
RC4178 1 @ 2 1K_0201_5% CFG5 CFG2 E9 DV6 TS_DET# 100K_0201_5% 1 2 RC294
CFG1 D9 CFG_2 RSVD_15
RC4180 1 @ 2 1K_0201_5% CFG8 CFG0 E7 CFG_1 DV4 RSVD_TP_13 PAD~D 1 TP@ TP8
RC4181 1 @ 2 1K_0201_5% CFG12 CFG_0 RSVD_TP_13 DW3 RSVD_TP_14 PAD~D 1 TP@ TP9
RC4182
RC4183
1
1
@
@
2
2
1K_0201_5%
1K_0201_5%
CFG13
CFG15
RC49 2 1 49.9_0402_1% CFG_RCOMP B5
CFG_RCOMP
RSVD_TP_14
RSVD_TP_15
DU1 RSVD_TP_15 PAD~D 1 TP@ TP10
I2CTCH --> RC294 pop
CMC@TP@ TP95 1 CFG17 U17 DT2 RSVD_TP_16 PAD~D 1 TP@ TP11
1 CFG16 H11 CFG_17 RSVD_TP_16
Reserve CMC@TP@ TP94
CFG_16 RSVD_TP_17 Pin Name TS_DET#
DW2 PAD~D 1 TP@ TP12
BPM#3 Y1 RSVD_TP_17 DV2 RSVD_TP_18 PAD~D 1 TP@ TP13
RC50 1 2 10K_0201_5% BPM#3 BPM#2 M4 BPM#_3 RSVD_TP_18 TOUCH HIGH
RC51 1 2 10K_0201_5% BPM#2 BPM#1 AB4 BPM#_2 E1 RSVD_TP_19 PAD~D 1 TP@ TP14
pull high in XDP side
<79> BPM#1
BPM#0 Y2 BPM#_1 RSVD_TP_19 F1 RSVD_TP_20 PAD~D 1 TP@ TP15
Non TOUCH LOW
<79> BPM#0 BPM#_0 RSVD_TP_20
X01_10
TPC0_MBIAS_RCOMP
A3
B3 RSVD_6
RSVD_7
RSVD_16
RSVD_TP_21
AB2
DR1 RSVD_TP_21
RSVD_TP_22
PAD~D 1 TP@ TP16
Panel TOUCH DETECT#
AR2 DR2 PAD~D 1 TP@ TP18
TP19 TP@ 1 PAD~D RSVD_TP_2 AL10 TCP0_MBIAS_RCOMP RSVD_TP_22
1
+VCCIO_OUT TP20 TP@ 1 PAD~D RSVD_TP_3 AM12 RSVD_TP_2 DR53 RSVD_TP_23 PAD~D 1 TP@ TP21
RC768 TP22 TP@ 1 PAD~D RSVD_TP_4 AH12 RSVD_TP_3 RSVD_TP_23 DW5 RSVD_TP_24 PAD~D 1 TP@ TP23
2.2K_0201_1% TP24 TP@ 1 PAD~D RSVD_TP_5 AJ10 RSVD_TP_4 RSVD_TP_24
RC4179 1 @ 2 1K_0201_5% TP25 TP@ 1 PAD~D RSVD_TP_6 AR1 RSVD_TP_5 DV51
RSVD_TP_6 VSS_1 DW52 TP_3 PAD~D 1 TP@ TP26
2
RC4239 1 @ 2 1K_0201_5% CFG6 BN10 TP_3 DV53 TP_4 PAD~D 1 TP@ TP27
BM12 RSVD_8 TP_4 W34
DD13 RSVD_9 RSVD_17 V35
DF13 RSVD_10 RSVD_18
RSVD_11 D52 SKTOCC# PAD~D 1 TP@ TP185
reserve pull down , refer by PDG 2.0 SKTOCC#
@ TGL-U_BGA1449
D D
UC1B UC1C
REV 1.6 REV 1.6
@ TGL-U_BGA1449
+VCC1.05_OUT_FET +VCCIN
1
RC4118 RC45
24.9_0201_1% 24.9_0201_1%
@ @
2
DP_COMP
UC1D
+1.2V_DDR REV 1.6
DDR_RCOMP_2 DW47
0.1U_0201_10V6K 2 1 CC1 RD30 DDR_RCOMP_1 DW49 RSVD_3
RSVD_4
1
1
UC4
1 5 RC4042 RC4119 RC4120
2
A 4 DDR_DRAMRST#_R 1 @ 2 DDR_DRAMRST#
<86>
2
3 Y 0.6V_DDR_VTT_ON <23,24> DDR_DRAMRST#_R
1 RD29 0_0201_5%
GND @
74AUP1G07GW_TSSOP5 CC2
100P_0402_50V8J
2 R-short 0831
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P008 - TGL-U(3/13)LPDDR4/x
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 8 of 100
5 4 3 2 1
5 4 3 2 1
BOOT HALT CONSENT STRAP A0 PERSONALITY STRAP TLS CONFIDENTIALITY CPUNSSC CLOCK FREQ ESPI OR EC LESS
SPI0_MOSI(NO INTERNAL PU/PD) SPI0_IO2(NO INTERNAL PU/PD) SPI0_IO3 GPP_C2 (Weak internal PD 20K) GPP_B23 (Weak internal PD 20K) GPP_C5 (Weak internal PD 20K)
0 = Enable 0 = Enable 0 = Enable 0 = TLS CONFIDENTIALITY DISABLE 0 = 38.4 MHz clock direct from crystal (default) 0 = Enable eSPI. (Default)
1 = Disable 1 = Disable 1 = Disable 1 = TLS CONFIDENTIALITY ENABLE 1 = 19.2 MHz clock from divider (Device from 38.4MHz crystal) 1 = Disable eSPI.
+3VALW_PCH +3VALW_PCH +3VALW_PCH
+3VALW_PCH +1.8V_PRIM +3VALW_PCH +1.8V_PRIM +3VALW_PCH +1.8V_PRIM
EDS recommend
100K(RVP(0.7) NC) GPP_C2 RC61 1 @ 2 4.7K_0201_5% GPP_B23 RC63 1 @ 2 4.7K_0201_5% GPP_C5 RC62 1 @ 2 4.7K_0201_5%
RC64 1 2 4.7K_0201_5% RC65 1 2 100K_0201_5% RC66 1 2 100K_0201_5%
RC67 1 2 4.7K_0201_5% RC69 1 @ 2 4.7K_0201_5% RC68 1 @ 2 4.7K_0201_5%
CPU_SPI_0_D0 RC70 1 @ 2 4.7K_0201_5% CPU_SPI_0_D2 RC71 1 @ 2 4.7K_0201_5% CPU_SPI_0_D3 RC72 1 @ 2 100K_0201_5%
RC73 1 @ 2 20K_0201_5% RC75 1 @ 2 20K_0201_5% RC74 1 @ 2 20K_0201_5%
D D
no need this security for CSMB This strap is used in conjunction with Boot Strap 1,2,3, (on GPP_H0, GPP_H1, GPP_H2
respectively).
(internal PD) 0000 = Master Attached Flash Configuration (BIOS / CSME on SPI). <--use this
Reserved 1000 = Slave Attached Flash Configuration (BIOS / CSME on eSPI attached device).
0100 = BIOS on eSPI Peripheral Channel; CSME on master attached SPI.
1100 = BIOS on eSPI peripheral Channel; CSME on slave attached SPI.
Others: Reserved.
GPP_E6 (External pull-up is required)
+3VALW_PCH +1.8V_PRIM
RC99 1 @ 2 4.7K_0201_5%
PCH_SMBDATA 2.2K_0201_5% 2 1 RC4052
PCH_SMBCLK 2.2K_0201_5% 2 1 RC4053
UC1E
REV 1.6
RC87 1 2 100K_0201_5%
+3VALW_PCH
CPU_SPI_0_CLK DJ37 DK21 MEM_SMBCLK
CPU_SPI_0_D3 Strap Pin DG35 SPI0_CLK GPP_C0/SMBCLK DM19 MEM_SMBDATA
CPU_SPI_0_D2 DJ39 SPI0_IO3 GPP_C1/SMBDATA DN19 Strap Pin (1.8V) GPP_C2 DDR4,XDP
Strap Pin
CPU_SPI_0_D1 DJ33 SPI0_IO2 GPP_C2/SMBALERT# MEM_SMBCLK RC4051 1 2 1K_0201_5%
CPU_SPI_0_D0 Strap Pin DJ35 SPI0_MISO DK19 SML0_SMBCLK RC4160 1 2 0_0201_5% MEM_SMBDATA RC4050 1 2 1K_0201_5%
CPU_SPI_0_CS#1 SPI0_MOSI GPP_C3/SML0CLK GPU_THM_SMBCLK <58,66>
DF35 DM17 SML0_SMBDATA RC46 1 2 0_0201_5% GPU,THM.EC
CPU_SPI_0_CS#0 DG37 SPI0_CS1# GPP_C4/SML0DATA DN17 Strap Pin GPP_C5 GPU_THM_SMBDAT <58,66>
+3VS CPU_SPI_0_CS#2 DF39 SPI0_CS0# GPP_C5/SML0ALERT# SML0_SMBDATA RC82 1 2 499_0201_1%
To TPM <66> CPU_SPI_0_CS#2 SPI0_CS2# DK17 SML1_SMBCLK SML0_SMBCLK RC84 1 2 499_0201_1%
DJ6 GPP_C6/SML1CLK DJ17 SML1_SMBDATA
DN5 GPP_E11 / THC0_SPI1_CLK GPP_C7/SML1DATA CY50 Strap Pin GPP_B23 Type-C , TBT
DR9 GPP_E2 / THC0_SPI1_IO3 GPP_B23/SML1ALERT#/PCHHOT#/GSPI1_CS1# SML1_SMBCLK RC85 1 2 1K_0201_5%
RC4130 1 2 10K_0201_5% SATA_LED# DM6 GPP_E1 / THC0_SPI1_IO2 DN53 1.8V ESPI_CLK_R RC88 1 2 49.9_0201_1% SML1_SMBDATA RC86 1 2 1K_0201_5%
C GPP_E12 / THC0_SPI1_IO1 GPP_A5/ESPI_CLK ESPI_IO3_R ESPI_CLK <58> C
DK6 DJ53 1.8V RC89 1 2 15_0201_1%
GPP_E13 / THC0_SPI1_IO0 GPP_A3/ESPI_IO3/SUSACK# ESPI_IO2_R ESPI_IO3 <58>
DK8 DH50 1.8V RC90 1 2 15_0201_1%
SATA_LED# GPP_E10 / THC0_SPI1_CS# GPP_A2/ESPI_IO2/SUSWARN#_SUSPWRDNACK ESPI_IO1_R ESPI_IO2 <58>
DV11 DP50 1.8V RC92 1 2 15_0201_1% ESPI 1.8V
<63,68> SATA_LED# GPP_E8 / SATA_LED# GPP_A1/ESPI_IO1 ESPI_IO0_R ESPI_IO1 <58>
3.3V DW9 DP52 1.8V RC95 1 2 15_0201_1%
GPP_E6 GPP_E17/THC0_SPI1_INT# GPP_A0/ESPI_IO0 ESPI_CS# ESPI_IO0 <58>
Strap Pin (1.8V) DT8 DK52 1.8V
GPP_E6/THC0_SPI1_RST# GPP_A4/ESPI_CS# ESPI_RESET# ESPI_CS# <58>
DL50 1.8V
GPP_A6/ESPI_RESET# ESPI_RESET# <58>
3.3V DN15
1.8V DK13 GPP_F11/THC1_SPI2_CLK
1.8V DM13 GPP_F15/GSXSRESET#/THC1_SPI2_IO3
GPP_F14/GSXDIN/THC1_SPI2_IO2 Check!!
1.8V DN13 AEP pop RC91/RC93
1.8V DJ15 GPP_F13/GSXSLOAD/THC1_SPI2_IO1 +1.8V_PRIM
GPP_F12/GSXDOUT/THC1_SPI2_IO0 RVP unpop RC91/RC93
DK15
DN10 GPP_F16/GSXCLK/THC1_SPI2_CS# RC91 1 @ 2 1K_0201_5%
DV14 GPP_F18/THC1_SPI2_INT#
GPP_F17/THC1_SPI2_RST# ESPI_CS# RC93 1 @ 2 75K_0201_1%
DH3
DH4 CL_CLK
Didn't support C-Link DF2 CL_DATA ESPI_RESET# RC96 1 2 75K_0201_1%
CL_RST#
R1 R3 SPI1-64Mb @ TGL-U_BGA1449
PCH
R4 SPI2-128Mb
+3VS
2
L2N7002DW1T1G_SC88-6
MEM_SMBCLK 6 1
PCH_SMBCLK <23,24>
R1
5
QC6B DDR4
L2N7002DW1T1G_SC88-6
CPU_SPI_0_CLK RC76 1 2 0_0201_5% CPU_SPI_0_CLK_R NPI pop D11 MEM_SMBDATA 3 4
PCH_SMBDATA <23,24>
CPU_SPI_0_D3 CPU_SPI_0_D3_R
CPU_SPI_0_D2
RC77
RC78
1
1
2
2
0_0201_5%
0_0201_5% CPU_SPI_0_D2_R
MP pop RC56
PCH Side CPU_SPI_0_D1
CPU_SPI_0_D0
RC79 1 2 0_0201_5% CPU_SPI_0_D1_R
CPU_SPI_0_D0_R
+3.3V_SPI +3VALW_PCH
RC80 1 2 0_0201_5%
B B
RC300 1 2 0_0402_5%
R2 R2 should place near P.58 UE1 (EC side)
SHD_CLK RC23 1 2 100_0201_1% CPU_SPI_0_CLK_R
<58> SHD_CLK SHD_IO3 CPU_SPI_0_D3_R
RC24 1 NTPM@ 2 100_0201_1%
<58> SHD_IO3 SHD_IO2 CPU_SPI_0_D2_R
RC25 1 NTPM@ 2 100_0201_1%
From EC <58>
<58>
SHD_IO2
SHD_IO1
SHD_IO1
SHD_IO0
RC26 1 2 100_0201_1% CPU_SPI_0_D1_R
CPU_SPI_0_D0_R
+3VALW_PCH For EC Auto Load Code
RC27 1 2 100_0201_1%
<58> SHD_IO0
RC349 1 G3@ 2 4.7K_0201_5% CPU_SPI_0_CS#0 RC4173 1 G3@ 2 0_0201_5%
SHD_CS0# <58>
R3 RC350 1 G3@ 2 4.7K_0201_5% CPU_SPI_0_CS#1 RC4174 1 G3@ 2 0_0201_5%
SHD_CS1# <58>
CPU_SPI_0_CLK_R RC102 1 2 15_0201_1% SPI_CLK_ROM
CPU_SPI_0_D3_R RC103 1 2 15_0201_1% SPI_D3_ROM
CPU_SPI_0_D2_R RC104 1 2 15_0201_1% SPI_D2_ROM
CPU_SPI_0_D1_R
CPU_SPI_0_D0_R
RC105 1 2 15_0201_1% SPI_D1_ROM
SPI_D0_ROM
To SPI ROM 1
RC106 1 2 15_0201_1%
+3.3V_SPI
R4 CC5
1 2
0.1U_0402_10V7K
CPU_SPI_0_CLK_R RC341 1 2 15_0201_1% SPI_CLK_ROM2 UC5
@
CPU_SPI_0_D3_R RC342 1 2 15_0201_1% SPI_D3_ROM2 CPU_SPI_0_CS#0 1 8
CPU_SPI_0_D2_R RC343 1 2 15_0201_1% SPI_D2_ROM2 SPI_D1_ROM 2 /CS VCC 7 SPI_D3_ROM
CPU_SPI_0_D1_R
CPU_SPI_0_D0_R
RC344 1 2 15_0201_1% SPI_D1_ROM2
SPI_D0_ROM2
To SPI ROM 2 SPI_D2_ROM 3 DO(IO1)
/WP(IO2)
/HOLD(IO3)
CLK
6 SPI_CLK_ROM
SPI_D0_ROM
RC345 1 2 15_0201_1% 4 5
GND DI(IO0)
GD25B64CSIGR_SO8
SA000039A40 W25Q64JVSSIQ Use X76 control UC5 and UC6
R5 should place near P.66 UX1 (TPM side) 64Mb Flash ROM X7687131L84 - Winbond
R5 X7687131L85 - Gigadevice
CPU_SPI_0_CLK_R
CPU_SPI_0_D1_R
RC346
RC347
1 TPM@
1 TPM@
2
2
15_0201_1%
15_0201_1%
SPI_CLK_TPM
SPI_D1_TPM SPI_CLK_TPM <66> ROM_1 +3.3V_SPI X7687131L86 - XMC
CPU_SPI_0_D0_R RC348 1 TPM@ 2 15_0201_1% SPI_D0_TPM SPI_D1_TPM
SPI_D0_TPM
<66>
<66>
To TPM
1 2 RF@ @RF@
RF Request
CC6 0.1U_0402_10V7K SML1_SMBCLK CC4 1 2 33P_0201_50V8J
UC6
@
CPU_SPI_0_CS#1 1 8
SPI_D1_ROM2 2 CS# VCC 7 SPI_D3_ROM2 @EMI@ @EMI@
A For 2 Flash + 1 TPM SPI_D2_ROM2 3 DO(IO1) IO 6 SPI_CLK_ROM2 EMI@ SPI_CLK_ROM RC40542 1 CC7 2 1 A
4 IO2 CLK 5 SPI_D0_ROM2 33_0402_5%
GND DI(IO0) 33P_0402_50V8J
R2 R3 R4
W25Q128JVSIQ_SO8
SA00005VV20 W25Q128JVSIQ
place colse to UC5
128Mb Flash ROM
RC24 TPM@
49.9_0201_1%
SD00000TO00 FLASH ROM ROM_2
RC25 TPM@
49.9_0201_1%
SD00000TO00
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2020/10/01 Deciphered Date 2018/10/01 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P009 - TGL-U(4/13)SPI,SMB,ESPI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 9 of 100
5 4 3 2 1
5 4 3 2 1
D D
UC1F
REV 1.6 +3VS
+3VS
56P_0201_25V8J
CC946
2.2P_0201_50V8B
CC14 @RF@
2.2P_0201_50V8B
CC16 @RF@
2 2 2 1 = DISABLE (ME can update)
@RF@
HDA for Audio ME_FWP_PCH 1 HDA_SDOUT
Capacitor to only be used for HDA_SDO, HDA_RST#, and
<58> ME_FWP 1 @ 2 2
HDA_SDI for EMI purposes and should be a close as RC147 0_0201_5% RC148 2.2K_0201_5%
possible to the PCH.
R-short 0831
B UC1G B
REV 1.6
+3VALW_PCH
@
N3V3 100K_0201_5% 1 2 RC3952
+1.8V_PRIM
Pin Name Net name : N3V3
A CPU_ID A
2nd source Audio control change to MSFT control (Default) RC108 1 PREM@ 2 100K_0201_5%
RC109 1 2 100K_0201_5% TYPEC
TYPEC@
main source Audio control change to MSFT control RC110 1 BASE@ 2 100K_0201_5% CPU_ID
RC111 1 2 100K_0201_5% TYPEC
NTYPEC@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P010 - TGL-U(5/13)HDA,I2C,ISH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 10 of 100
5 4 3 2 1
5 4 3 2 1
+3VS
UC1K
1
REV 1.6
3
4
BW1 DU14 GPP_F19 PAD~D 1 RC167
BW2 CLKOUT_PCIE_P6
GPP_F19/SRCCLKREQ6# DF23 TP191 TP@ 200K _0201_1% YH1
CLKOUT_PCIE_N6
GPP_H11/SRCCLKREQ5# DG25 CLKREQ_PCIE#4 38.4MHZ_10PF_8Y38420005
CB2 GPP_H10/SRCCLKREQ4# DT24 CLKREQ_PCIE#4 <68> <--SSD
1
2
CB1 CLKOUT_PCIE_P5GPP_D8/SRCCLKREQ3# DT30 CLKREQ_PCIE#2 EMI@
CLKOUT_PCIE_N5GPP_D7/SRCCLKREQ2# DV30 CLKREQ_PCIE#1 CLKREQ_PCIE#2 <51> <--LAN RC168 CC169
D GPP_D6/SRCCLKREQ1# DW30
CLKREQ_PCIE#1 <52> <-- WLAN 33_0201_5% 10P_0201_50V8J D
BW4 GPP_D5/SRCCLKREQ0# <-- GPU XTAL_PCH_38P4M_OUT 1 2 XTAL_38P4M_OUT 1 2
SSD --> <68>
<68>
CLK_PCIE_P4
CLK_PCIE_N4
BW5 CLKOUT_PCIE_P4
CLKOUT_PCIE_N4 XTAL_OUT
DM1
DL1
XTAL_PCH_38P4M_OUT
XTAL_PCH_38P4M_IN
CL7 XTAL_IN
CL8 CLKOUT_PCIE_P3 DW41 SUSCLK RC4175 1 2 0_0402_5% RC170 CC171
CLKOUT_PCIE_N3 GPD8/SUSCLK SUSCLK_R <52,58> 0_0201_5% 15P_0201_50V8J
CB4 DT47 PCH_RTCX2 PCH_RTCX1 1 2 PCH_RTCX1_R 1 2
LAN --> <51>
<51>
CLK_PCIE_P2
CLK_PCIE_N2
CB5 CLKOUT_PCIE_P2
CLKOUT_PCIE_N2
RTCX2
RTCX1
DR47 PCH_RTCX1 SUSCLK
2
BY4 DN37 PCH_RTCRST#
1
WLAN --> <52>
<52>
CLK_PCIE_P1
CLK_PCIE_N1
BY3 CLKOUT_PCIE_P1
CLKOUT_PCIE_N1
RTCRST#
SRTCRST#
DK37 SRTCRST# @EMI@ YC1
1
CC140 32.768KHZ_12.5PF_9H03200042
CN7 0.1U_0201_10V6K RC172
GPU -->
1
CN8 CLKOUT_PCIE_P0 2 10M_0201_1% ESR MAX=50k ohm
CLKOUT_PCIE_N0
2
RC174 1 2 60.4_0201_1% XCLK_RCOMP DJ5
2
XCLK_BIASREF RC173
@ TGL-U_BGA1449 2 0_0201_5%
1
@ +RTC_SOC RC175 CC176
CLME1 CC17 0_0201_5% 15P_0201_50V8J
1
SHORT PADS 1U_0201_6.3V6M PCH_RTCX2 1 2 PCH_RTCX2_R 1 2
2
SRTCRST# 1 1 2
RC177 20K_0201_5%
PCH_RTCRST# 1 2
1 RC178 20K_0201_5%
1
@
CLCMOS1 CC18
SHORT PADS 1U_0201_6.3V6M
2
2
C C
+3VALW_PCH
PCH_BATLOW# RC185 1 2 100K_0201_5% Follow Modena MLK and Intel check list
AC_PRESENT
change to 100K
RC186 1 2 100K_0201_5%
ESD@
VCCST_PWRGD CC20 1 2 100P_0201_50V8J
RB751S-40_SOD523-2 DV14 and RC130 co-lay ESD Request:place near CPU side
SCS00006300 CPU_C10_GATE# RC4222 1 2 100K_0201_5%
+3VALW_PCH
UC1L
SIO_SLP_SUS# DV49 REV 1.6 BM9 CPUPWRGD R-short 0831
<78> SIO_SLP_SUS# SLP_SUS# PROCPWRGD
1
+3VALW_PCH
Pin Name TPM_PRSNT#
RC200 1 2 100K_0201_5% SIO_SLP_S0#
LOW TPM (HW)
RC207 1 @ 2 10K_0201_5% PCH_RSMRST#_AND
HIGH NTPM (SW)
2
1 2
CC24 1 @ 2 0.33U_0201_6.3V6M RC199 +3VS
UC32 100K_0201_5% @
5
RC205 1 @ 2 100K_0201_5% SIO_SLP_S5# MC74VHC1G08EDFT2G_SC70 UC31 @
5
PCH_PLTRST# 1 MC74VHC1G08EDFT2G_SC70
STRAP FOR SPI 1.8V/3.3V SEL SA0000BIP00
1
CC25 1 @ 2 0.33U_0201_6.3V6M B 4 1
SA0000BIP00 PCH_PWROK
P
O PLTRST# <51,52,66,68> <88> VR_READY B
1
1 2 4
A O
1
RC206 1 2 100K_0201_5% SIO_SLP_S4# RC209 RUNPWROK 2
<58> RUNPWROK A
G
SPIVCCIOSEL CC3864 100K_0201_5% RC212
3
1
A CC27 1 @ 2 0.33U_0201_6.3V6M 0.1U_0201_10V6K 100K_0201_5% A
3
ESD@ 2 RC4212
2
RC208 1 2 100K_0201_5% SIO_SLP_S3# 0 = SPI voltage is 3.3V (4.7 k pull-down to GND) 100K_0201_5%
2
@
CC28 1 @ 2 0.33U_0201_6.3V6M
1 = SPI voltage is 1.8V (4.7K pull-up to DSW_PWROK)
2
RC210 1 @ 2 100K_0201_5% SIO_SLP_A#
+3VALW_PCH +3VALW_PCH same as +3VALW_DSW
2nd should pick CMOS And gate
CC29 1 @ 2 0.33U_0201_6.3V6M
RC217 1 @ 2 4.7K_0201_5% SPIVCCIOSEL
RC213 1 @ 2 100K_0201_5% SIO_SLP_WLAN#
RC218 1 2 4.7K_0201_5%
CC30 1 @ 2 0.33U_0201_6.3V6M
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2020/10/01 Deciphered Date 2018/10/01 Title
RC216 1 @ 2 100K_0201_5% SIO_SLP_S0#
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P011 - TGL-U(6/13)CLK,GPIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 11 of 100
5 4 3 2 1
5 4 3 2 1
UC1I
BT7 REV 1.6 CV4
BT8
CE2
PCIE12_TXP/SATA1_TXP
PCIE12_TXN/SATA1_TXN
USB2P_10
USB2N_10
CY3 USB20_P10
USB20_N10
<52>
<52> BT
CE1 PCIE12_RXP/SATA1_RXP DD5
PCIE12_RXN/SATA1_RXN USB2P_9 DD4
BT9 USB2N_9
<67> SATA_CTX_DRX_P0 BV9 PCIE11_TXP/SATA0_TXP CW9
SATA HDD ---> <67> SATA_CTX_DRX_N0
<67> SATA_CRX_DTX_P0
CF4 PCIE11_TXN/SATA0_TXN USB2P_8 DA9 USB20_P8 <38>
Touch Screen
CF3 PCIE11_RXP/SATA0_RXP USB2N_8 USB20_N8 <38>
<67> SATA_CRX_DTX_N0 PCIE11_RXN/SATA0_RXN DD1
D
<52> PCIE_CTX_DRX_P10
BV7
BV8 PCIE10_TXP
USB2P_7
USB2N_7
DD2 USB20_P7
USB20_N7
<73>
<73> Card Reader (IO/B) D
B B
UC1H
P5 REV 1.6 V5
P7 PCIE4_TX_P_3 PCIE4_TX_P_1 V7
N1 PCIE4_TX_N_3 PCIE4_TX_N_1 T1
N2 PCIE4_RX_P_3 PCIE4_RX_P_1 T2
PCIE4_RX_N_3 PCIE4_RX_N_1
T5 Y5
T7 PCIE4_TX_P_2 PCIE4_TX_P_0 Y7
R1 PCIE4_TX_N_2 PCIE4_TX_N_0 V1
R2 PCIE4_RX_P_2 PCIE4_RX_P_0 V2
PCIE4_RX_N_2 PCIE4_RX_N_0
Y12 PCIE4_RCOMP_P RC225 1 2 2.2K_0201_1%
PCIE4_RCOMP_P V12 PCIE4_RCOMP_N
PCIE4_RCOMP_N
@ TGL-U_BGA1449
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P012 - TGL-U(7/13)PCIE,USB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 12 of 100
5 4 3 2 1
5 4 3 2 1
UC1J
REV 1.6
D22 DK47
B22 CSI_F_DP_1 CNVI_WT_D1P DM47 CNV_CTX_DRX_P1 <52>
E22 CSI_F_DN_1 CNVI_WT_D1N DN49 CNV_CTX_DRX_N1 <52>
D20 CSI_F_DP_0 CNVI_WT_D0P DR49 CNV_CTX_DRX_P0 <52>
A20 CSI_F_DN_0 CNVI_WT_D0N DN45 CNV_CTX_DRX_N0 <52>
B20 CSI_F_CLK_P CNVI_WT_CLKP DN47 CLK_CNV_CTX_DRX_P <52>
CSI_F_CLK_N CNVI_WT_CLKN CLK_CNV_CTX_DRX_N <52>
D
B18
A18 CSI_E_DP_1/CSI_F_DP_2 CNVI_WR_D1P
DU43
DV43
CNV_CRX_DTX_P1 <52> CNVi D
CSI_E_DN_1/CSI_F_DN_2 CNVI_WR_D1N CNV_CRX_DTX_N1 <52>
D18 DR44
CSI_E_DP_0/CSI_F_DP_3 CNVI_WR_D0P CNV_CRX_DTX_P0 <52>
E18 DT43 CNV_CRX_DTX_N0 <52>
C16 CSI_E_DN_0/CSI_F_DN_3 CNVI_WR_D0N DV44
CSI_E_CLK_P CNVI_WR_CLKP CLK_CNV_CRX_DTX_P <52> +1.8V_PRIM
D16 DW44
CSI_E_CLK_N CNVI_WR_CLKN CLK_CNV_CRX_DTX_N <52>
D15 DN51 CNV_WT_RCOMP RC226 1 2 150_0201_1%
E15 CSI_C_DP_2 CNVI_WT_RCOMP
A15 CSI_C_DN_2 DJ13 1.8V CNV_RGI_CRX_DTX CNV_BRI_CRX_DTX RC227 1 @ 2 20K_0201_5%
CSI_C_DP_3 GPP_F3/CNV_RGI_RSP/UART0_CTS# CNV_RGI_CTX_DRX CNV_RGI_CRX_DTX <52> CNV_RGI_CRX_DTX
B15 DG13 Strap Pin(1.8V) RC229 1 @ 2 20K_0201_5%
CSI_C_DN_3 GPP_F2/CNV_RGI_DT/UART0_TXD CNV_BRI_CRX_DTX CNV_RGI_CTX_DRX <52>
DF15 1.8V
CNV_BRI_CRX_DTX <52>
L18 GPP_F1/CNV_BRI_RSP/UART0_RXD DF17 Strap Pin(1.8V) CNV_BRI_CTX_DRX
CSI_C_DP_1 GPP_F0/CNV_BRI_DT/UART0_RTS# CNV_BRI_CTX_DRX <52>
N18
L20 CSI_C_DN_1 DJ10 CLKREQ_CNV#
N20 CSI_C_DP_0 GPP_F5/MODEM_CLKREQ/CRF_XTAL_CLKREQ DV15 CLKREQ_CNV# <52>
G20 CSI_C_DN_0 GPP_F6/CNV_PA_BLANKING DK10 1.8V CNV_RF_RESET#
H20 CSI_C_CLK_P
CSI_C_CLK_N
GPP_F4/CNV_RF_RESET# CNV_RF_RESET# <52> M.2 CNVI MODES
H16
G16 CSI_B_DP_1
G18 CSI_B_DN_1
H18 CSI_B_DP_0 GPP_F2/CNV_RGI_DT
L16 CSI_B_DN_0
N16 CSI_B_CLK_P CNV_RF_RESET# RC4122 1 2 75K_0201_1% 0 = INTEGRATED CNVI ENABLE
CSI_B_CLK_N
G14 CLKREQ_CNV# RC4132 1 @ 2 10K_0201_5%
H14 CSI_B_DP_2 1 = INTEGRATED CNVI DISABLE
L14 CSI_B_DN_2 +1.8V_PRIM
N14 CSI_B_DP_3
CSI_B_DN_3
RC231 2 1 150_0201_1% CSI_RCOMP K14
CSI_RCOMP RW29 1 CNV@ 2 100K_0201_1%
DK25
DM25 GPP_H23/IMGCLKOUT4 CNV_RGI_CTX_DRX RW30 1 @ 2 4.7K_0201_5%
DN25 GPP_H22/IMGCLKOUT3
DJ25 GPP_H21/IMGCLKOUT2
TP186 TP@ 1 PAD~D GPP_D4 DR30 GPP_H20/IMGCLKOUT1
GPP_D4/IMGCLKOUT_0/BK4/SBK4
@ TGL-U_BGA1449
XTAL SEL
C C
RW32 1 @ 2 4.7K_0201_5%
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P013 - TGL-U(8/13)CSI,CNVi
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 13 of 100
5 4 3 2 1
5 4 3 2 1
+VCCIN
+VCCIN
D D
UC1M 2 2 2 2 2 2
REV 1.6
RF@
CC948
RF@
CC951
RF@
CC949
RF@
CC953
RF@
CC950
RF@
CC952
A24 G32
A26 VCCIN_1 VCCIN_66 H24
A29 VCCIN_2 VCCIN_67 H26 1 1 1 1 1 1
A30 VCCIN_3 VCCIN_68 H30
VCCIN_4 VCCIN_69
10P_0201_25V8
10P_0201_25V8
10P_0201_25V8
10P_0201_25V8
10P_0201_25V8
10P_0201_25V8
A33 H32
A35 VCCIN_5 VCCIN_70 J1
AY39 VCCIN_6 VCCIN_71 J2
VCCIN_7 VCCIN_72
1.The total Length of Data and Clock (from CPU to each VR) must be equal (±0.1
B24 K1 inch).
B26 VCCIN_8 VCCIN_73 K2
VCCIN_9 VCCIN_74
2.Route the Alert signal between the Clock and the Data signals.
B29 K24 CAD Note: Place the PU resistors close to CPU
B30 VCCIN_10 VCCIN_75 K26
B33 VCCIN_11 VCCIN_76 K30 +1.05V_VCCST
B35 VCCIN_12 VCCIN_77 K32
BA10 VCCIN_13
VCCIN_14
VCCIN_78
VCCIN_79
L24 RF Request
BA40 L26
VCCIN_15 VCCIN_80
1
BB39 L30
BB9 VCCIN_16
VCCIN_17
VCCIN_81
VCCIN_82
L32 SVID DATA RC232
BC10 N24 100_0201_5%
BC40 VCCIN_18 VCCIN_83 N26
BD39 VCCIN_19 VCCIN_84 N30
2
BD9 VCCIN_20 VCCIN_85 N32
BE10 VCCIN_21 VCCIN_86 P24
BE40 VCCIN_22 VCCIN_87 P26 SOC_SVID_DAT 1 @ 2
VCCIN_23 VCCIN_88 VR_SVID_DATA <88>
BF9 P28 RC4069 0_0201_5%
BG10 VCCIN_24 VCCIN_89 P30
C BG40 VCCIN_25 VCCIN_90 P32 C
BH12 VCCIN_26 VCCIN_91 T21 R-short 0831
BH39 VCCIN_27 VCCIN_92 T23
BH9 VCCIN_28 VCCIN_93 T25 +1.05V_VCCST
BJ10 VCCIN_29 VCCIN_94 T27
BJ40 VCCIN_30 VCCIN_95 T31
BK39 VCCIN_31 VCCIN_96 U23
VCCIN_32 VCCIN_97
1
BL10 U27
BL40 VCCIN_33
VCCIN_34
VCCIN_98
VCCIN_99
U29 SVID ALERT# RC234
BM39 U31 56_0201_5%
BN40 VCCIN_35 VCCIN_100 U33
BP12 VCCIN_36 VCCIN_101 V23
2
BP39 VCCIN_37 VCCIN_102 V25
BR10 VCCIN_38 VCCIN_103 V27
BR40 VCCIN_39 VCCIN_104 V29 SOC_SVID_ALERT# 1 @ 2
VCCIN_40 VCCIN_105 VR_SVID_ALERT# <88>
BT12 V31 RC4071 0_0201_5%
BT39 VCCIN_41 VCCIN_106 V33
BU10 VCCIN_42 VCCIN_107 W22
BU40 VCCIN_43 VCCIN_108 W24 R-short 0831
BV12 VCCIN_44 VCCIN_109 W28
BY12 VCCIN_45 VCCIN_110 W32 +1.05V_VCCST
VCCIN_46 VCCIN_111
Trace Length Match<25 mils
CA10 Must be routed as differential pair to VR
CB12 VCCIN_47 R38
D24 VCCIN_48 VCCIN_SENSE R37 VCC_SENSE_VCCIN <88>
VCCIN_49 VSSIN_SENSE VSS_SENSE_VCCIN <88>
1
D26
D29 VCCIN_50
VCCIN_51 VIDSOUT
M12 SOC_SVID_DAT
SOC_SVID_CLK
SVID CLK RC238
D30 M11 @ 43_0201_5%
D33 VCCIN_52 VIDSCK P12 SOC_SVID_ALERT#
D35 VCCIN_53 VIDALERT#
2
B E24 VCCIN_54 B
E26 VCCIN_55
E27 VCCIN_56 SOC_SVID_CLK 1 @ 2
VCCIN_57 VR_SVID_CLK <88>
E29 RC4070 0_0201_5%
E30 VCCIN_58
E32 VCCIN_59
E33 VCCIN_60 R-short 0831 1
G2 VCCIN_61 CC32 @RF@
G24 VCCIN_62 33P_0201_50V8J
G26 VCCIN_63 2
G30 VCCIN_64
VCCIN_65
@ TGL-U_BGA1449
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P014 - TGL-U(9/13)CPU PWR,SVID
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 14 of 100
5 4 3 2 1
5 4 3 2 1
D D
+1.2V_DDR
16x 10uF 0402 +VCCSTG_FUSE
1
CC960
1U_0201_6.3V6M
2
2x 47uF 0603 +1.2V_DDR RC309
1 @ 2
0_0402_1%
@
CC129
1
1U_0201_6.3V6M
CC130
1U_0201_6.3V6M
2
1 1 1 1 1 1 1 1 1 1 1 1
1U_0201_6.3V6K
CC33
1U_0201_6.3V6K
CC34
1U_0201_6.3V6K
CC35
1U_0201_6.3V6K
CC36
1U_0201_6.3V6K
CC37
1U_0201_6.3V6K
CC38
1U_0201_6.3V6K
CC39
1U_0201_6.3V6K
CC40
1U_0201_6.3V6K
CC41
1U_0201_6.3V6K
CC42
47U_0603_6.3V6M
CC61
47U_0603_6.3V6M
CC62
UC1O
REV 1.6 2 @
AF9
2 2 2 2 2 2 2 2 2 2 2 2 AA39 VCCSTG_OUT_1 AF12
AB40 VDD2_1 VCCSTG_1 AD12
AC39 VDD2_2 VCCSTG_2
AD40 VDD2_3 AN10
AD51 VDD2_4 VCCSTG_OUT_2 AM9
+1.2V_DDR AD52 VDD2_5 VCCSTG_OUT_3 AG10 +VCCIO_OUT
AE39 VDD2_6 VCCSTG_OUT_4
AF40 VDD2_7 V15 +VCCSTG_OUT_LGC +1.05V_VCCSTG
AG39 VDD2_8 VCCIO_OUT
AH40 VDD2_9 M9 1 @ 2
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VDD2_10 VCCSTG_OUT_LGC Output
10U_0402_6.3V6M
CC51
10U_0402_6.3V6M
CC52
10U_0402_6.3V6M
CC53
10U_0402_6.3V6M
CC54
10U_0402_6.3V6M
CC55
10U_0402_6.3V6M
CC56
10U_0402_6.3V6M
CC57
10U_0402_6.3V6M
CC58
10U_0402_6.3V6M
CC59
10U_0402_6.3V6M
CC60
10U_0402_6.3V6M
CC954
10U_0402_6.3V6M
CC955
10U_0402_6.3V6M
CC956
10U_0402_6.3V6M
CC957
10U_0402_6.3V6M
CC958
10U_0402_6.3V6M
CC959
AJ39 RC240 0_0402_1%
AK40 VDD2_11 BT2
AK51 VDD2_12 VCCST_1 BT1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 AK52 VDD2_13 VCCST_2 BT4 R-short 0831
AL39 VDD2_14 VCCST_3
AM40 VDD2_15 BP2 +1.05V_VCCST
C AN39 VDD2_16 VCCSTG_3 BP1 C
AP40 VDD2_17 VCCSTG_4 BP4
VDD2_18 VCCSTG_5 Input
AR39
AT52 VDD2_19
VDD2_20 1 1
1U_0201_6.3V6M
CC49
1U_0201_6.3V6M
CC50
AU40 +VCCSTG_CPU
AW40 VDD2_21
AW51 VDD2_22
VDD2_23 Input 2 2
AW52 @
BD51 VDD2_24
VDD2_25 1 1
1U_0201_6.3V6M
CC63
1U_0201_6.3V6M
CC64
BD52
BK51 VDD2_26
BK52 VDD2_27
+1.2V_DDR BV51 VDD2_28 2 @ 2
EMC CAPS - PLACE <4MM FROM SOC VDDQ, WITH EACH PAIR <12MM APART BV52 VDD2_29
CA40 VDD2_30
CC40 VDD2_31
CC49 VDD2_32
1 1 1 1 1 1 1 1 VDD2_33
12P_0201_25V8J
CC86 RF@
2.2P_0201_25V8C
CC87 RF@
12P_0201_25V8J
CC88 RF@
2.2P_0201_25V8C
CC89 RF@
12P_0201_25V8J
CC90 RF@
2.2P_0201_25V8C
CC91 RF@
12P_0201_25V8J
CC92 RF@
2.2P_0201_25V8C
CC93 RF@
CC50
CE40 VDD2_34
CG40 VDD2_35
2 2 2 2 2 2 2 2 CH39 VDD2_36
CJ40 VDD2_37
CL40 VDD2_38
CN40 VDD2_39
CP47 VDD2_40
CR40 VDD2_41
D50 VDD2_42
E51 VDD2_43
F49 VDD2_44
T51 VDD2_45
T52 VDD2_46
VDD2_47
@ TGL-U_BGA1449
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P015 - TGL-U(10/13)CPU PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 15 of 100
5 4 3 2 1
5 4 3 2 1
+VCCIN_AUX +VCCIN_AUX
1
+3VLP RC782 2 2 2 2 2 2
100_0402_1%
RF@
CC936
RF@
CC937
RF@
CC938
RF@
CC939
RF@
CC940
RF@
CC941
2
1
1 1 1 1 1 1
RC783
10P_0201_25V8
10P_0201_25V8
10P_0201_25V8
10P_0201_25V8
10P_0201_25V8
10P_0201_25V8
100K_0201_5%
6
2
L2N7002DW1T1G_SC88-6
QC5A
D D
2 +VCCPRIM_1P8 +1.8V_PRIM
L2N7002DW1T1G_SC88-6
3
+3VALW_PCH
1
RC4164 1 2 0_0603_5%
QC5B
@
<58,87,91> 1.8V_PRIM_PG
5 RF Request
R-short 0831
1 1 1
4
1
1U_0201_6.3V6M
CC135
0.1U_0201_10V6K
CC136
0.01U_0201_10V6K
CC137
1M_0201_1%
RC738
+VCCIN_AUX +VCCPRIM_1P8
2 2 2 @
EVT1_23 UC1N
2
REV 1.6 1
1U_0201_6.3V6M
CC134
1.8V/32A AB12 CY18 1.8V/1.3A
AC10 VCCIN_AUX_1 VCCPRIM_1P8_1 CY20
AE10 VCCIN_AUX_2 VCCPRIM_1P8_2 CY24
VCCIN_AUX_3 VCCPRIM_1P8_3 2 Place near DA35 , DC28 , DD30
AK2 CY26
AR10 VCCIN_AUX_4 VCCPRIM_1P8_4 DA18 @
AT12 VCCIN_AUX_5 VCCPRIM_1P8_5 DA20 +VCCA_CLKLDO_1P8 +1.8V_PRIM
AU10 VCCIN_AUX_6 VCCPRIM_1P8_6 DA22 LC1 @
AW10 VCCIN_AUX_7 VCCPRIM_1P8_7 DA24 0.68UH_UHP252012NF-R68M_3A_20%
BV1 VCCIN_AUX_8 VCCPRIM_1P8_8 DA26 1 2
BV39 VCCIN_AUX_9 VCCPRIM_1P8_9 DC18 1 @ 2
BW40 VCCIN_AUX_10 VCCPRIM_1P8_10 DC20 RC4068 0_0603_5% +VCCRTCEXT +VCCLDOSTD_OUT_0P85
VCCIN_AUX_11 VCCPRIM_1P8_11
1
BY39 DC22
CC1 VCCIN_AUX_12 VCCPRIM_1P8_12 DC24 RC243
CD12 VCCIN_AUX_13 VCCPRIM_1P8_13 DC26 +3VALW_PCH 0_0402_1%
R-short 0831
CF10 VCCIN_AUX_14 VCCPRIM_1P8_14 DD20
VCCIN_AUX_15 VCCPRIM_1P8_15 1 1
0.1U_0201_10V6K
CC138
2.2U_0402_6.3V6K
CC139
CG12 DD22
2
CH10 VCCIN_AUX_16 VCCPRIM_1P8_16 DV22
VCCIN_AUX_17 VCCPRIM_1P8_17 +VCCA_CLKLDO_1P8_C
CJ1 1
VCCIN_AUX_18 2 2
47U_0603_6.3V6M
CC97
CJ12 DA35 3.3V/0.202A
C CK10 VCCIN_AUX_19 VCCPRIM_3P3_1 DC28 C
CL12 VCCIN_AUX_20 VCCPRIM_3P3_2 DC30
CM10 VCCIN_AUX_21 VCCPRIM_3P3_3 DD30 +VCCRTCEXT 2
CP1 VCCIN_AUX_22 VCCPRIM_3P3_4 +VCCLDOSTD_OUT_0P85
CP10 VCCIN_AUX_23 DV34
CR12 VCCIN_AUX_24 DCPRTC
VCCIN_AUX_25 Place near DV34 Place near DV46
+V1.05A_BYPASS +VNN_BYPASS CT10 DV46
CU12 VCCIN_AUX_26 VCCLDOSTD_0P85
CY1 VCCIN_AUX_27 DV16 +VCCDPHY_1P24
AK1 VCCIN_AUX_28 VCCA_CLKLDO_1P8_1 DC15
X01_5 VCCIN_AUX_29 VCCA_CLKLDO_1P8_2
1
1
100K_0201_5%
RC257
100K_0201_5%
RC4077
4.7U_0402_6.3V6M
CC94
1U_0201_6.3V6M
CC95
DD18 BR3
VCC_VNNEXT_1P05_2 VCC1P05_OUT_FET +VCC1.05_OUT_FET
BR4 Place near DC35
DA15 VCC1P05_OUT_FET BT5 1 @ 2
DA17 VCC_V1P05EXT_1P05_1 VCC1P05_OUT_FET RC246 0_0402_1% 2 2
VCC_V1P05EXT_1P05_2 1 1
1
0.1U_0201_10V6K
CC98
1U_0201_6.3V6M
CC99
100K_0201_5%
R6227
DA31
VRALERT#_R VCCPRIM_1P05_1 +VCC1.05_OUT_PCH
RC247 1 @ 2 0_0201_5% VRALERT# DB39 DC33
TP187 1 TP@ PAD~D VNN_CTRL DV12 GPP_B2/VRALERT# VCCPRIM_1P05_2 DC31 R-short 0831
TP188 1 TP@ PAD~D V1P05_CTRL DT12 GPP_F22/VNN_CTRL VCCPRIM_1P05_3 +3VALW_DSW 2 2 @
GPP_F23/V1P05_CTRL DC35
2
RC4073 1 @ 2 0_0201_5% AUX_VID0_R DB37 VCCRTC DD37
<78,91> AUX_VID0 GPP_B0/CORE_VID0 VCCDSW_3P3 Place near DV28 Place near DD38
RC249 1 @ 2 0_0201_5% AUX_VID1_R DB38 DA28
<78,91> AUX_VID1 GPP_B1/CORE_VID1 VCCPGPPR ?
CY31
?
R-short 0831 VCCPRIM_3P3_5 CY33 +3VALW_PCH
VCCPRIM_3P3_6 CV39
VCCPRIM_1P8_18 +VCCPRIM_1P8
+3VALW_PCH
AP12 PAD~D 1 +VCCPGPPR_3P3_1P8 RC251 +3VALW_PCH
RC311 1 @ 2 100K_0201_5% AUX_VID0_R RSVD_1 TP192 TP@ 0_0402_1%
RC312 1 @ 2 100K_0201_5% AUX_VID1_R @ TGL-U_BGA1449 Audio Power 1 @ 2
B B
1
CC100 R-short 0831
0.1U_0201_10V6K
2
RC258
100K_0201_5%
2
DC5
VRALERT#_R 1 2
H_PROCHOT# <7,58,82,84,88>
RB751S-40_SOD523-2
+3VALW_DSW +3VALW_PCH
R-short 0831
1 @ 2
1 RC4165 0_0402_1%
@
CC141
0.1U_0201_10V6K
2
Place near DD37
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P016 - TGL-U(11/13)PCH Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 16 of 100
5 4 3 2 1
5 4 3 2 1
@ TGL-U_BGA1449
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P017 - TGL-U(12/13)GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 17 of 100
5 4 3 2 1
5 4 3 2 1
UC1S
D REV 1.6 D
DF53 C53
RSVD_19 RSVD_23 T35
DF52 RSVD_24 E53
RSVD_20 RSVD_25 CF39
1 PCH_IST_TP_1 DT52 RSVD_26 U35
PAD~D TP@ TP30 1 PCH_IST_TP_0 DU53 PCH_IST_TP_1 RSVD_27 F53
PAD~D TP@ TP31 PCH_IST_TP_0 RSVD_28 B53
DF50 RSVD_29 AP9
DF49 RSVD_21 RSVD_30 A52
RSVD_22 RSVD_31
1 RSVD_TP_25 CY30 BF12 RSVD_TP_28 1
TP33TP@ PAD~D
PAD~D TP@ TP32 1 RSVD_TP_26 CY15 RSVD_TP_25 RSVD_TP_28 V21 RSVD_TP_29 1
+1.8V_PRIM_CY15 (ES1 solution) RSVD_TP_26 RSVD_TP_29 RSVD_TP_30 TP35TP@ PAD~D
PAD~DTP@TP194 W20 1
RSVD_TP_27 RSVD_TP_30 RSVD_TP_31 TP36TP@ PAD~D
1 D4 U37 1
PAD~D TP@ TP37 RSVD_TP_27 RSVD_TP_31 RSVD_TP_32 TP38TP@ PAD~D
CD39 1
IST_TP_1 RSVD_TP_32 RSVD_TP_33 TP39TP@ PAD~D
1 A6 U21 1
TP41TP@ PAD~D
PAD~D TP@ TP40 1 IST_TP_0 A4 IST_TP_1 RSVD_TP_33 CB39
PAD~D TP@ TP42 IST_TP_0 RSVD_32 BB12 RSVD_TP_34 1
RSVD_TP_34 RSVD_TP_35 TP43TP@ PAD~D
W37 1
RSVD_TP_35 RSVD_TP_36 TP44TP@ PAD~D
AY12 1
RSVD_TP_36 RSVD_TP_37 TP45TP@ PAD~D
W38 1
RSVD_TP_37 RSVD_TP_38 TP46TP@ PAD~D
U38 1
RSVD_TP_38 RSVD_TP_39 TP47TP@ PAD~D
CY28 1
RSVD_TP_39 TP193 PAD~D
TP@
+1.8V_PRIM_CY28 (ES1 solution)
@ TGL-U_BGA1449
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P018 - TGL-U(13/13)RSVD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 18 of 100
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
Reserve
C C
B B
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/09/08 Deciphered Date 2013/10/28 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
(RSVD)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 19 of 101
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
C C
B
Reserve B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
(RSVD)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 20 of 101
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
Reserve
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
(RSVD)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 21 of 101
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
Reserve
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
(RSVD)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 22 of 101
5 4 3 2 1
5 4 3 2 1
Non-Interleaved Memory
138 20
<8> DDR_M0_CLK1 DDR_M0_CLK#1 CK1(T) DQ2 DDR_M0_D59
<8> DDR_M0_CLK#1 140 21
CK1#(C) DQ3 4 DDR_M0_D60
DDR_M0_CKE0 109 DQ4 3 DDR_M0_D62
BOT: DIMM1(JDIMM2 CONN) Non-ECC DIMM <8> DDR_M0_D[0..15]
<8>
<8>
DDR_M0_CKE0
DDR_M0_CKE1
DDR_M0_CKE1 110 CKE0
CKE1
DQ5
DQ6
DQ7
16
17
DDR_M0_D61
DDR_M0_D57
DDR_M0_CS#0 149 13 DDR_M0_DQS7
<8> DDR_M0_CS#0 DDR_M0_CS#1 S0# DQS0(T) DDR_M0_DQS#7 DDR_M0_DQS7 <8>
157 11
+3VS +3VS +3VS <8> DDR_M0_D[16..31] <8> DDR_M0_CS#1 S1# DQS0#(C) DDR_M0_DQS#7 <8>
162
165 S2#/C0 28 DDR_M0_D51
<8> DDR_M0_D[32..47] ? S3#/C1 DQ8
DQ9
29 DDR_M0_D53
1
1
D DDR_M0_ODT0 155 41 DDR_M0_D49 D
<8> DDR_M0_D[48..63] <8> DDR_M0_ODT0 DDR_M0_ODT1 ODT0 DQ10 DDR_M0_D54
RD1 RD2 RD3 161 42
<8> DDR_M0_ODT1 ODT1 DQ11 DDR_M0_D48
@ 0_0402_5% @ 0_0402_5% @ 0_0402_5% 24
JDIMM2B DDR_M0_BG0 115 DQ12 25 DDR_M0_D52
<8> DDR_M0_BG0 DDR_M0_BG1 BG0 DQ13 DDR_M0_D55
RVS 113 38
<8> DDR_M0_BG1
2
2
SA0_CHA_DIM1 SA1_CHA_DIM1 SA2_CHA_DIM1 111 141 DDR_M0_BA0 150 BG1 DQ14 37 DDR_M0_D50
+1.2V_DDR 112 VDD1 VDD11 142
+1.2V_DDR <8> DDR_M0_BA0 DDR_M0_BA1 145 BA0 DQ15 34 DDR_M0_DQS6
VDD2 VDD12 <8> DDR_M0_BA1 BA1 DQS1(T) DDR_M0_DQS#6 DDR_M0_DQS6 <8>
117 147 32
VDD3 VDD13 DQS1#(C) DDR_M0_DQS#6 <8>
1
1
118 148 DDR_M0_MA0 144
VDD4 VDD14 <8> DDR_M0_MA0 DDR_M0_MA1 A0 DDR_M0_D45
RD4 RD5 RD6 123 153 133 50
VDD5 VDD15 <8> DDR_M0_MA1 DDR_M0_MA2 A1 DQ16 DDR_M0_D47
0_0402_5% 0_0402_5% 0_0402_5% 124 154 132 49
VDD6 VDD16 <8> DDR_M0_MA2 DDR_M0_MA3 A2 DQ17 DDR_M0_D41
129 159 131 62
VDD7 VDD17 <8> DDR_M0_MA3 DDR_M0_MA4 A3 DQ18 DDR_M0_D40
130 160 128 63
<8> DDR_M0_MA4
2
2
135 VDD8 VDD18 163 DDR_M0_MA5 126 A4 DQ19 46 DDR_M0_D44
+3VS VDD9 VDD19 <8> DDR_M0_MA5 DDR_M0_MA6 A5 DQ20 DDR_M0_D46
136 127 45
VDD10 <8> DDR_M0_MA6 DDR_M0_MA7 A6 DQ21 DDR_M0_D42
122 58
<8> DDR_M0_MA7 DDR_M0_MA8 A7 DQ22 DDR_M0_D43
255 258 125 59
VDDSPD VTT +0.6V_DDR_VTT <8> DDR_M0_MA8 DDR_M0_MA9 121 A8 DQ23 55 DDR_M0_DQS5
PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM <8> DDR_M0_MA9 DDR_M0_MA10 A9 DQS2(T) DDR_M0_DQS#5 DDR_M0_DQS5 <8>
0.1U_0201_10V6K
2.2U_0201_6.3V6M
164 257 146 53
+0.6V_DDRA_VREFCA VREFCA VPP1 259
+2.5V_MEM <8> DDR_M0_MA10 DDR_M0_MA11 120 A10_AP DQS2#(C) DDR_M0_DQS#5 <8>
2 2 VPP2 <8> DDR_M0_MA11 A11
DDR_M0_MA12 119 70 DDR_M0_D36
<8> DDR_M0_MA12 DDR_M0_MA13 A12 DQ24 DDR_M0_D38
CD2
CD1
1 99 158 71
VSS VSS <8> DDR_M0_MA13 DDR_M0_MA14_WE# A13 DQ25 DDR_M0_D33
2 102 151 83
SPD ADDRESS FOR CHANNEL A : 1 1 5 VSS
VSS
VSS
VSS
103
<8>
<8>
DDR_M0_MA14_WE#
DDR_M0_MA15_CAS#
DDR_M0_MA15_CAS#
DDR_M0_MA16_RAS#
156 A14_WE#
A15_CAS#
DQ26
DQ27
84 DDR_M0_D35
DDR_M0_D39
6 106 152 66
VSS VSS <8> DDR_M0_MA16_RAS# A16_RAS# DQ28 DDR_M0_D37
9 107 67
10 VSS VSS 167 DDR_M0_ACT# 114 DQ29 79 DDR_M0_D34
SA0 = 0; SA1 = 0; SA2 = 0. PLACE NEAR TO PIN 14
15
VSS
VSS
VSS
VSS
168
171
+1.2V_DDR <8> DDR_M0_ACT#
DDR_M0_PAR 143
ACT# DQ30
DQ31
80
76
DDR_M0_D32
DDR_M0_DQS4
VSS VSS <8> DDR_M0_PAR DDR_M0_ALERT# PARITY DQS3(T) DDR_M0_DQS#4 DDR_M0_DQS4 <8>
18 172 116 74
VSS VSS <8> DDR_M0_ALERT# DIMM1_M0_EVENT# ALERT# DQS3#(C) DDR_M0_DQS#4 <8>
19 175 RD7 2 1 134
22 VSS VSS 176 240_0402_1% DDR_DRAMRST#_R 108 EVENT# 174 DDR_M0_D11
VSS VSS <8,24> DDR_DRAMRST#_R RESET# DQ32 DDR_M0_D10
23 180 173
26 VSS VSS 181 DQ33 187 DDR_M0_D14
27 VSS VSS 184 PCH_SMBDATA 254 DQ34 186 DDR_M0_D8
VSS VSS <9,24> PCH_SMBDATA PCH_SMBCLK SDA DQ35 DDR_M0_D12
30 185 253 170
VSS VSS <9,24> PCH_SMBCLK SCL DQ36 DDR_M0_D9
31 188 169
35 VSS VSS 189 SA2_CHA_DIM1 166 DQ37 183 DDR_M0_D15
36 VSS VSS 192 To SOC SA1_CHA_DIM1 260 SA2 DQ38 182 DDR_M0_D13
39 VSS VSS 193 SA0_CHA_DIM1 256 SA1 DQ39 179 DDR_M0_DQS1
VSS VSS SA0 DQS4(T) DDR_M0_DQS#1 DDR_M0_DQS1 <8>
40 196 177
VSS VSS DQS4#(C) DDR_M0_DQS#1 <8>
43 197
C VSS VSS DDR_M0_D5 C
44 201 92 195
47 VSS VSS 202 91 CB0_NC DQ40 194 DDR_M0_D7
48 VSS VSS 205 101 CB1_NC DQ41 207 DDR_M0_D0
51 VSS VSS 206 105 CB2_NC DQ42 208 DDR_M0_D2
+1.2V_DDR 52 VSS VSS 209 88 CB3_NC DQ43 191 DDR_M0_D6
56 VSS VSS 210 +1.2V_DDR 87 CB4_NC DQ44 190 DDR_M0_D4
57 VSS VSS 213 100 CB5_NC DQ45 203 DDR_M0_D3
60 VSS VSS 214 104 CB6_NC DQ46 204 DDR_M0_D1
DIMM Side CPU Side 61
64
VSS
VSS
VSS
VSS
VSS
VSS
217
218
RD25 2
RD26 2
@
@
1 240_0402_1%
1 240_0402_1%
97
95
CB7_NC
DQS8(T)
DQS8#(C)
DQ47
DQS5(T)
DQS5#(C)
200
198
DDR_M0_DQS0
DDR_M0_DQS#0 DDR_M0_DQS0
DDR_M0_DQS#0
<8>
<8>
2
65 222
RD9 +0.6V_DDRA_VREFCA +V_DDR_REFA_R 68 VSS VSS 223 216 DDR_M0_D31
69 VSS VSS 226 12 DQ48 215 DDR_M0_D24
1K_0402_1% +1.2V_DDR
72 VSS VSS 227 33 DM0#/DBI0# DQ49 228 DDR_M0_D26
73 VSS VSS 230 54 DM1#/DBI1# DQ50 229 DDR_M0_D30
1
CD5 89 244 2
RD11 0.022U_0201_25V6K 90 VSS VSS 247 CD3
2 93 VSS VSS 248 0.1U_0201_10V6K
1K_0402_1%
94 VSS VSS 251 @ESD@ 237 DDR_M0_D17
VSS VSS DQ56
2
DEREN_40-42271-26001RHF
CONN@
+1.2V_DDR
B
Decopling Cap._Channel A Part Number:SP07001JH00
B
@EMI@
@EMI@
@EMI@
@EMI@
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
Layout Note: Layout Note: Layout Note: 2 2 2 2
Place near JDIMM2.257,259 Place near JDIMM2.258 PLACE THE CAP near JDIMM2. 164
C107 place near JDIMM2
1 1 1 1
CD43
CD44
CD45
CD46
+0.6V_DDR_VTT
+2.5V_MEM +0.6V_DDR_VTT +0.6V_DDRA_VREFCA
2.2uF *1
10uF *1 10uF *1+1uF *2 0.1uF *1
1uF *1
10P_0201_25V8
C107
@RF@
1U_0201_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1
CD24 @ CD25
2
CD47
CD48
CD49
CD51
CD52
0.1U_0201_10V6K 2.2U_0201_6.3V6M
1 1
2 2 2 2 2
EMC CAPS-PLACE
< 4mm from SO-DIMM VDDQ
with each pair < 12mm Apart
12pF* 5 (EMI@)
2.2pF* 5 (EMI@)
1 1 1 1 1 1 1 1 1 1
follow RVP 1p0
EMI@ CD3853
EMI@ CD3854
EMI@ CD3851
EMI@ CD3852
EMI@ CD3845
EMI@ CD3846
EMI@ CD3847
EMI@ CD3848
EMI@ CD3849
EMI@ CD3850
12P_0201_50V8J
12P_0201_50V8J
12P_0201_50V8J
12P_0201_50V8J
12P_0201_50V8J
2.2P_0201_50V8C
2.2P_0201_50V8C
2.2P_0201_50V8C
2.2P_0201_50V8C
2.2P_0201_50V8C
A
10uF*8 A
+1.2V_DDR 1uF*8 +1.2V_DDR 2 2 2 2 2 2 2 2 2 2
@330uF*1
1
POP
EMI@
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 @
+ CD3856
UNPOP
CD57
CD58
CD59
CD60
CD61
CD62
CD63
CD64
CD65
CD66
CD67
CD68
CD69
CD70
CD71
CD72
330U_D2_2V_Y
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 @EMI@\@ESD@\@RF@\CONN@\@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR4_CHM0: DIMM0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 23 of 101
5 4 3 2 1
5 4 3 2 1
1
CKE1 DQ6 17 DDR_M1_D44
RD13 RD14 RD15 DDR_M1_CS#0 149 DQ7 13 DDR_M1_DQS5
<8> DDR_M1_D[48..63] <8> DDR_M1_CS#0 DDR_M1_CS#1 S0# DQS0(T) DDR_M1_DQS#5 DDR_M1_DQS5 <8>
@ 0_0201_5% 0_0201_5% @ 0_0201_5% 157 11
<8> DDR_M1_CS#1 S1# DQS0#(C) DDR_M1_DQS#5 <8>
JDIMM1B 162
D STD 165 S2#/C0 28 DDR_M1_D34 D
?
2
2
SA0_CHB_DIM2 SA1_CHB_DIM2 SA2_CHB_DIM2 111 141 S3#/C1 DQ8 29 DDR_M1_D36
+1.2V_DDR 112 VDD1 VDD11 142
+1.2V_DDR DDR_M1_ODT0 155 DQ9 41 DDR_M1_D32
VDD2 VDD12 <8> DDR_M1_ODT0 DDR_M1_ODT1 ODT0 DQ10 DDR_M1_D37
117 147 161 42
VDD3 VDD13 <8> DDR_M1_ODT1 ODT1 DQ11
1
1
118 148 24 DDR_M1_D35
RD16 RD17 RD18 123 VDD4 VDD14 153 DDR_M1_BG0 115 DQ12 25 DDR_M1_D33
VDD5 VDD15 <8> DDR_M1_BG0 DDR_M1_BG1 BG0 DQ13 DDR_M1_D38
0_0201_5% @ 0_0201_5% 0_0201_5% 124 154 113 38
VDD6 VDD16 <8> DDR_M1_BG1 DDR_M1_BA0 BG1 DQ14 DDR_M1_D39
129 159 150 37
VDD7 VDD17 <8> DDR_M1_BA0 DDR_M1_BA1 BA0 DQ15 DDR_M1_DQS4
130 160 145 34
<8> DDR_M1_BA1 DDR_M1_DQS4 <8>
2
2
135 VDD8 VDD18 163 BA1 DQS1(T) 32 DDR_M1_DQS#4
+3VS VDD9 VDD19 DDR_M1_MA0 DQS1#(C) DDR_M1_DQS#4 <8>
136 144
VDD10 <8> DDR_M1_MA0 DDR_M1_MA1 A0 DDR_M1_D58
133 50
<8> DDR_M1_MA1 DDR_M1_MA2 A1 DQ16 DDR_M1_D62
255 258 132 49
VDDSPD VTT +0.6V_DDR_VTT <8> DDR_M1_MA2 DDR_M1_MA3 131 A2 DQ17 62 DDR_M1_D60
<8> DDR_M1_MA3 DDR_M1_MA4 A3 DQ18 DDR_M1_D57
0.1U_0201_10V6K
2.2U_0201_6.3V6M
164 257 128 63
+0.6V_DDRB_VREFCA VREFCA VPP1 259
+2.5V_MEM <8> DDR_M1_MA4 DDR_M1_MA5 126 A4 DQ19 46 DDR_M1_D59
PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM 2 2 VPP2 <8> DDR_M1_MA5 DDR_M1_MA6 127 A5 DQ20 45 DDR_M1_D61
<8> DDR_M1_MA6 DDR_M1_MA7 A6 DQ21 DDR_M1_D63
CD7
CD8
1 99 122 58
VSS VSS <8> DDR_M1_MA7 DDR_M1_MA8 A7 DQ22 DDR_M1_D56
2 102 125 59
1 1 VSS VSS <8> DDR_M1_MA8 DDR_M1_MA9 A8 DQ23 DDR_M1_DQS7
5 103 121 55
SPD ADDRESS FOR CHANNEL B : 6
9
VSS
VSS
VSS
VSS
106
107
<8>
<8>
DDR_M1_MA9
DDR_M1_MA10
DDR_M1_MA10
DDR_M1_MA11
146
120
A9
A10_AP
DQS2(T)
DQS2#(C)
53 DDR_M1_DQS#7 DDR_M1_DQS7
DDR_M1_DQS#7
<8>
<8>
VSS VSS <8> DDR_M1_MA11 DDR_M1_MA12 A11 DDR_M1_D54
10 167 119 70
<8> DDR_M1_MA12
PLACE NEAR TO PIN 14 VSS VSS 168 DDR_M1_MA13 158 A12 DQ24 71 DDR_M1_D49
SA0 = 0; SA1 = 1; SA2 = 0. 15
18
VSS
VSS
VSS
VSS
171
172
<8>
<8>
DDR_M1_MA13
DDR_M1_MA14_WE#
DDR_M1_MA14_WE#
DDR_M1_MA15_CAS#
151
156
A13
A14_WE#
DQ25
DQ26
83
84
DDR_M1_D52
DDR_M1_D50
VSS VSS <8> DDR_M1_MA15_CAS# DDR_M1_MA16_RAS# A15_CAS# DQ27 DDR_M1_D55
19 175 152 66
VSS VSS <8> DDR_M1_MA16_RAS# A16_RAS# DQ28 DDR_M1_D51
22 176 67
23 VSS VSS 180 DDR_M1_ACT# 114 DQ29 79 DDR_M1_D53
VSS VSS +1.2V_DDR <8> DDR_M1_ACT# ACT# DQ30 DDR_M1_D48
26 181 80
27 VSS VSS 184 DDR_M1_PAR 143 DQ31 76 DDR_M1_DQS6
VSS VSS <8> DDR_M1_PAR DDR_M1_ALERT# PARITY DQS3(T) DDR_M1_DQS#6 DDR_M1_DQS6 <8>
30 185 116 74
VSS VSS <8> DDR_M1_ALERT# DIMM2_M2_EVENT# ALERT# DQS3#(C) DDR_M1_DQS#6 <8>
31 188 RD19 2 1 134
35 VSS VSS 189 240_0402_1% DDR_DRAMRST#_R 108 EVENT# 174 DDR_M1_D8
VSS VSS <8,23> DDR_DRAMRST#_R RESET# DQ32 DDR_M1_D14
36 192 173
39 VSS VSS 193 DQ33 187 DDR_M1_D10
40 VSS VSS 196 PCH_SMBDATA 254 DQ34 186 DDR_M1_D12
VSS VSS <9,23> PCH_SMBDATA PCH_SMBCLK SDA DQ35 DDR_M1_D15
43 197 253 170
VSS VSS <9,23> PCH_SMBCLK SCL DQ36 DDR_M1_D13
44 201 169
47 VSS VSS 202 SA2_CHB_DIM2 166 DQ37 183 DDR_M1_D9
48 VSS VSS 205
To SOC SA1_CHB_DIM2 260 SA2 DQ38 182 DDR_M1_D11
+1.2V_DDR 51 VSS VSS 206 SA0_CHB_DIM2 256 SA1 DQ39 179 DDR_M1_DQS1
C VSS VSS SA0 DQS4(T) DDR_M1_DQS#1 DDR_M1_DQS1 <8> C
52 209 177
VSS VSS DQS4#(C) DDR_M1_DQS#1 <8>
56 210
57 VSS VSS 213 92 195 DDR_M1_D7
60 VSS VSS 214 91 CB0_NC DQ40 194 DDR_M1_D6
61 VSS VSS 217 101 CB1_NC DQ41 207 DDR_M1_D2
64 VSS VSS 218 105 CB2_NC DQ42 208 DDR_M1_D3
65 VSS VSS 222 88 CB3_NC DQ43 191 DDR_M1_D0
68 VSS VSS 223 +1.2V_DDR 87 CB4_NC DQ44 190 DDR_M1_D5
DIMM Side CPU Side
69 VSS VSS 226 100 CB5_NC DQ45 203 DDR_M1_D1
2
@ESD@
2
DEREN_40-42261-26001RHF
Part Number:SP07001HY00
Part Value:S SOCKET LOTES ADDR0207-P001A 260P DDR4
Layout Note:
Layout Note: Layout Note: PLACE THE CAP WITHIN 200 MILS
Place near JDIMM1.257,259 Place near JDIMM1.258 FROM THE JDIMM1 08/30
Update Table 4-26 for DDR4 SO-DIMM Decoupling Caps
572907_ICL_UY_PDG_Rev0p7 Page.99
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1
10U_0402_6.3V6M
CD55 @ CD56
CD14
CD16
CD18
CD20
CD21
0.1U_0201_10V6K 2.2U_0201_6.3V6M
1 1
2 2 2 2 2
Layout Note:
10P_0201_25V8
C108
@RF@
2
follow RVP 1p0
A A
10uF*8
+1.2V_DDR 1uF*8 +1.2V_DDR
@330uF*1
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CD26
CD27
CD28
CD29
CD30
CD31
CD32
CD33
CD34
CD35
CD36
CD37
CD38
CD39
CD40
CD41
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR4_CHM1: DIMM1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 24 of 101
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
C C
B
Reserve B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
(RSVD)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 25 of 101
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
C C
B
Reserve B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
(RSVD)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 26 of 101
5 4 3 2 1
1 2 3 4 5
A A
B B
C C
D D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NV(1/5)-PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 27 of 101
1 2 3 4 5
1 2 3 4 5
A A
B B
C C
D D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NV(2/5)-IFP_ABCDEF_DAC_XTAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 28 of 101
1 2 3 4 5
1 2 3 4 5
A A
B B
C C
D D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NV(3/5)-POWER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 29 of 101
1 2 3 4 5
1 2 3 4 5
A A
B B
C C
D D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NV(4/5)-GPIO/Strap
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 30 of 101
1 2 3 4 5
1 2 3 4 5
A A
B B
C C
D D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NV(5/5)-MEMORY FBA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 31 of 101
1 2 3 4 5
5 4 3 2 1
D D
Reserve
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 32 of 101
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SMbus Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 33 of 101
5 4 3 2 1
5 4 3 2 1
D D
Reserve
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SMbus Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 34 of 101
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N17S_GDDR5_A
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 35 of 101
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N17S_GDDR5_B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 36 of 101
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DGPU_DC/DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 37 of 101
5 4 3 2 1
5 4 3 2 1
1
+DCBAT_LCD
60 mils DMIC_CLK_EDP
I2CTCH@ --> I2C Touch Screen 1 2
41 1 2 F1
G1 2 3
42
G2 3 4
1 2 DMIC_DATA_EDP
USBTCH@ --> USB Touch Screen 1A_65V_T0603FF1000TM
4 5 +LCDVDD_LCD
10P_0201_25V8
C105
@RF@
1.5A_24V_SMD1812P150TF-24 1 1 +TS_VDD
5 6
1
R96 close JEDP! @ 08/15 C5 C6 +MIC_VCC +3VS_CAM
6 7 60 mils
2
@
F5 USBTCH@ +3VS_CAM
7 8
0.1U_0402_50V7K
1000P_0402_50V7K
RF@ 1 2
+5VS
2
8 9 2 2 2 @ 1
9 10 1 1 C105 place near JEDP1
1
LCD_TST_C
0.1U_0402_16V7K
10P_0402_50V8J
1A_65V_T0603FF1000TM R83 0_0402_5% 1
10 11 DBC_PANEL_EN_R
C7
C8
C9
1 1 @RF@
D 11 12 EDP_HPD F6 I2CTCH@ C102 D
2
12 13 EDP_HPD <6> 2 2 1 2 10P_0201_25V8
ED4 +3VS C39 @ C36
1
13 14 LCD_CBL_DET# CEST523NC5VB_SOT-523-3 2
14 15 LCD_CBL_DET# <10> 1U_0201_6V3M 0.1U_0402_10V7K
EDP_AUXP_C +LCDVDD_LCD +LCDVDD @ESD@ 1A_65V_T0603FF1000TM 2 2
15 16 EDP_AUXN_C
16 17
17 18 EDP_TXN0_C 1 2
18 19 EDP_TXP0_C R8 0_0603_5%
19 20 C36: colse to JEDP1.29 C102: colse to JEDP1
20 21 EDP_TXN1_C Non-TCH -->R81, R82, F5 unpop
21 22 EDP_TXP1_C D3
22 23 EE note: Never change R8 to short pad after MP
23 24 1 2 RB551V-30_SOD323-2
24 25 TOUCH_SCREEN_INT#_LCD <10> <59,77> NB_LID#
25 26 TOUCH_SCREEN_RST_LCD <10> DMIC_DATA_EDP R6243 1 2 0_0201_5% DMIC_DATA_CODEC
to Codec
26 27 LCD_BRIGHTNESS +MIC_VCC DMIC_CLK_EDP DMIC_DATA_CODEC <54>
R6244 1 2 0_0201_5% DMIC_CLK_CODEC R14
27 28 BLON_OUT_C DMIC_CLK_CODEC <54> TS_EN 1 2
28 29
+3VS_CAM R6245 1 @ 2 0_0201_5% DMIC_PCH_DATA TOUCH_SCREEN 1 33_0402_5%
TOUCH_SCREEN_PD# <7,10>
29 30 DMIC_DATA_EDP R6246 1 @ 2 0_0201_5% DMIC_PCH_CLK DMIC_PCH_DATA <10>
30 31 DMIC_CLK_EDP DMIC_PCH_CLK <10>
C18 @
31 32
32 33 USB20_N6_R 1 2 BKLT_CTRL to PCH 2
10P_0402_50V8J
33 34 USB20_P6_R R75 1 2 100K_0402_5% BLON_OUT_D9
34 35 R76 100K_0402_5%
35 36 USB20_N8_R 1 @ 2
36 37 USB20_P8_R R11 0_0201_5%
37 38
38 39
39 40
TS_DET#
TS_EN TS_DET# <7>
D2
Brightness
Main Func = Hinge up protection
2
40 +TS_VDD EDP_BKLT_CTRL <6>
ACES_51540-04001-P01 LCD_BRIGHTNESS 1 2 BKLT_CTRL 1
SP010029F00 R79 100_0402_5% +LCDVDD
3 LCD_TST
LCD_TST_C 1 2 LCD_TST LCD_TST <58>
+3VS
R80 100_0402_5% BAT54C_SOT23-3~D +LCDVDD
2
1 @ 2 CABLE2_OCP#
CABLE2_OCP# <58>
1U_0201_6.3V6M
R790 0_0201_5% C350
C955
10U_0402_6.3V6M
R-short 0831 D9
1
U4 ICPRO@ ICPRO@ 1
C 2
Backlight 1 10 C
1 2 DBC_PANEL_EN_R PANEL_BKEN_EC <58> IN1 OUT1
<10> DBC_PANEL_EN R13 @ 0_0201_5% ICPRO@ ICPRO@
BLON_OUT_C 1 2 BLON_OUT_D9 1 2 +3VALW LCDVDD_EN 2 9 CABLE1_OCP# R33 1 2 0_0201_5% CABLE2_OCP#
R78 100_0402_5% EN1 FLAG1
3 3 8
<6> EDP_TXN0 C12 1 2 0.1U_0201_16V6K EDP_TXN0_C BKLT_IN_EDP <6> VB GND to EC ICPRO@
C13 1 2 0.1U_0201_16V6K EDP_TXP0_C BAT54C_SOT23-3~D SIO_SLP_S3# 4 7 CABLE2_OCP#_R R34 1 2 0_0201_5% CABLE2_OCP#
<6> EDP_TXP0 <11,78> SIO_SLP_S3# EN2 FLAG2
1U_0201_6.3V6M
C956
1 5 6
IN2 OUT2 +3VS_CAM
C14 1 2 0.1U_0201_16V6K EDP_TXN1_C +3VALW 11 ICPRO@
<6> EDP_TXN1 EDP_TXP1_C EPAD +3VS_CAM_TS 1
C15 1 2 0.1U_0201_16V6K +3VS +LCDVDD ICPRO@ 2
<6> EDP_TXP1 2 R99 0_0402_5% +TS_VDD
1U_0201_6.3V6M
G2895ALK21U_TDFN10_2X2
R105
C954
1 2
100K_0201_5%
PRO@ U1 PRO@
<6> EDP_AUXN C17 1 2 0.1U_0201_16V6K EDP_AUXN_C C16 2 1 5 1 40mil 1
R100 ICPRO@ 0_0402_5%
C19 1 2 0.1U_0201_16V6K EDP_AUXP_C D4 IN OUT +3VS
<6> EDP_AUXP
10U_0402_6.3V6M
10U_0402_6.3V6M
2 1U_0201_6.3V6M 2 @ ICPRO@ 1 1
1
<6> EDP_VDD_EN GND 2
R15 PRO@
LCDVDD_EN
C351
C352
1 4 3 2 1
EN OC 10K_0402_5%
3 SY6288C20AAC_SOT23-5 2 2
<58> LCD_VCC_TEST_EN
High Active
1
BAT54C_SOT23-3~D R17
EC (BIST MODE) 100K_0402_5%
ICPRO@ ICPRO@
2
+19VB RF Request
For BL_PWR_SRC & LCDVDD monitor Close to JEDP1
+19VB
I2C_0_LCD_SDA 1 2 USB20_N8_R
B <10> I2C_0_LCD_SDA B
LBIST@RF@ LBIST@RF@ LBIST@RF@ R84 0_0201_5%
1 1 1
I2C_0_LCD_SCL 1 I2CTCH@
2 USB20_P8_R
<10> I2C_0_LCD_SCL
1
100P_0201_25V7K
0.1U_0201_25V6K
+DCBAT_LCD_DV13_R 2 2 2 2 +3VS
USB20_N8_R
I2CTCH@
2
SB00000W600 1 2 I2C_0_LCD_SDA
R621 MMDT3906_SOT363-6 USB20_P8_R R86 4.7K_0402_5%
LBIST@ QV18A 1 I2CTCH@
2 I2C_0_LCD_SCL
+DCBAT_LCD 10K_0201_5% LBIST@ R87 4.7K_0402_5%
I2CTCH@
6
1 2 TOUCH_SCREEN_RST_LCD
1
2
DV16 2 1 +DCBAT_LCD_DV13 R88 10K_0402_5%
LBIST@
1
R624 R627
2
200K_0201_5% LBIST@ 1 2
LBIST@ 47K_0201_5% ED2 R18 0_0201_5%
2
1
QV19 CEST523NC5VB_SOT-523-3
2
LBIST@ C @ESD@ L4
BL_PWR_MONITOR 2 USB20_P8_R 2 1
2 1 USB20_P8 <12>
B
+3VS E
3
+LCDVDD_LCD USB20_N8_R 3 4
3 4 USB20_N8 <12>
LMBT3904WT1G_SC70-3
DLM0NSN900HY2D_4P
1
@EMI@
R658
4
LBIST@ USB20_P6_R 1 2
100K_0201_5% R19
USB20_N6_R USBTCH@0_0201_5%
2
+LCDVDD_LCD_DV14_R 5
PANEL_MONITOR <58>
@
2
SB00000W600 1 2
R-short 0831
1
2
R622 MMDT3906_SOT363-6 R10 0_0201_5%
10K_0201_5% QV18B R677
+LCDVDD_LCD LBIST@ LBIST@ LBIST@
3
1M_0201_5% L3 @EMI@
1
A LBIST@ 2 1 A
1
QV21 @
2
LBIST@ C 1 2
LCDVDD_MONITOR 2 R12 0_0201_5%
R-short 0831
B
E
3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LCD/Cam/MIC/T.Panel
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 38 of 101
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
C C
B
Reserve B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
(RSVD)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 39 of 101
5 4 3 2 1
5 4 3 2 1
5.6_0402_1% 5.6_0402_1%
1
CI2 1 2 0.1U_0201_10V6K HDMI_CLKP 2 1 3 4
<6> CPU_DP1_P3 RI3 EMI@
CI3 1 2 0.1U_0201_10V6K HDMI_TX_N0 150_0402_5% RI4 EMI@
<6> CPU_DP1_N2 CI4 1 2 0.1U_0201_10V6K HDMI_TX_P0 3 4 2 1 150_0402_5%
<6> CPU_DP1_P2
D D
2
LI1 @EMI@ LI2 @EMI@
RI17
RI18
RI19
RI20
RI21
RI22
RI23
RI24
RI7 EMI@ RI8 EMI@
1
1
1
1
1
1
1
1
HDMI_TX_P2 1 2 HDMI_L_TX_P2 HDMI_TX_P1 1 2 HDMI_L_TX_P1
5.6_0402_1% 5.6_0402_1%
2
2
2
2
2
2
2
2
HCM1012GH900BP_4P HCM1012GH900BP_4P
2
470_0402_5%
470_0402_5%
470_0402_5%
470_0402_5%
470_0402_5%
470_0402_5%
470_0402_5%
470_0402_5%
HDMI_PLL_GND 2 1 2 1
RI9 EMI@ RI10 EMI@
150_0402_5% 150_0402_5%
3 4 3 4
+5VS
1
1
5.6_0402_1% 5.6_0402_1%
1
ZZZ @
DI1
3 BAW56W_SOT323-3 +5VS +5V_HDMI RO0000002HM
2
W=20mils
2
CI9
1
0.1U_0402_10V7K
G
1 6 HDMI_CTRL_CLK 2
<6> CPU_DP1_CTRL_CLK
S
QI3B
5
L2N7002DW1T1G_SC88-6
JHDMI1 CONN@
G
4 3 HDMI_CTRL_DAT 19
<6> CPU_DP1_CTRL_DATA HP_DET
S
QI3A 18
L2N7002DW1T1G_SC88-6 17 +5V
HDMI_CTRL_DAT 16 DDC/CEC_GND
B SDA B
HDMI_CTRL_CLK 15
14 SCL
13 Reserved
HDMI_L_CLKN 12 CEC
+3VS 11 CK-
HDMI_L_CLKP 10 CK_shield
HDMI_L_TX_N0 9 CK+
8 D0-
HDMI_L_TX_P0 7 D0_shield
D0+
1
1M_0402_5%
HDMI_L_TX_N1 6
5 D1-
D1_shield
RI13
HDMI_L_TX_P1 4 20
HDMI_L_TX_N2 3 D1+ GND 21
2 D2- GND 22
2
D2_shield GND
2
G
HDMI_L_TX_P2 1 23
D2+ GND
3 1 HDMI_HPD CONCR_099AKAC19NBLCNF
<6> CPU_DP1_HPD
D
DC021702131
1
20K_0402_5%
QI2
RI16
2N7002KW_SOT323-3
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI L.Shifter/Conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 40 of 101
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
(RSVD)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 41 of 101
5 4 3 2 1
1 2 3 4 5
A A
B B
C C
D D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TBT_TYPE-C_Port0 (1/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 42 of 101
1 2 3 4 5
1 2 3 4 5
Main Func =
A A
B B
Reserve
C C
D D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TBT_TYPE-C_Port0 (2/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 43 of 101
1 2 3 4 5
1 2 3 4 5
A A
B B
Reserve
C C
D D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TBT_TYPE-C_Port1 (1/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 44 of 101
1 2 3 4 5
1 2 3 4 5
A A
Reserve
B B
C C
D D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TBT_TYPE-C_Port1 (2/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 45 of 101
1 2 3 4 5
1 2 3 4 5
A A
B B
C C
D D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TBT_TYPE-C_Port2 (1/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 46 of 101
1 2 3 4 5
1 2 3 4 5
A A
B B
C C
D D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TBT_TYPE-C_Port2 (2/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 47 of 101
1 2 3 4 5
1 2 3 4 5
A A
B B
Reserve
C C
D D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TBT_TYPE-C_Port3 (1/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 48 of 101
1 2 3 4 5
5 4 3 2 1
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for TBT_TYPE-C_Port3 (2/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 49 of 101
5 4 3 2 1
1 2 3 4 5
UNPOP 1 @ 2 +5VALW_25814
CCG5C@/TBT@ RT1423
0_0603_5%
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
4.7U_0603_25V6K
CT3957 TYPEC@
R-short 0831 1 1 1 1 1 1 1
CT3968TYPEC@
CT3971TYPEC@
CT3955TYPEC@
CT3970TYPEC@
CT3972TYPEC@
CT3969TYPEC@
+LDO_3V3
2 2 2 2 2 2 W=120 mils 2
UT37 TYPEC@
1
A A
29 26
RT1446 RT5 PP5V2 VBUS1
+3VALW 100K_0201_5% 100K_0201_5% +3VALW 28 27
@TYPEC@ TYPEC@ PP5V1 VBUS2
2
ADCIN1 1
RT1451 1 TYPEC@2 100K_0201_5% TPS25814_EN# ADCIN2 32 22 TPS25814_USB_P RT1452 1 TYPEC@2 0_0201_5% USB20_P4
CT3967 VIN_3V3 USB_P
1
10U_0402_6.3V6M 23 TPS25814_USB_N RT1453 1 TYPEC@2 0_0201_5% USB20_N4
2 TYPEC@ USB_N
need to ask EC , low active for TPS25814 RT1447 RT1448 ADCIN1 2
ADCIN1
100K_0201_5% 100K_0201_5%
TYPEC@ @TYPEC@ ADCIN2 3 24 20 mils TYPEC_CC1 <50>
2
ADCIN2 CC1
low Active 25 TYPEC_CC2 <50>
CC2 +3VALW
TPS25814_EN# 5
+5VALW <58> TPS25814_EN# DISABLE
CHG_HI# 17 6 RT1422 1 TYPEC@2 100K_0201_5%
CHG_HI DEBUG
RT1458 1 TYPEC@2 100K_0201_5% 30 7 RT1426 1 @ 2 0_0201_5%
USB_OC2# <6>
CTL FAULT
1
RT1456 +LDO_3V3
2
2
100K_0201_5%
TYPEC@ RT1445 RT1444 RT1443 1
TYPEC@ TYPEC@ TYPEC@ LDO_3V3 +3VALW
thermal pad
2
GND1
CT3966 +LDO_1V5 TPS25814_POL# 1 TYPEC@2
NC1
NC2
NC3
NC4
NC5
NC6
NC7
TPS25814_I2C_SDA 10U_0402_6.3V6M RT1450 100K_0201_5%
TPS25814_I2C_SCL 2 TYPEC@ TPS25814_UFP# 1 TYPEC@2
CHG_HI PD set for 3A TPS25814_I2C_IRQ#
1 RT1449 100K_0201_5%
11
12
15
16
19
20
21
33
14
PTPS25814AARSMR_QFN32_4X4
B
(replay by TI FAE) CT3965
B
10U_0402_6.3V6M
2 TYPEC@
2
USB3_CRX_L_DTX_N3 USB3_CRX_L_DTX_N3
TYPEC@ CT3964
2 2 9 8
10U_0603_25V6M
EU16
@ESD@
1
3 4 USB3_CTX_L_DRX_P3 4 4 7 7 USB3_CTX_L_DRX_P3
L30ESD24VC3-2_SOT23-3
HCM1012GH900BP_4P USB3_CTX_L_DRX_N3 5 5 6 6 USB3_CTX_L_DRX_N3
USB3_CTX_DRX_N3 1 2 USB3_CTX_C_DRX_N3 2 TYPEC@EMI@
1 USB3_CTX_L_DRX_N3 2
<12> USB3_CTX_DRX_N3
CU23 0.1U_0402_10V7K RT1439 0_0402_5% 3 3
TYPEC@
8
1
S DIO(BR) AZ1045-04F.R7G DFN2510P10E ESD
TYPEC@ESD@
USB3_CRX_DTX_P3 2 TYPEC@EMI@
1 USB3_CRX_L_DTX_P3
POP <12> USB3_CRX_DTX_P3 RT1440 0_0402_5%
EMI@/TYPEC@/TYPEC@EMI@/TYPEC@ESD@ 2
LT14 @EMI@
1
UNPOP
CCG5C@/@EMI@/CCG5C@EMI@/@ESD@/CCG5C@RF@ 3 4 +CCG_VBUS +CCG_VBUS
HCM1012GH900BP_4P
USB3_CRX_DTX_N3 2 TYPEC@EMI@
1 USB3_CRX_L_DTX_N3
<12> USB3_CRX_DTX_N3 RT1435 0_0402_5% JUSBC1
A1 B12
GND1 GND3
USB3_CTX_L_DRX_P3 A2 B11 USB3_CRX_L_DTX_P3
USB3_CTX_L_DRX_N3 A3 SSTXP1 SSRXP1 B10 USB3_CRX_L_DTX_N3
USB3_CTX_DRX_P4 1 2 USB3_CTX_C_DRX_P4 2 TYPEC@EMI@
1 USB3_CTX_L_DRX_P4 SSTXN1 SSRXN1
C <12> USB3_CTX_DRX_P4 C
CU25 0.1U_0402_10V7K RT1438 0_0402_5% CT3962 2 1 A4 B9 1 2 CT3960
HCM1012GH900BP_4P 0.47U_0402_50V6K TYPEC@ VBUS1 VBUS3 TYPEC@ 0.47U_0402_50V6K
TYPEC@
3 4 TYPEC_CC1 A5 B8 1M_0201_5% 1 TYPEC@2 RT1276
<50> TYPEC_CC1 CC1 SUB2
USB20_P4_R A6 B7 USB20_N4_R
2 1 USB20_N4_R A7 DP1 DN2 B6 USB20_P4_R
DN1 DP2
LT15 @EMI@ RT1275 2 TYPEC@1 1M_0201_5% A8 B5 TYPEC_CC2
TYPEC_CC2 <50>
Bottom
USB3_CTX_DRX_N4 1 2 USB3_CTX_C_DRX_N4 2 TYPEC@EMI@
1 USB3_CTX_L_DRX_N4 SUB1 CC2
<12> USB3_CTX_DRX_N4
CU24 0.1U_0402_10V7K RT1433 0_0402_5% CT3963 2 1 A9 B4 1 2 CT3961
TOP
0.47U_0402_50V6K TYPEC@ VBUS2 VBUS4 TYPEC@ 0.47U_0402_50V6K
TYPEC@
DVT1 USB3_CRX_L_DTX_N4 A10 B3 USB3_CTX_L_DRX_N4 DVT1
USB3_CRX_L_DTX_P4 A11 SSRXN2 SSTXN2 B2 USB3_CTX_L_DRX_P4
SSRXP2 SSTXP2
USB3_CRX_DTX_P4 2 TYPEC@EMI@
1 USB3_CRX_L_DTX_P4 USB20_P4_R A12 B1 TYPEC_CC1
<12> USB3_CRX_DTX_P4 RT1437 0_0402_5% USB20_N4_R GND2 GND4 TYPEC_CC2
2
1 4
HCM1012GH900BP_4P EU14 2 GND5 GND8 5 EU13
2
3 4 3 GND6 GND9 6
AZC199-02SPR7G_SOT23-3 AZC199-02SPR7G_SOT23-3
TYPEC@ESD@ GND7 GND10 TYPEC@ESD@
1
2 1 JAE_DX07S024JJ2R1300~D
1
CONN@
LT16 @EMI@
USB3_CRX_DTX_N4 2 TYPEC@EMI@
1 USB3_CRX_L_DTX_N4
<12> USB3_CRX_DTX_N4 RT1436 0_0402_5%
TYPE-C
1 @EMI@ 2 EU12
RT74 0_0201_5% USB3_CTX_L_DRX_P4 1 1 10 9 USB3_CTX_L_DRX_P4
DLM0NSN900HY2D_4P USB3_CTX_L_DRX_N4 2 2 9
8 USB3_CTX_L_DRX_N4
USB20_N4 3 4 USB20_N4_R
<12> USB20_N4 3 4 USB3_CRX_L_DTX_P4 USB3_CRX_L_DTX_P4
4 4 7 7
1 @EMI@ 2 8
RT75 0_0201_5%
S DIO(BR) AZ1045-04F.R7G DFN2510P10E ESD
TYPEC@ESD@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TYPE-C_Power Path
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 50 of 101
1 2 3 4 5
5 4 3 2 1
CL3
CL4
CL5
CL6
R-short 0831
D
1 1 1 1 1
LAN CHIP 10/100/1000 UL1 1000@
NC
2
D
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
2 2 2 2 2 4
NC
1000@
1000@
1000@
RTL8111H-CG_QFN32_4X4 25MHZ_10PF_XRCGB25M000F2P34R0
RTL8111H-CG RTL8106E-CG 3
SA000080P00
3
SA000080P00 SA000065Y00 UL1 100@
CL7
LDO mode LDO mode 2 1 LANXOUT_R 1 EMI@ 2 LANXOUT
+3VS RL3 33_0402_5%
Layout:
For RTL8111H-CG 12P_0402_50V8J
10/100/1000M 10/100M RTL8106E-CG_QFN32_4X4
* Place CL10 and CL11 and CL12 close to each VDD33 pin 11, 23 , 32
For RTL8106E SA000065Y00
1
* Place CL11 and CL12 close to each VDD33 pin 23, 32 RL8
1K_0402_5%
+LAN_VDD33 VDDREG
R-short 0831 CL8, CL9 close to UL1 Pin 17, 18
CL13, CL14 close to UL1 Pin 13, 14
2
UL1 @
40 mils RL4 1 @ 2 0_0603_5% ISOLATE#
LAN_MDIP0 1 17 PCIE_CRX_C_DTX_P9 CL8 2 1 0.1U_0201_10V6K
LAN_MDIP1 MDIP0 HSOP PCIE_CRX_C_DTX_N9 PCIE_CRX_DTX_P9 <12>
CL10
CL11
CL12
4 18 CL9 2 1 0.1U_0201_10V6K PCIE_CRX_DTX_N9 <12>
MDIP1 HSON
1
LAN_MDIN0 2
1 1 1 MDIN0
CL12: close to Pin23 RL9 LAN_MDIN1 5
15K_0402_1% MDIN1 13 PCIE_CTX_C_DRX_P9 CL13 2 1 0.1U_0201_10V6K
CL10: close to Pin11 HSIP PCIE_CTX_C_DRX_N9 PCIE_CTX_DRX_P9 <12>
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
14 CL14 2 1 0.1U_0201_10V6K
2 2 CL11: close to Pin32 2 VDD10 8 HSIN PCIE_CTX_DRX_N9 <12>
2
AVDD10
1000@
VDD10 30
+LAN_VDD33 32 AVDD10 19
AVDD33 PERSTB PLTRST# <11,52,66,68>
VDDREG 23
DVDD33 20 ISOLATE#
15 ISOLATEB "PCIE_WAKE#" PU 1k on CPU side
<11> CLK_PCIE_P2 16 REFCLK_P 21
<11> CLK_PCIE_N2 REFCLK_N LANWAKEB PCIE_WAKE# <11,52,58,68>
C C
RL5 1 @ 2 0_0201_5% CLKREQ_PCIE#2_R 12 26 LED1 RL6 2 @ 1 10K_0402_5% +LAN_VDD33
<11> CLKREQ_PCIE#2 CLKREQB GPO
LANXIN 28
LANXOUT 29 CKXTAL1
R-short 0831 CKXTAL2 3 VDD10
+LAN_VDD33 TP53 27 NC 6 LAN_MDIP2
TP54 25 LED0 NC 7 LAN_MDIN2
LED1 NC 9 LAN_MDIP3
2.49K_0402_1%~D 1 2 RL7 31 NC 10 LAN_MDIN3
RSET NC 11 +LAN_VDD33
1 1 NC
CL15 CL17 33 22 VDD10 CL16 1 2 1U_0201_6V3M
4.7U_0402_6.3V6M
@
4.7U_0402_6.3V6M
@
+LAN_VDD33 Rising time (10%~90%) need GND NC
NC
24 REGOUT
CL18 1 2 0.1U_0402_10V7K
MCT3
MCT2
2 2
>0.5mS and <100mS. RTL8106E-CG_QFN32_4X4
RTL8106E-CG_QFN32_4X4
MCT1
MCT0
1000@
1000@
Layout: JP5
CL15: close to Pin32
CL17: close to Pin11 Always Open
2
RL12
RL13
RL14
RL15
+3VALW +LAN_VDD33
CL20
75_0603_5%
75_0603_5%
75_0603_5%
75_0603_5%
JP5
1
2 1 SE00000UO00
W=40mils 2MM W=40mils
Main Func = LAN LAN TransFormer 10/100M x2 @100EMI@
MCT
JP@
10P 2KV J NPO 1206 H1.25
CL20 1
TL2 SE00001OW00 CL20 EMI@
+3VALW +LAN_VDD33 LAN_MDIN3 16 1 RJ45_MDIN3 10P_1206_2KV8J
LAN_MDIP3 15
14
RX+
RX-
RD+
RD-
2
3 MCT3
RJ45_MDIP3 TL1 TOP, TL2 BOT @1000EMI@ 2
B RCT2 RCT1 B
UL2 13 4 33P 2KV J U2J 1206 H1
CL19 2 1 5 1 12 NC4 NC1 5
IN OUT +3VALW 11 NC3 NC2 6 MCT2
1U_0201_6.3V6M 2 LAN_MDIN2 10 TCT2 TCT1 7 RJ45_MDIN2
4
GND
3 2 RL10 1
LAN_MDIP2 9 TX+
TX-
TD+
TD-
8 RJ45_MDIP2 Both 100 and 1000 use 10P
<58> AUX_ON EN OC 10K_0402_5% NS681611H LAN
SY6288C20AAC_SOT23-5
High Active JLAN1 CONN@
2
12
RL11 GND 11
100K_0402_5% GND 10
TL1 GND 9
LAN_MDIP0 16 1 RJ45_MDIP0 RJ45_MDIP0 1 GND
1
10 7 4
LAN_MDIN1 9 TX+ TD+ 8 RJ45_MDIN1 PR3+
TX- TD- RJ45_MDIN2 5
NS681611H LAN PR3-
RJ45_MDIN1 6
PR2-
Layout note: RJ45_MDIP3 7
30 mil spacing between MDI differential pairs. PR4+
1.0V Source RL1 CL2 CL5 CL6 CL10 CL12 Layout note: RJ45_MDIN3 8
PR4-
1 30 mil spacing between MDI differential pairs.
CL21
0.01U_0402_16V7K SANTA_130460-N
2 DC021702130
RTL8111H-CG
Main:
A
RTL8111G-CGT
(71.08111.U03)
LDO O O O O O X Follow Reference Schematic 0.01uF~0.4uF SP050005Y00, S X'FORM_ NS0015 LF LAN A
RTL8106E-CG X X X X X O
(071.08106.0003) LDO
Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
Issued Date 2018/04/01 Deciphered Date 2019/04/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN RTL8111/RTL8106
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 51 of 101
5 4 3 2 1
5 4 3 2 1
+3VALW_PCH
1A +3.3V_WLAN
D D
R-short 0831
10U_0402_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
10P_0402_50V8J
1 1 1 1
CW1
CW2
CW3
CW4 RF@
2 2 2 2
+3.3V_WLAN
JWLAN1
1 2
3 GND1 3.3V1 4
C <12> USB20_P10 USB_D+ 3.3V2 C
<12> USB20_N10 5 6
USB_D- LED1# TP51
7 8
9 GND2 PCM_CLK/I2S_SCK 10
<13> CNV_CRX_DTX_N1 SDIO_CLK PCM_SYNC/I2S_W S CNV_RF_RESET# <13>
11 12
<13> CNV_CRX_DTX_P1 13 SDIO_CMD
SDIO_DAT0
PCM_IN/I2S_SD_IN
PCM_OUT/I2S_SD_OUT
14
CLKREQ_CNV# <13>
1.8V
15 16
<13> CNV_CRX_DTX_N0 SDIO_DAT1 LED2# TP52
17 18
<13> CNV_CRX_DTX_P0 19 SDIO_DAT2 GND3 20
21 SDIO_DAT3 UART_W AKE# 22 CNV_BRI_CRX_DTX_R RW3 1 CNV@ 2 49.9_0201_1%
<13> CLK_CNV_CRX_DTX_N SDIO_W AKE# UART_RXD CNV_BRI_CRX_DTX <13>
<13> CLK_CNV_CRX_DTX_P 23
SDIO_RESET#
RW4 1 @ 2 0_0201_5%
HOST_DEBUG_TX <58>
32 CNV_RGI_CTX_DRX_R RW5 1 CNV@ 2 0_0201_5%
UART_TXD CNV_RGI_CRX_DTX_R CNV_RGI_CTX_DRX <13>
33 34 RW6 1 CNV@ 2 49.9_0201_1%
PCIE_CTX_C_DRX_P10 GND4 UART_CTS CNV_BRI_CTX_DRX_R CNV_RGI_CRX_DTX <13>
<12> PCIE_CTX_DRX_P10 0.1U_0201_10V6K CW5 1 2 35 36 RW7 1 CNV@ 2 0_0201_5%
PCIE_CTX_C_DRX_N10 PETp0 UART_RTS CNV_BRI_CTX_DRX <13>
<12> PCIE_CTX_DRX_N10 0.1U_0201_10V6K CW6 1 2 37 38
39 PETn0 VENDER_DEFINED1 40
<12> PCIE_CRX_DTX_P10
41
43
GND5
PERp0
VENDOR_DEFINED2
VENDOR_DEFINED3
42
44
RW5,RW7 close to CPU
<12> PCIE_CRX_DTX_N10 45 PERn0 COEX3 46
47 GND6 COEX2 48
<11> CLK_PCIE_P1 REFCLKP0 COEX1
49 50 WLAN_SUSCLK RW24 1 2 0_0402_5% SUSCLK_R
<11> CLK_PCIE_N1 REFCLKN0 SUSCLK(32kHz) SUSCLK_R <11,58>
51 52
B
<11> CLKREQ_PCIE#1
R-Short 0831 1 @ 2 CLKREQ_PCIE#1_R 53 GND7 PERST0# 54 BT_RADIO_DIS#_R RC4123 1 @ 2 0_0201_5%
PLTRST# <11,51,66,68>
BT_RADIO_DIS# <10>
B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NGFF_WLAN CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 52 of 101
5 4 3 2 1
5 4 3 2 1
D D
C C
B
Reserve B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WIGIG / WIDI(RSVD)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 53 of 101
5 4 3 2 1
5 4 3 2 1
Main Function:
+3VALW_PCH +1.8V_CS8409
UA4
1 2 16 1
<54,58> EC_MUTE# 15 B1 A1 2 EC_MUTE#_LS <54,55>
RA167 0_0402_5%
14 VCCB VCCA 3 HDA_BIT_CLK_LS
<10> HDA_BIT_CLK_R 13 B2 A2 4 HDA_SYNC_LS
<10> HDA_SYNC_R B3 A3 HDA_SDOUT_LS
12 5
D <10> HDA_SDOUT_R B4 A4 HDA_SDIN0_R_LS D
11 6 1 RA84 2 33_0201_1% HDA_SDIN0_LS
<10> HDA_SDIN0 1 2 10 B5 A5 7 HDA_RST#_LS
<10> HDA_RST#_R B6 A6
RA157 0_0402_5% 9 8
GND OE
1 RA153 2 TXB0106PWR_TSSOP16 +1.8V_CS8409
10K_0201_5% 1 2
For power saving CA172 1 RA161 !!! Attention !!!
1
RA162 0_0402_5%
According to the Vendor reference circuit, CA89 and CA168 must be exchanged.
0.1U_0201_10V6K
1
10K_0201_5% CA173 But Bullseye PVT does not enter the layout, so in order to modify the ispd Bom, the CA89 and CA168 of the circuit are deliberately exchanged.
2 0.1U_0201_10V6K
So now the capacitance value of the circuit is wrong, please exchange.
2
2 +1.8V_CS8409
1 Low ESR, X7R or better for VL_HD Capacity
CA88
1U_0603_16V7
2
1
1
+1.8V_CS8409
CA168 CA202
@
2
2
0.22U_0201_10V6K
0.1U_0201_10V6K
0.22U_0201_10V6K
1 2
<54,58> EC_MUTE# EC_MUTE#_LS <54,55>
RA163
1
0_0402_5%
CA89
19
38
30
4
UA1
VL_SP1
VL_SP2
VA_PLL
VL_HD
CS8409_2_SCLK <55>
CS8409_2_FSYNC <55>
10P_0201_50V8J
10P_0201_50V8J
1 1
18 1 TA4 TA@ @EMI@ @EMI@
HDA_BIT_CLK_LS 29 ASP2_MCLK 21 RA87 1 2 33_0402_5% CS8409_2_SCLK
HDA_SYNC_LS BCLK ASP2_SCLK CS8409_2_FSYNC
To Amp TAS5825
CA180
CA181
33 14 RA88 1 2 33_0402_5%
HDA_SDOUT_LS 32 SYNC ASP2_LRCK/FSYNC 17 RA89 1 SW@ 2 33_0402_5% 2 2
HDA_BIT_CLK_R HDA_SDIN0_LS SDO ASP2_SDIN CS8409_2_SDIN <55>
28 15 RA90 1 2 33_0402_5%
HDA_RST#_LS 34 SDI ASP2_SDOUT CS8409_2_SDOUT <55>
RST
C C
2 1 TA5 TA@
ASP1_MCLK
2
33_0402_5%
10P_0201_50V8J
35 1 RA93 1 2 33_0402_5%
NC ASP1_SDIN CS8409_1_SDIN <55>
10P_0201_50V8J
5 RA94 1 2 33_0402_5% @EMI@ 1 1 @EMI@
23 ASP1_SDOUT CS8409_1_SDOUT <55>
@
1
CA191
CA192
10K_0201_5%
1
DMIC_DATA 25 9 1 TA6 TA@ De-pop control 2 2
DMIC1_DATA SPI_SCLK
2
CA87
@EMI@
2
GPIO2/CS2 11 RA40 1 2 0_0402_5%
GPIO3/MISO2 CS8409_WAKE <55>
1 TA@ TA2 1 27 10 CS8409_I2C_SCL <55>
0.1U_0201_10V6K TA@ TA3 1 26 DMIC2_DATA GPIO6/SCL 16
RA8,CA20: close to UA1.5 DMIC2_CLK GPIO7/SDA CS8409_I2C_SDA <55>
CA169
2 22 RA43 1 2 0_0402_5% CS8409_INT
GND_PLL
GPIO4 CS8409_RST# CS8409_INT <55>
39 RA44 1 2 0_0402_5%
GNDL1
GNDL2
GPIO5 CS8409_RST# <55>
GNDD
PAD
CS8409-CNZR_QFN40_5X5
31
41
3
20
37
CS8409 AUD_PC_BEEP input 1.8V signal,
RA76 1 2 33_0402_5% DMIC_DATA please make sure you BEEP and SPKR voltage
<38> DMIC_DATA_CODEC
EMI@ DA5
LA10 1 2 BLM15PX221SN1D_2P DMIC_CLK 2
<38> DMIC_CLK_CODEC <10> SPKR
1 AUD_PC_BEEP_C 1 2 1 2 AUD_PC_BEEP
1 1
CA4,LA5 place colse to UA1.3 RA55 CA53 0.1U_0402_16V7K
1
CA83 CA84 <58> BEEP 3 8.2K_0201_5%
B B
10P_0402_50V8J 6.8P_0402_50V RA59
@RF@ @RF@ BAT54C_SOT23-3~D 10K_0201_5%
2 2
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
(RSVD)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 54 of 101
5 4 3 2 1
5 4 3 2 1
Main Function:
2 1
RA165 1K_0402_1%
LP3878@ LP3878@
+3VALW CA182
0.01U_0402_16V7K U35 LP3878@
1 2 1 8
2 BYPASSSHUTDOWN# 7
3 NC NC 6
4 GND ADJ 5
INPUT OUTPUT 9
2
1
LP3878@ TML-PAD LP3878@
CA183 LP3878@ LP3878MR-ADJ-NOPB_SO POWERPAD8
1
LP3878@ RA164 moat CS42L42 Power state:
CA187 CA186 806_0402_1% 1. Off configuration: Clock/data lines held low;
1
0.01U_0402_16V7K
1 2 1 2 3300P_0201_16V7K
RA166 47K_0201_5% 2 +1.8V_CS8409 RESET = LOW; VA = VL = VCP = 0 V; VP = 3.6 V.
2
10U_0402_10V6M LP3878@
15.1mA 2. Standby configuration: Clock/data lines held low;
D LP3878@ Dmic 4.419mA + ASP 10.683mA VA = VL = VCP = 0 V; VP = 3.6 V; M_MIC_WAKE = 0, M_HP_WAKE = 0 (unmasked). D
CA184 1 2 10U_0402_10V6M 1 2
2 2 RA107 0_0402_5%
3. Standby configuration (RCO clocking): Clock/data lines held low;
1 2 LP3878@ LP3878@ 2 VA = 0 V; VL = 1.8 V, VCP = 0 V, VP = 3.6 V; M_MIC_WAKE = 0, M_HP_WAKE = 0 (unmasked).
CA185 0.01U_0402_16V7K CA188 CA189
LP3878@
1U_0402_10V6K
0.1U_0402_10V7K
CA111
1 1
10U_0402_6.3V6M
1
Close pin33
+1.8V_CS42L42
1 2 1 2
6mA VA 3.032mA + VCP 1.2mA + VL 1.559mA RA113 0_0201_5% RA114 0_0201_5% +5V_PVDD +5V_PVDD
+1.8V_PRIM 1 2
Audio1v8@ RA108 0_0402_5%
QA1 SB00000FG10 2 1 CA113
AO3416L_SOT-23-3 CS8409_I2C_SDA
<54> CS8409_I2C_SDA 1 EMI@ 1 EMI@ 1 1 1 EMI@ 1 EMI@
.1U_0402_16V7K
1
CA112 CS8409_I2C_SCL CA175 CA174 CA162 CA163 CA164 CA165 CA166 CA167 CA176 CA177
<54> CS8409_I2C_SCL
1 3 10U_0402_6.3V6M
D
1 2
0.1U_0402_10V7K
0.1U_0402_10V7K
10U_0603_10V6M
10U_0603_10V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
10U_0603_10V6M
10U_0603_10V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
2
2
2 2 2 2 2 2
Close pin29
G
2
CS8409_1_LRCK
CS8409_1_LRCK <54>
2KV +1.8V_CS42L42
CS8409_1_SCLK
+3VS CS8409_1_SCLK <54>
1
+1.8V_DVDD CA117 RA116
0.1U_0402_16V7K +3VALW_VP 1 2 CS8409_1_SDOUT
15mA 1 2 TA@ 0_0201_5% CS8409_1_SDOUT <54> +1.8V_DVDD
1 2 2 RA117 0_0402_5% TA11 +1.8V_DVDD
RA109 0_0402_5% CS8409_1_SDIN
1 2 CS8409_1_SDIN <54>
2 1 @ 1 EMI@ 1 EMI@ 1
1
CA114 CA115 RA118 0_0201_5% CA179 CA178
+5VS
1
+5V_PVDD +3VALW_VP RA150 CA160 CA161
2A
10U_0402_6.3V6M
.1U_0402_16V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
Close pin8
39
47
37
36
35
34
38
43
42
44
41
10K_0402_5%
2
4
1 2 2 2 2
4.7U_0402_6.3V6M
0.1U_0201_16V6K
UA2 @
1 2 2 1 RA168 2
VD_FILT
ASP_SDOUT
VL
SCL
AD0
AD1
GNDL
DIGLDO_PDN
ASP_LRCK/FSYNC
ASP_SDIN/SWIRE_SD
SDA
ASP_SCL/SWIRE_CLK
<54> EC_MUTE#_LS
1
RA106 0_0805_5% 0_0402_5%
CA118 +1.8V_DVDD
<54> CS8409_MUTE
10U_0402_6.3V6M 2
1
CA190 HW@
RA119 2 RA173 1
21
22
+3VALW 1U_0402_10V6K
4
+3VALW_VP TA@ TA9 1 45 0_0201_5% 1 10K_0402_5% UA3
0.3mA CS8409_RST# SPDIF_TX 48 1 2 +1.8V_CS42L42
DVDD
PVDD
PVDD
PVDD
PVDD
C <54> CS8409_RST# VL_SEL +1.8V_DVDD C
RA170 6 TA@
1 2 1 0_0201_5%2 40 VP TA13 1 9
SWIRE_SEL GPIO0
2
RA110 0_0402_5% 32 7 10 18 CA170 2 1 1U_0402_10V6K
+1.8V_CS42L42 FILT+ VCP 8 CA119 1 2 2.2U_0402_6.3V6M <54> CS8409_2_SDIN 1 11 GPIO1 GVDD 19 2 1
RA151 TA@TA14
1 FLYP 9 0_0402_5% HW@ 2 RA158 1 17 GPIO2 AVDD CA171 1U_0402_10V6K
RA120 1 2 47K_0201_5% 2 RESET FLYC 11 CA120 1 2 2.2U_0402_6.3V6M 0_0402_5% PDN# 2 AUD_SPK_L+
RA121 1 2 47K_0201_5% 3 INT FLYN 10 OUT_A+ 1 1 2
+3VS
1
+3V_DM WAKE +VCP_FILT 13 8 BST_A+ CA158 0.22U_0201_10V6K
0.2mA
1
CS8409_INT CA121 +1.8V_CS42L42 -VCP_FILT 12 CA159 1 2 1U_0402_10V6K 7 ADR 30 AUD_SPK_L-
<54> CS8409_INT CS8409_WAKE 33 GNDCP VR_DIG OUT_A- 29 1 2
Dmic 0.194mA <54> CS8409_WAKE
TAS5825MRHBR_VQFN32_5X5
VA BST_A-
1
10U_0603_10V6M
1 2 CA122 CA123 CA124 CA157 0.22U_0201_10V6K
2
2
RA169 0_0402_5% 49 22 CS8409_2_FSYNC 12 23 AUD_SPK_R+
PAD HSBIAS_FILT <54> CS8409_2_FSYNC LRCLK OUT_B+
2
RA122 31 23 1 2 CS8409_2_SCLK 13 24 1 2
2
GNDA HSBIAS_FILT_REF <54> CS8409_2_SCLK CS8409_2_SDOUT SCLK BST_B+
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
47K_0201_5% 46 RA152 14 CA156 0.22U_0201_10V6K
RING_SENSE
GNDD <54> CS8409_2_SDOUT SDIN
HS_CLAMP1
HS_CLAMP2
5 CA200 0_0402_5% SW@ 27 AUD_SPK_R-
TIP_SENSE
TSTI1 OUT_B-
HPSENSA
HPSENSB
4.7U_0402_6.3V CS8409_I2C_SDA RA41 1 SW@ 2 0_0402_5% CS8409_I2C_SDA_R 15 28 1 2
HS3_REF
HS4_REF
HPOUTA
HPOUTB
1
CS8409_I2C_SCL 2 0_0402_5% CS8409_I2C_SCL_R SDA BST_B-
GNDHS
1 16 CA155 0.22U_0201_10V6K
HSIN+
DGND
1
PGND
PGND
PGND
PGND
AGND
SCL
GPAD
1
HSIN-
CA125 RA42 SW@
HS3
HS4
2.2U_0402_6.3V6M
2
CS42L42-CNZR_QFN48_6X6
21
18
19
20
14
15
16
17
24
28
26
27
29
30
25
25
26
31
32
20
33
RA156 @
2 1
+1.8V_DVDD
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
JACK_PLUG
RING2_R
RA148
0_0402_5%1 HW@ 2 CS8409_I2C_SDA_R Ti AMP IC
1 HW@ 2 CS8409_I2C_SCL_R
RA149 Project CPN Vendor PN
2
2
0_0402_5%
2
2
Bullseye SA0000ECT10 SN005825TRHBR (0db)
1RA123
RA124
1 RA125
RA126
Warlock SA0000ECT20 SN005825DRHBR (-15db)
1
SLEEVE
RING2
AUD_HP1_JACK_L
AUD_HP1_JACK_R
330P_0402_50V7K
330P_0402_50V7K
CA14
CA42
1
2 Layout Note:
@EMI@
@EMI@
B 2
Speaker trace width >40mil @ 2W4ohm speaker power Speaker B
@ESD@
1 @ESD@
@ESD@
1 @ESD@
1 DA20
DA21
1 DA22
DA23
ACES_50224-00401-001
CONN@
AUD_HP1_JACK_R RA139 1 2 0_0402_5% AUD_HP1_JACK_R1 LA13 1 EMI@ 2 BLM15PX330SN1D_2P HPOUT_R SP02000GC10
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
LA14 1 ESD@ 2 BLM15PX330SN1D_2P SLEEVE_R 1 1 1 1
EMI@ CA141
EMI@ CA142
EMI@ CA143
EMI@ CA144
AZ4A24-01F.R7G_DFN0603P2Y2
AZ4A24-01F.R7G_DFN0603P2Y2
AZ4A24-01F.R7G_DFN0603P2Y2
AZ4A24-01F.R7G_DFN0603P2Y2
SLEEVE
2 2 2 2
2
Layout Note: Universal Jack
Close to UA1
(Use Global Headset Jack)
JHP1 CONN@
SLEEVE_R 3
CLOSE TO JHP1 HPOUT_L 1 G/M
L/R EMI need withstand voltage 10V
HPOUT_R
HPOUT_L
JACK_PLUG 5
5
JACK_PLUG JACK_PLUG_DET 6
JACK_PLUG_DET 6
HPOUT_R 2
R/L
RING2_R 4
7 M/G
GND
YUQIU_PJ753-F07J1BE-B
1
2
10K_0402_5%
RA144
10K_0402_5%
RA145
1 1 1 1 1 1 DC021512140
3
JACK_PLUG_DET
100P_0402_50V8J
CA147 EMI@
100P_0402_50V8J
CA148 EMI@
680P_0402_50V8J
CA149 ESD@
680P_0402_50V8J
CA150 ESD@
ESD@
AZ5123-02S.R7G_SOT23-3
DA17
680P_0402_50V8J
CA151 @ESD@
680P_0402_50V8J
CA152 @ESD@
ESD@
AZ5125-02S.R7G_SOT23-3
DA18
@ESD@
AZ5125-02S.R7G_SOT23-3
DA19
@ @
10 mils
1
2 2 2 2 2 2
2
RA146
A 0_0201_5% Layout Note: A
Headset jack placement should close to UA2
2
1
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
(RSVD)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 55 of 101
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Main Function:
D D
C C
B
Reserve B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
(RSVD)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 57 of 101
5 4 3 2 1
5 4 3 2 1
+3VALW +3VALW_EC
1
SD041100280 10K_0201_1% EVT 10K
RE5 1 @ 2 SD000026U00 17.8K_ 0201_1% RE3 DVT-1 17.8K RE1
+3VALW 0_0402_1% SD000015700 27K_ 0201_1% Ra @ Reserve 27K Ra @
SD000014200 37.4K_ 0201_1% 17.8K_ 0201_1% 10K_0201_1% 100K_0201_1% DVT-2 37.4K 100K_0201_1%
<63> KSI[0..7] 1 1 1 1 1 1 1 1 1 1
1
RE66 1 2 10K_0201_5% KSI0 CE1 CE2 CE5 CE6 CE7 CE8 CE9 CE506 CE507 CE100 CE101 SD000014400 49.9K_ 0201_1% Reserve 49.9K
R-short 0831
2
RE67 1 2 10K_0201_5% KSI1 RF@ RF@ SD000013K00 64.9K_ 0201_1% MODEL_ID Pilot 64.9K BOARD_ID
<63> KSO0[0..9] NA 82.5K_ 0201_1% SD000026U00 SD041100280 Reserve 82.5K
10U_0402_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
12P_0201_25V8J
100P_0201_25V8J
RE68 1 2 10K_0201_5% KSI2
SD00002AM80 107K_ 0201_1%
2
2 2 2 2 2 2 2 2 2 2
0.1U_0201_10V6K
RE69 1 2 10K_0201_5% KSI3 1 RE1 1
<63> KSO[10..16]
For CE10 RE4 CE11 RE2
RE70 1 2 10K_0201_5% KSI7 Model ID Select Rb Rb
0.1U_0201_10V6K
RE71 1 2 10K_0201_5% KSI6 100K_0201_1% 100K_0201_1%
RE72 1 2 10K_0201_5% KSI5 UMA 10K 2 2
1
RE73 1 2 10K_0201_5% KSI4 DIS 17.8K
64.9K_ 0201_1%
RE74 1 2 100K_0201_5% KSO00 A8 B5 B48 B39 A52 B26 B4 B9 SD000013K00
RE75 1 2 100K_0201_5% KSO01
RE76 1 2 100K_0201_5% KSO02 Every 0.1uF decoupling capacitor should close to designated UE1 power pin
RE77 1 2 100K_0201_5% KSO03
A64
B48
B39
A52
B26
B19
RE84 1 2 100K_0201_5% KSO12 CE12 PBAT_CHG_SMBCLK RE9 1 2
A8
B5
B4
B9
RE85 1 2 100K_0201_5% KSO13 R-short 0831 UE1 4.7K_0201_5%
0.1U_0402_10V7K
VBAT
VTR1
VTR1
VTR1
VTR1
VTR1
VTR2
VTR3
VTR_PLL
VTR_REG
RE86 1 2 100K_0201_5% KSO08 2 CABLE2_OCP# RE555 1 2
RE87 1 2 100K_0201_5% KSO15 MISC. Interface & GPIO 100K_0201_5%
RE88 1 2 100K_0201_5% KSO14 B63 EC_PCH_SPI_EN TOUCHPAD_INTR# RE542 1 @ 2
GPIO062_nRESETO/I2C11_SCL NB_MUTE# EC_PCH_SPI_EN <59>
RE89 1 2 100K_0201_5% KSO16 A1 RE29 1 @ 2 0_0201_5% 100K_0201_5%
1 2 GPIO221/32KHz_OUT/nSYS_SHDN A2 EC_MUTE# <54> GPU_THM_SMBDAT 1 2
RE18 100K_0201_5% KSO09 RUNPWROK RE565 @
GPIO057/VCC_PWRGD B2 nRESET_IN R-short 0831 499_0201_1%
RE19 1 2 100K_0201_5% USB_PWR_EN# JTAG Interface nRESET_IN B3 RESET_OUT# RE550 1 @ 2 0_0201_5% GPU_THM_SMBCLK RE566 1 @ 2
BAT1_LED# JTAG_TMS GPIO106/PWROK LCD_VCC_TEST_EN SYS_PWROK <11>
RE21 1 2 100K_0201_5% A56 A3 499_0201_1%
BAT2_LED# JTAG_CLK GPIO150/I2C15_SCL/JTAG_TMS/UART2_DTR# GPIO226 SHD_IO1 LCD_VCC_TEST_EN <38>
RE23 1 2 100K_0201_5% B59 B22
1 2 VCCDSW_EN JTAG_TDO A55 GPIO147/I2C15_SDA/JTAG_CLK/UART2_DSR# GPIO224/GPTP_IN0/SHD_IO1 A21 SHD_IO3 SHD_IO1 <9> +RTC_CELL
RE58 100K_0201_5% PWRGD strap
1 2 EC_PCH_SPI_EN JTAG_TDI B58 GPIO146/I2C09_SCL/JTAG_TDO/UART2_TX GPIO016/GPTP-IN1/SHD_IO3/ICT3/DSW_PWROK B23 SHD_IO2 SHD_IO3 <9>
RE545 @ 100K_0201_5%
PTP_DIS# JTAG_RST# GPIO145/I2C09_SDA/JTAG_TDI/UART2_RX GPIO227/SHD_IO2/PWRGD_STRAP SHD_IO0 SHD_IO2 <9>
RE560 1 2 100K_0201_5% A40 A22
JTAG_nRST GPIO223/SHD_IO0 PS_ID SHD_IO0 <9>
B41
GPIO116 PS_ID <82> LID_POWER_ON# RE556
A6 BEEP 1 2 100K_0201_5%
GPIO035/PWM8/CTOUT1/ICT15 A30 BEEP <54>
KSO15
+3VS ESPI Host Interface GPIO151/ICT4/KSO15 A39 TABLE_MODE# RE501 1 @ 2 0_0201_5% TABLE_MODE#_EC
ESPI_IO0 A17 MEC1515 GPIO117 B32 KSI0
TABLE_MODE#_EC <10>
RE163 1 @ 2 10K_0201_5% SSD_SCP# <9> ESPI_IO0 ESPI_IO1 A18 GPIO070/ESPI_IO0/I2C14_SDA GPIO017/KSI0/UART0_nDCD A31 KSO00 +3VS
<9> ESPI_IO1 ESPI_IO2 B20 GPIO071/ESPI_IO1/I2C14_SCL GPIO040/GPTP_OUT2/KSO00/UART1_nCTS B33 KSI7
<9> ESPI_IO2 ESPI_IO3 A19 GPIO072/ESPI_IO2/I2C01_SDA_ALT GPIO032/KSI7/GPTP-OUT0/UART0_nRI A32 KSI6 TACH_FAN1 RE16 1 2
+3VALW <9> ESPI_IO3 ESPI_CLK B18 GPIO073/ESPI_IO3/I2C01_SCL_ALT GPIO031/KSI6/GPTP_OUT1 B34 KSI3 10K_0201_5%
ESPI_CLK <9> ESPI_CLK ESPI_RESET# GPIO065/ESPI_CLK/I2C13_SCL GPIO026/KSI3/UART0_nDTR/I2C12_SDA PWM_FAN1
B16 B35 KSI4 RE17 1 2
<9> ESPI_RESET# ESPI_CS# GPIO061/ESPI_nRESET GPIO027/KSI4/UART0_nDSR/I2C12_SCL
B17 A33 KSI5 10K_0201_5%
<9> ESPI_CS# GPIO066/ESPI_nCS/I2C13_SDA GPIO030/KSI5/I2C10_SDA
1
LID_CL_SIO# <9,66> GPU_THM_SMBDAT GPU_THM_SMBCLK B62 GPIO003/I2C00_SDA/UART2_nRI GPIO043/SB-TSI_CLK A38 PECI_VREF 100K_0201_5%
<9,66> GPU_THM_SMBCLK
2
1
SHD_CS0#
SHORT PADS
CLEC1 @
1U_0201_6.3V6M
CE505
100_0201_1%
RE527
2
TACH_FAN1 B55 GPIO014/PWM6/GPTP_IN2 GPIO171/UART1_RX/CEC_IN A53 HOST_DEBUG_TX
Boot Source Select Strap <77> TACH_FAN1 A51 GPIO050/ICT0_TACH0 GPIO241/CMP_VOUT0 B7 SIO_PWRBTN# <52> HOST_DEBUG_TX
1=Use the Shared SPI pins for Boot LCD_TST A26 GPIO051/ICT1_TACH1 GPIO254/CMP_VREF1 A63 LID_POWER_ON# SIO_PWRBTN# <11> R-short 0831
<38> LCD_TST GPIO052/ICT2_TACH2 nVCI_IN1/GPIO162 LID_POWER_ON# <59>
2
0=Use the eSPI Flash Channel for Boot RE532 2 @ 1 0_0201_5% IMVP_VR_ON B1 B67 POWER_SW_IN#
<78> IMVP_VR_EN GPIO033/TACH3 nVCI_IN0/GPIO163 POWER_SW_IN# <63>
RE529
+RTC_CELL 4.7K_0402_5%
MISC. Interface & GPIO
R-short 0831
1
1
VR_CAP
B66
VSS_EP
CE508
NC
2
1
2 @ @ Un-pop RE546 100K_0201.
TP86
100K_0201_5% SA0000CEG00 MEC1515H-D0-I-NB_DQFN132_11X11 Pop RE32 100K_0201. RE30 RE546
B R-short 0831 B
C1
B8
5
2
EC_PCH_SPI_EN 2 1U_0402_16V6K SYSPWR_PRES
A
G
ESR <100m ohms 1
2
1
74LVC1G32GW_TSSOP5 G3@ CE22
3
5
NL17SZ06EDFT2G_SOT-353
32.768KHz Oscillator +RTC_CELL
1
2
VCC
4 OUT Y 2 PROCHOT
+3V_OSC +3VLP <7,16,82,84,88> H_PROCHOT# INA
GND
2
XE1 @ NC
1
OSC_CLK 3 4 RE552 1 @ 2 0_0201_5% CE24 RE45
3
OUTPUT VCC @ESD@
RE553 1 @ 2 0_0201_5% 100P_0201_25V8J 100K_0201_5%
2
0.01U_0201_10V6K
1
2 1
GND STAND-BY @ CE510
32.768KHZ_15PF_FRB5014A
SJ000009G00 2
+3VALW_EC
JESPI1 CONN@
1
1 2
2 3 ESPI_IO0 R-short 0831
3 4 ESPI_IO1
4 5 ESPI_IO2 RUNPWROK 1 @ 2 ALL_SYS_PWRGD
5 6 ESPI_IO3 <11> RUNPWROK ALL_SYS_PWRGD <78,85>
RE508 0_0201_5%
6 7 ESPI_CS#
7 8 ESPI_RESET#
11 8 9
12 GND 9 10 ESPI_CLK
GND 10
JXT_FP241AH-010GAAM
+3VALW_EC
SP010021O00
+3VALW_PCH
1
JDEG1 CONN@
2
1 +EC_DEBUG_VCC +3VALW_EC
1 2 JTAG_TDI PRIM_PWRGD 1 @ 2 PRIM_PWRGD_R RE165 1 @ 2 0_0201_5%
2 3 JTAG_TMS JTAG_TDI 1.8V_PRIM_PG <16,87,91>
RE90 1 2 10K_0201_5% RE182 0_0201_5% RE507 1 2 0_0201_5%
3 4 JTAG_CLK JTAG_TMS 1 2 PG_VCCIN_AUX <91>
RE91 10K_0201_5%
4 5 JTAG_TDO JTAG_CLK RE92 1 2 10K_0201_5%
5 6 MSCLK JTAG_TDO RE93 1 2 10K_0201_5% R-short 0831
6 7 MSDATA 0_0201_5%
7 8 HOST_DEBUG_TX RE525 1 @ 2 DEBUG_TX RE524 1 @ 2 10K_0201_5%
11 8 9 DEBUG_TX MSCLK RE49 1 2 10K_0201_5%
12 GND 9 10 MSDATA RE50 1 @ 2 100K_0201_5%
GND 10 RE57 1 @ 2 10K_0201_5%
JXT_FP241AH-010GAAM R-short 0831 Security Classification Compal Secret Data Compal Electronics, Inc.
SP010021O00 Issued Date 2018/08/31 Deciphered Date 2019/08/06 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC MEC1515
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 58 of 100
5 4 3 2 1
5 4 3 2 1
VCCDSW_EN_GPIO
VCCDSW_EN_GPIO <78>
D D
RE564
1
100K_0402_1% D @ Q32
1 2 VCCDSW_OFF 2
@ G
S 2N7002KW 1N SOT323-3
3
+3VALW_EC
0.22U_0402_16V7K
1
CE511
@
2
1
RE97
1
100K_0201_5%
RE99
2
1M_0402_1%
PCH_DPWROK_EC
PCH_DPWROK_EC <58,78>
U34
2
RE562 1 2 0_0201_5% DPWROK_OFF# 1 8
<58,78> PCH_RSMRST#_R A# VCC
RE563 1 @ 2 0_0201_5% 2 7 CEXT_U34
<58> EC_PCH_SPI_EN B R/CEXT
CLR#_U34 3 6
CLR# CEXT
1
D Q19
4 5 PCH_DPWROK_OFF 2
GND Q G
2
0.22U_0402_16V7K
SN74LVC1G123DCUR_VSSOP8 1 S 2N7002KW 1N SOT323-3
3
CE36
RE98
1M_0201_5%
2
1
C C
B B
RE558
RE557 390K_0402_1%
100K_0201_1% UE6 S5LID@
S5LID@ 1 8
2
A# VCC LID_POWER_ON#
LID_POWER_ON# <58>
2
NB_LID# 2 7
B R/CEXT
3 6
CLR# CEXT
1
D
4 5 LID_POWER_ON#_G 2 QE19
GND Q G 2N7002KW_SC-70-3
SN74LVC1G123DCUR_VSSOP8 S S5LID@
3
+3VALW S5LID@
1
1
10U_0402_10V6M
CE109
1M_0201_1%
RE480
PU in P.58
1
RE122 S5LID@
Pull up +3VLP on DB Hall sensor side 100K_0201_5% 2 S5LID@
@
2
DE1
2
NB_LID# 1 2 LID_CL_SIO#
<38,77> NB_LID# LID_CL_SIO# <58>
Connect to EC
RB520SM-30T2R_EMD2-2
S5LID@
RE561 1 2 0_0201_5%
LID@
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
(RSVD)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 59 of 101
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
C C
B
Reserve B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
(RSVD)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 60 of 101
5 4 3 2 1
5 4 3 2 1
@ 1k ohm
+3VS
DB45 ISH_I2C_0_SCL
ISH_I2C_0_SCL
4.7k ohm @ 2.2k ohm Reserved
DB44 ISH_I2C_0_SDA
ISH_I2C_0_SDA
+3VS 4.7k ohm
+3VS @ 2.2k ohm
D D
USB20_P8_R 0 ohm I2C_0_LCD_SCL 0 ohm I2C_0_SCL DV18 1k ohm
I2C0_SCL
JeDP CONN DW18
I2C Address:0x10 For Touch Screen
USB20_N8_R 0 ohm I2C_0_LCD_SDA 0 ohm I2C_0_SDA
I2C0_SDA 1k ohm
+3VS
CY39 ISH_I2C_1_SCL
ISH_I2C_1_SCL SCL FreeFall Sensor FreeFall Sensor reserved
TGL-U
DB47 ISH_I2C_1_SDA LNG2DMTR LGA SMBus Address: 0101001b
ISH_I2C_1_SDA SDA
2.2k ohm @ 2.2k ohm
499 ohm
+3VALW_PCH 2.2k ohm
+3VS
DK19 SML0_SMBCLK 0 ohm GPU_THM_SMBCLK THM_SML1_CLK
SML0CLK 8
1k ohm
1k ohm +3VALW_PCH
SML1CLK DK17 SML1_SMBCLK
I2C_1_SDA_R 0 ohm
4.7k ohm
B B
+3VALW_EC
MEC 1515 GPIO131
PBAT_CHG_SMBCLK
4.7K ohm
100 ohm
CLK_SMB 7 SCL
BATT CONN 7-bit Address:0x0B
PBAT_CHG_SMBDAT 100 ohm
GPIO130 DAT_SMB 6 SDA 0001011x x is R/W
0 ohm
21 SDA Charger
0 ohm
SMBus Address:0b00010011(resd)
ISL95522
22 SCL
PUB01 0b00010010 (write)
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SMB/I2C Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 61 of 101
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
C C
B
Reserve B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
(RSVD)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 62 of 101
5 4 3 2 1
5 4 3 2 1
1
2 1
JKB1 CONN@ 1 R45 R43 R106 1 @ 2 0_0603_5%
1 0.5A_13.2V_MF-NSMF050-2 KBBL@ 2.2K_0201_5% 2.2K_0201_5%
<6> KB_DET# KSI7 2 1 C22
KSI6 3 2 .1U_0402_16V7K R-short 0831
PCH/I2C
2
KSI4 4 3 2
KSI2 5 4 I2C_1_SCL RC4220 2 @ 1 0_0201_5% I2C_1_SCL_R
5 <10> I2C_1_SCL
KSI5 6
KSI1 7 6 KBBL@ JKBBL1 I2C_1_SDA RC4221 2 @ 1 0_0201_5% I2C_1_SDA_R
7 <10> I2C_1_SDA
KSI3 8 R38 1
KSI0 9 8 1 2 KB_LED_DET_C 2 1
D KSO05 10 9 <10> KB_LED_BL_DET 51K_0402_5% 3 2 5 R-short 0831 D
1
KSO04 11 10 KB_BL_CTRL# 4 3 G1 6
KSO07 12 11 4 G2 +TP_VDD +TP_VDD
KSO06 13 12 R40 ACES_51575-00401-001
KSO08 14 13 100K_0201_5% I2CPAD@
14 CONN@
1
KSO03 15 CLK_TP_SIO_I2C_DAT RC4171 2 1 0_0201_5%
EC/I2C
2
KSO01 16 15 DAT_TP_SIO_I2C_CLK RC4172 2 1 0_0201_5% R42
KSO02 17 16 I2CPAD@ 100K_0201_5%
KSO00 18 17
18
2
KSO12 19
2
19
1
KSO16 20 D Q31 Q8
KSO15 21 20 2 KBBL@ 1 3 @ INT_TP#
KSO13 22 21 <58> KB_LED_PWM <7,58> TOUCHPAD_INTR#
G
S
KSO14 23 22
S
3
KSO09 24 23 LN2306LT1G_SOT23-3 +TP_VDD LN2306LT1G_SOT23-3
KSO11 25 24
KSO10 26 25
CAP_LED 27 26
28 27
28
Co-lay EC to PAD I2C/PS2
29 31
30 29GND31 32
it's used for TP I2C(EC will do PS2 virturlization)
1
30GND32 RC4225 2 @ 1 0_0201_5%
I/F to control it in ePSA mode or BIOS menu
HEFEN_AFB02-S30F1A-HF R6239 R6420
SP021707030 4.7K_0201_5% 4.7K_0201_5%
2
DAT_TP_SIO_I2C_CLK RC731 2 1 0_0201_5% DAT_TP_SIO_R
<58> DAT_TP_SIO_I2C_CLK CLK_TP_SIO_I2C_DAT CLK_TP_SIO_R
RC732 2 1 0_0201_5%
<58> CLK_TP_SIO_I2C_DAT
PS2PAD@
EC/PS2
+TP_VDD
10P_0201_50V8J
@ESD@ C24
10P_0201_50V8J
@ESD@ C25
CONN@
1 1
2 1 SP01001A900
0.1U_0402_16V7K C26 ACES_51524-0080N-001
+3VS +TP_VDD
2 2 8
R46 1 2 100K_0201_5% I2C_1_SDA_R 7 8 10
I2C_1_SCL_R 6 7 G2 9
5 6 G1
5
1
C D5 INT_TP# 4 C
R47 +5VS 1 2 TP_LOCK# 3 4
<58> PTP_DIS# DAT_TP_SIO_R 3
100K_0402_5% 2
RB551V-30_SOD323-2 CLK_TP_SIO_R 1 2
ESD depop location 1
CAP LED Control
2
JTP1
3
R2
3 1 CAP_LED_R# 2 Q12
<58> CAP_LED# DDTA144VCA-7-F_SOT23-3
S
R1
Q9
LN2306LT1G_SOT23-3
1
R48
CAP_LED_Q 1 2 CAP_LED
1K_0402_5%
R89
100K_0402_5% +5VALW
2
LED1
1 2 1 2
B
+1.8V_PRIM WHITE_LED_BAT
R26 @ 10K_0402_5% RC158 10K_0402_5% 2 1 2 1 B
R27 200_0402_5% W
3
2
AMBER_LED_BAT 2 1 4 3
R2
R28 200_0402_5% Y
<58> MASK_SATA_LED# CHG_AMBER_LED_R#
1 6 2 Q2
<58> BAT1_LED#
DDTA144VCA-7-F_SOT23-3 LTW-295DSKS-5A_YEL-WHITE~D
R1
Q15A
2
G
L2N7002DW1T1G_SC88-6
SATA_LED#_R 3 1 BATT_WHITE_LED_R#
1
S
3
5
AMBER_LED_BAT WHITE_LED_BAT 1 2
Q3 R2
C21 1U_0402_10V6K
LN2306LT1G_SOT23-3 4 3 BATT_WHITE_LED_R# 2 Q4
<58> BAT2_LED#
DDTA144VCA-7-F_SOT23-3
R1
Q15B
L2N7002DW1T1G_SC88-6
1
SATA_LED# 1 @ 2 SATA_LED#_R
R791 0_0201_5%
WHITE_LED_BAT
3
RB751S-40_SOD523-2
R30 SCS00006300
100K_0402_5% M_BIST_R R2
QZ3
+3VS <58> M_BIST_R BAT1_LED#_Q 2 LMUN5111T1G_SC70-3
+3VALW SB000010P00
2
R1
1
SATA_LED#_R RZ36 1 2
R31 1M_0201_5%
1
100K_0402_5% C
1
3
L2N7002DW1T1G_SC88-6 E
1
5 CZ218
A 2.2U_0201_6.3V6M RZ35 A
2
4
6
150_0402_5%
Q16A
2
L2N7002DW1T1G_SC88-6
SATA_LED# 2 POWER_SW_IN#
<9,68> SATA_LED# <58> POWER_SW_IN#
1
Security Classification
2018/04/01
Compal Secret Data
2019/04/01 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Keyboard/Touch Pad/Thermal/FAN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 63 of 101
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
Reserve
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
(RSVD)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 64 of 101
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
Reserve
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
(RSVD)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 65 of 101
5 4 3 2 1
5 4 3 2 1
R-Short 0716
+3VS +3VALW
Main Func = TPM RX18 1 @ 2 0_0402_5% +3VALW
0.1U_0201_10V6K
10U_0402_6.3V6M
1 1
CX1
CX2
R5 R6241
@ 0_0402_5% +3VS CX1, CX2: close to Pin1
0_0402_5%
Main Func = OTP 2 2
TPM@
TPM@
D D
2
1 TPM@ 2 TPM_SPI_IRQ#
1 2 +FP_VCC RX1 10K_0201_5%
C4 0.1U_0402_16V7K JFP1
8 1 @ 2 CPU_SPI_0_CS#2
7 8 10 RX23 10K_0201_5% UX1 @ +3VS
6 7 G2 9 1
<12> USB20_N5 6 G1 VSB
<12> USB20_P5
5 29
4 5 30 SDA/GPIO0 8 RX12 1 2 750_CTPM@ 0_0402_5%
3 4 GPIO1/SCL VHIO 22 RX15 1 TPM@ 2 0_0402_5% +3VS
3 VHIO
3
0.1U_0201_10V6K
10U_0402_6.3V6M
2 6 1 1
<58> FPR_SCAN# 2 TP80 GPIO3
0.1U_0201_10V6K
0.1U_0201_10V6K
10U_0402_6.3V6M
CX3
1 2 1 1 1
1 SPI_D1_TPM NC
CX5
CX6
CX4
<9> SPI_D1_TPM
24 3 1 @ 2 +3VALW_PCH
MISO NC
2
SPI_D0_TPM
RX11
CX7
ACES_51522-00801-001 <9> SPI_D0_TPM 21 5 RX16
MOSI/GPIO7 NC
2
TPM_SPI_IRQ# 2 2
TPM@
CONN@ 18 7 0_0402_5%
<10> TPM_SPI_IRQ# SPI_IRQ#/GPIO2 NC TP81 2 2 2
ST_CTPM@
TPM@
TPM@
SP01001AE00 9
NC
0_0201_5%
@
EU5 10
1
SPI_CLK_TPM NC
RX21 0_0201_5%
CEST523NC5VB_SOT-523-3 19 11 CX5, CX6, CX7: colse to Pin22
<9> SPI_CLK_TPM SCLK NC
2
CTPM@
ESD@ <9> CPU_SPI_0_CS#2 20 12
1
EU6 17 SCS#/GPIO5 NC 14 1 @ 2
<11,51,52,68> PLTRST# +3VALW_PCH
1
CEST523NC5VB_SOT-523-3 27 RESET# NC 15 RX17 0_0402_5%
@ESD@ 13 NC NC 26 1 CTPM@ 2
GPIO4/SINT# NC +3VS CX3, CX4: colse to Pin8
25 RX20 0_0402_5%
1
NC 28
4 NC 31
PP/GPIO6 NC 32 RX22 2 CTPM@ 1 0_0201_5%
NC
C 16 RX13 1 2 750_CTPM@ 0_0201_5% C
GND 23 RX14 1 2 750_CTPM@ 0_0201_5%
+3VALW GND 33 UX1
PGND
R6242 2 1 10K_0201_5% S IC NPCT750JABYX QFN 32P TPM FW 7.2.1.0 SA0000AQ2C0
SA0000AQ270 TPM@
+3VS
HW TPM:TPM@ S IC NPCT750JADYX QFN 32P TPM FW 7.2.2.0
FPR_SCAN# R6 2 @ 1 10K_0201_5% SW TPM:fTPM@ UX1 place colse to UC3
China TPM:CTPM
1
R54 1 2 10.5K_0402_1% ALERT# +RTC_SOC +RTC_CELL
R49 Q17
R55 1 2 2K_0402_1% T_CRIT# 2.2K_0201_5% LP2301ALT1G_SOT23-3
T_CRIT# <85> +RTC_VCC +3VLP
2
+RTC_CELL 1 3
S
B B
2
+3VS Q11B D1
G
6 1 THM_SML1_DATA R1 2
<9,58> GPU_THM_SMBDAT anode
1
D
10K_0402_5%
L2N7002DW1T1G_SC88-6 1K_0402_5% 1
G
2
cathode
1
+RTC_PWR 3
1U_0201_6.3V6M
R63
2 1 1
R50 anode
1 1
C3
2.2K_0201_5% BAS40C_SOT23-3
5
C28 Q11A C1 @
2
2
G
0.1U_0402_16V7K 0.47U_0402_6.3V6K
2
2 3 4 THM_SML1_CLK 2 D8
<9,58> GPU_THM_SMBCLK
S
L2N7002DW1T1G_SC88-6 RB751S-40_SOD523-2
1
2 1
R2
10M_0402_5%
1
NCT7718_DXP D
2N7002KW 1N SOT323-3
R64
2
Q13 U3 2 RTCRST_ON_R 1 2 RTCRST_ON
RTCRST_ON <58>
2
THM_SML1_CLK
G
1 1 1 8 G
VDD SCL 1M_0402_5%
1
Q18
LMBT3904LT1G_SOT23-3
C @ S
3
THM_SML1_DATA
100K_0402_5%
0.1U_0402_10V7K
2 C29 C30 2 7 3 1 RTC_DET# <10>
D+ SDA
2
22P_0402_50V8J
@
B 470P_0603_50V8J 2200P_0402_25V7K
D
2 2 1
R65
E 3 6 ALERT#
3
NCT7718_DXN D- ALERT#
C2
C33
T_CRIT# 4 5 Q1
2
T_CRIT# GND 2N7002K_SOT23-3 2
DIMM CPU Core
1
NCT7718W_MSOP8
Layout Note:
A
Layout Note: C30 close U3
A
1000P_0402_50V7K
0.1U_0402_10V7K
10U_0603_10V6M
CS18 1 2 0.01U_0402_16V7K SATA_CRX_C_DTX_P0 6
<12> SATA_CRX_DTX_P0 6
10P_0201_25V8
C104
@RF@
7
R-short 0831 1 1 1 1
RS28 1 @ 2 0_0201_5% HDD_DEVSLP_R 8 7
<12> HDD_DEVSLP 8 A+ S2 2
CS29
CS30
CS31
FFS_INT2_Q 9
RS33 1 @ 2 0_0201_5% 10 9
2 2 2 2 <12> HDD_DET# +5V_HDD 10
11
12 11 A- S3 3
R-short 0831 12
13
C104 place near JHDD1 14 GND GND S4 4
GND
ACES_51625-01201-001
CONN@ B- S5 5
+3V_FFS +3VS
B+ S6 6
0_0201_5% 2 FFS@ 1 RS13
GND S7 7
0.1U_0402_10V7K
10U_0603_10V6M
CS32 FFS@
CS33
1 1
US2 FFS@ +5V_HDD DEVSLP P3 8
@
LNG2DM
5V P7 10
1
2 2 10 5
9 VDD_IO RES +3VS RS31 FFS@
VDD 12 ISH_ACC1_INT# 100K_0402_5%
SA0 3 INT 1 11 ISH_ACC2_INT# ISH_ACC1_INT#
ISH_ACC2_INT#
<10>
<10>
5V P8 11
SDO/SA0 INT 2
1
FFS_SDA 4
2
FFS_SCL 1 SDA/SDI/SDO 6 FFS@ RS30 FFS_INT2_Q
SCL/SPC GND 7 100K_0402_5% 5V P9 12
GND
3
2 8
CS GND QS1B FFS@
GND P10
2
+3V_FFS L2N7002DW1T1G_SC88-6
5
1 @ 2 SA0
LNG2DMTR_LGA12_2X2 Device
RS41 0_0201_5% SA000089W00 Activity P11 9
4
6
QS1A FFS@
L2N7002DW1T1G_SC88-6
<58,68> SSD_SCP# 1 @ 2 ISH_ACC2_INT# 2
DVT 1.0 RS29 0_0201_5%
Change US2.1 and US2.4(SCL/SDA) connect
1
from PCH_SMBCLK/PCH_SMBDATA to
ISH_I2C_0_SCL/ISH_I2C_0_SDA.
DVT 1.0
Change US2.3 (SA0) connect from +3V_FFS to GND.
ISH_I2C_1_SDA 1FFS@ 2 FFS_SDA
<10> ISH_I2C_1_SDA ISH_I2C_1_SCL 1FFS@
RS38 20_0201_5% FFS_SCL SA0 1 FFS@ 2
<10> ISH_I2C_1_SCL
RS39 0_0201_5% RS40 0_0201_5%
Cancel ODD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/FFS/ODD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 67 of 101
5 4 3 2 1
+3VS_SSD +3VS
JUMP@ JPC3
80 mils 1 2
D 1 2 D
10U_0603_10V6M
0.1U_0402_10V7K
1000P_0402_50V7K
22U_0603_6.3V6M
JUMP_43X79
@ 1 1 1 1
10P_0201_25V8
C103
@RF@
CS1
CS3
CS4
CS5
2
2 2 2 2
NGFF Key M
+3VS_SSD
JSSD1
1 2
3 GND1 3.3VAUX1 4
5 GND2 3.3VAUX2 6
<12> PCIE_CRX_DTX_N8 7 PETn3 N/C1 8 1 @ 2
<12> PCIE_CRX_DTX_P8 PETp3 N/C2 SSD_SCP# <58,67>
9 10 RS2 1 @ 2 0_0201_5%
CS13 1 2 0.22U_0201_10V6K PCIE_CTX_C_DRX_N8 11 GND3 DAS/DSS# 12 RS34 0_0201_5% SATA_LED# <9,63>
<12> PCIE_CTX_DRX_N8 PCIE_CTX_C_DRX_P8 PERn3 3.3VAUX3
CS14 1 2 0.22U_0201_10V6K 13 14
<12> PCIE_CTX_DRX_P8 15 PERp3 3.3VAUX4 16
17 GND4 3.3VAUX5 18 R-Short 0831
<12> PCIE_CRX_DTX_N7 19 PETn2 3.3VAUX6 20
C <12> PCIE_CRX_DTX_P7 PETp2 N/C3 C
21 22
CS11 1 2 0.22U_0201_10V6K PCIE_CTX_C_DRX_N7 23 GND5 N/C4 24
<12> PCIE_CTX_DRX_N7 1 2 PCIE_CTX_C_DRX_P7 25 PERn2 N/C5 26
CS12 0.22U_0201_10V6K
<12> PCIE_CTX_DRX_P7 27 PERp2 N/C6 28
29 GND6 N/C7 30
<12> PCIE_CRX_DTX_N6 31 PETn1 N/C8 32
<12> PCIE_CRX_DTX_P6 33 PETp1 N/C9 34
CS9 1 2 0.22U_0201_10V6K PCIE_CTX_C_DRX_N6 35 GND7 N/C10 36
<12> PCIE_CTX_DRX_N6 1 2 PCIE_CTX_C_DRX_P6 37 PERn1 N/C11 38
CS10 0.22U_0201_10V6K
<12> PCIE_CTX_DRX_P6 PERp1 DEVSLP SSD_DEVSLP <12>
39 40
41 GND8 N/C12 42
<12> PCIE_CRX_DTX_N5 43 PETn0/SATA-B+ N/C13 44
<12> PCIE_CRX_DTX_P5 45 PETp0/SATA-B- N/C14 46
CS7 1 2 0.22U_0201_10V6K PCIE_CTX_C_DRX_N5 47 GND9 N/C15 48
<12> PCIE_CTX_DRX_N5 PCIE_CTX_C_DRX_P5 PERn0/SATA-A- N/C16
CS8 1 2 0.22U_0201_10V6K 49 50
<12> PCIE_CTX_DRX_P5 51 PERp0/SATA-A+ PERST# 52 PLTRST# <11,51,52,66>
53 GND10 CLKREQ# 54 CLKREQ_PCIE#4 <11>
<11> CLK_PCIE_N4 55 REFCLKN PEWake# 56 PCIE_WAKE# <11,51,52,58>
<11> CLK_PCIE_P4 57 REFCLKP N/C17 58
1 RS1 @ 2 GND11 N/C18
+3VS_SSD
10K_0402_5% Key M
B 67 68 SSD_SUSCLK PAD~D 1 TP@ TP196 B
69 N/C19 SUSCLK(32kHz)(O)(0/3.3V) 70
<12> M2_SSD_PEDET 71 PEDET(OC-PCIe/GND-SATA) 3.3VAUX7 72
73 GND13 3.3VAUX8 74
75 GND15 3.3VAUX9
GND17
77 76
PEDET Module Type PTH2 PTH1
LCN_DAN05-67306-0103
0 SATA CONN@
1 PCIE
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NVME SSD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 68 of 101
5 4 3 2 1
A B C D E F G H
1 1
2 2
3 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eMMC (RSVD)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 69 of 101
A B C D E F G H
5 4 3 2 1
Main Function:
D D
C C
B
Reserve B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
(RSVD)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 70 of 101
5 4 3 2 1
5 4 3 2 1
EU1
W=80mils USB3.0 Port1
USB3_CRX_L_DTX_N1 1 1 10 9 USB3_CRX_L_DTX_N1 +USB3_VCC
4.7U_0402_6.3V
22U_0603_6.3V6M
22U_0603_6.3V6M
100U_A_6.3VM_R70M
2 1 5 + @RF@
<12> USB20_P1 2 1 STDA_SSRX-
CU4
CU5
CU6
CU7
S DIO(BR) AZ1045-04F.R7G DFN2510P10E ESD C100
LU1 EMI@ ESD@ ESD@ 10 10P_0201_25V8
2
EU2 11 GND1 2 2 2 2 2
AZC199-02SPR7G_SOT23-3 12 GND2
GND3
1
1 @EMI@ 2 13
RU2 0_0201_5% GND4
1
ACON_TARAN-9R1391
CONN@
HCM1012GH900BP_4P HCM1012GH900BP_4P
3 4 3 4
2 1 2 1
C C
Maximum Output
Current 2A
+5VALW +USB3_VCC
UU1
1
5 OUT
IN 2
4 GND
<58,73> USB_PWR_EN# EN 3
1 OCB USB_OC0# <12>
CU13
1U_0201_6V3M SY6288D20AAC_SOT23-5
2
+USB3_VCC
JUSB2
1 @EMI@ 2 USB3_CTX_L_DRX_P2 9
RU7 0_0201_5% EU3 1 STDA_SSTX+
USB3_CRX_L_DTX_N2 USB3_CRX_L_DTX_N2 USB3_CTX_L_DRX_N2 VBUS +USB3_VCC
Layout Note: Close JUSB2
1 1 10 9 8
USB20_P2_R 3 STDA_SSTX-
DLM0NSN900HY2D_4P USB3_CRX_L_DTX_P2 2 2 8 USB3_CRX_L_DTX_P2 4 D+
<12> USB20_P2
3 4 USB20_P2_R
9
USB20_N2_R 2 GND_1 100 mils
3 4 USB3_CTX_L_DRX_N2 4 4 7 USB3_CTX_L_DRX_N2 USB3_CRX_L_DTX_P2 6 D-
7
STDA_SSRX+ 1
7 1 1 1 @ 1
USB20_N2_R USB3_CTX_L_DRX_P2 USB3_CTX_L_DRX_P2 USB3_CRX_L_DTX_N2 GND_2
4.7U_0402_6.3V
22U_0603_6.3V6M
22U_0603_6.3V6M
100U_A_6.3VM_R70M
2 1 5 5 6 6 5 + @RF@
<12> USB20_N2 2 1 STDA_SSRX-
CU9
CU10
CU11
CU12
C101
2
3
LU4 EMI@ 3 3 10 10P_0201_25V8
2 11 GND1 2 2 2 2 2
3
ESD@ GND2
8 12
1 @EMI@ 2 AZC199-02SPR7G_SOT23-3 13 GND3
GND4
1
CONN@
HCM1012GH900BP_4P HCM1012GH900BP_4P
3 4 3 4
2 1 2 1
A A
LU5 @EMI@ LU6 @EMI@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB3.0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 71 of 101
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
C C
B
Reserve B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
(RSVD)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 72 of 101
5 4 3 2 1
5 4 3 2 1
<58,71> USB_PWR_EN#
4
IN
EN
GND
2
<12> USB20_P7 2 1
CardReader USB20_N7_R 4
5
3
4
5
3 3 4 USB20_N7_R USB20_P3_R 6
CU16
1
OCB
SY6288D20AAC_SOT23-5
USB_OC1# <6> <12> USB20_N7 3 4
DLM0NSN900HY2D_4P
USB2.0 Port USB20_N3_R 7
8
6
7
8
1U_0201_6V3M 9
10 9
2 +USB2_VCC 1 @EMI@ 2 11 10
+RTC_VCC 11
RU14 0_0201_5% +3VS 12
13 12
+USB2_VCC 13
1 1 @EMI@ 2 14
CU17 RU15 0_0201_5% 15 14
22U_0603_6.3V6M 80 mils 16 15
@ 16
2 DLM0NSN900HY2D_4P 17
2 1 USB20_P3_R 18 GND
<12> USB20_P3 2 1 GND
ACES_51524-0160N-001
C 3 4 USB20_N3_R C
<12> USB20_N3 3 4
LU8 EMI@
1 @EMI@ 2
RU16 0_0201_5%
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Finger Print & I/O CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 73 of 101
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
C C
B
Reserve B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DOCK(RSVD)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 74 of 101
5 4 3 2 1
5 4 3 2 1
(6) +3VALW
(6) +3VALW
10k-ohm VIN
(3) B+
VOUT (3) B+
(2) +SDC_IN +3VALW_PCH
VIN CHARGER
(4) ACAV_IN1 (6) VCCDSW_EN_GPIO (7) +3VALW_PCH (7) +3VALW_PCH 0-ohm (7) +3VALW_DSW
EN VOUT
ACOK VIN (6) POK
PG
D D
(5) ALWON
+3VALW
(6) +3VALW
EN VOUT
(3) B+ 0-ohm
(10) SIO_SLP_SUS# (10) PCH_PRIM_EN
(6) +3VALW
VIN
PG (6) POK
(1) +RTC_VCC (3) B+
(5) ALWON
+5VALW
(6) +5VALW 100k -ohm
EN VOUT
VIN
PG (12) 1.8V_PRIM_PG
(3) +3VLP
+1.8V_PRIM (6) +3VALW
(7) +3VALW_PCH (10) PCH_PRIM_EN (11) +1.8V_PRIM
EN VOUT
(7) +3VALW_DSW
(3) B+
(5) ALWON 100k -ohm
100K-ohm (6) +3VALW
VBAT GPIO_172 GPIO250
10K-ohm VCI_OVRD_IN VCI_OUT VIN (15) PG_VCCIN_AUX
PG
+VCCIN_AUX
(6) POK 100K-ohm (12) 1.8V_PRIM_PG (14) +VCCIN_AUX
ACPRESENT EN VOUT
(9) PCH_DPWROK
DSW_PWROK (8) PCH_DPWROK_EC
(7) +3VALW_DSW VCC_DSW3P3 GPIO_207 for TGL 0-ohm
(6)VCCDSW_EN
GPIO_012
(6) VCCDSW_EN_GPIO
(10) SIO_SLP_SUS#
SLP_SUS# open 1.8V_Prim (6) +3VALW (3) B+ (3) B+
(7) +3VALW_PCH
C VCC_PRIM3P3 C
(20) POWER_SW_IN#
(11) +1.8V_PRIM GPIO_163/VCI_IN0# Power Button
VCCPRIM_1P8
(12) +VCC1.05_OUT_FET
VCC1P05
SLP_S5#
(22) SIO_SLP_S5#
(23) SIO_SLP_S4#
GPI0_040
EC 1515 (13) CORE_VID0
(13) CORE_VID1
(14)VCCIN_AUX_CORE_VID
VIN
+VCCST_CPU
SLP_S4# GPIO_026
(15) VCCST_EN (16) +VCCST_CPU
(24) SIO_SLP_S0# EN VOUT
SLP_S0#
SLP_S3# (24) SIO_SLP_S3# VCCST_OVERRIDE_R
GPIO_032
(6) +3VALW (24) CPU_C10_GATE#
CPU_C10_GATE# SLP_VCCST_OVRD (12) +VCC1.05_OUT_FET
(24) SIO_SLP_S3#
Level
100k-ohm (13) CORE_VID1 (13) CORE_VID1
VCCST_PWRGD
Shifter (27) IMVP_VR_EN +VCCSTG_CPU
CORE_VID1 GPIO_033 (24) CPU_C10_GATE#
EN (32) +VCCSTG_CPU
VCCST_OVERRIDE_R UZ3 VOUT
B VCCST_OVERRIDE B
(28) IMVP_VR_ON_P
(6) +3VALW
open VCCIN
(32) CPUPWRGD
0-ohm VIN
+3VS
10ms 10ms
delay delay (24) SIO_SLP_S3# (25) +3VS
(30) IMVP_VR_PG EN VOUT
(31) PCH_PWROK (34) PCH_PLTRST# (35) PCH_PLTRST#_EC
PCH_PWROK PLTRST#
+5VS
(26) RUNPWROK (33) SYS_PWROK
SYS_PWROK
(ALL_SYS_PWRGD) (24) SIO_SLP_S3# (25) +5VS
EN VOUT
Reserve AND gate (25) +3VS
VIN
(6) +5VALW
(33) SYS_PWROK 10K-ohm
GPIO_106/PWROK delay
All_SYS_PWRGD power down use S3 off
(26) RUNPWROK
(ALL_SYS_PWRGD) (24) SIO_SLP_S3#
GPIO_057/VCC_PWRGD Buffer
UZ1
(25) 1.2V_VTT_PWRGD
A
(3) B+ A
VIN
PG (30) IMVP_VR_PG
+VCCIN
(28) IMVP_VR_ON_P (29) +VCCIN
EN VOUT
Security Classification
2018/04/01
Compal Secret Data
2019/04/01 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
(RSVD)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 75 of 101
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
Reserve
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
(RSVD)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 76 of 101
5 4 3 2 1
5 4 3 2 1
JPWR1 CONN@
1
POWER_SW#_MB 2 1
for S5 LID LID_CLOSE# 3 2
RC4197 1 S5LID@ 2 0_0402_5% +3V_LID 4 3
+3VLP 4
D D
+3VALW RC4216 1 LID@ 2 0_0402_5% 5
R25 1 2 100_0402_5% LID_CLOSE# 6 GND1
<38,59> NB_LID# for normal LID close GND2
<58> POWER_SW#_MB JXT_FP226H-004S1AM
SP01002BJ00
1 @ESD@
2
1000P_0402_50V7K
TST71-N-220-T170-S017_2P
EC1
ED1
2
SW1
@ AZ5125-02S.R7G_SOT23-3
@ESD@
1
For EMI Reserved
@ESD@
LID_CLOSE# EC2 1 2 0.1U_0402_10V7K
C PCB PN C
H1 H3 H4 H5 H6 H7 H8 1 ZZZ PCB R1
22U_0603_6.3V6M
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
C27
DA8001NI000
2 DISPCB@
1
H_5P6N G2
ACES_50224-00401-001
H_3P0 H_3P0X4P0 H_3P2-G CONN@
H_3P0-G SP02000GC10
B B
HCPU1 HCPU2 HCPU3 HCPU4
HOLEA HOLEA HOLEA HOLEA
1
CPU
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWRBTN/PCB PN//SCREW/FAN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 77 of 101
5 4 3 2 1
5 4 3 2 1
0.1U_0201_6.3V6K
1 +3VALW
6 9 +3VS
VIN2 VOUT2
@ESD@
7 8
VIN2 VOUT2
1
VCCDSW_EN_GPIO
CZ8
1M_0201_5%
1
15
@ RZ5
@ CZ9
1 1
0.1U_0402_25V6
D 07/4 ESD require 2 GPAD DZ3 D
CZ10
1U_0201_6.3V6M EM5209VF_DFN14_3X2 CZ11 RZ7 1 @ 2 0_0201_5% 2 1 VCCDSW_EN_Q RZ29 1 @ 2 0_0201_5%
<58> VCCDSW_EN
2
0.1U_0402_10V7K
2
2 2 RB751S-40_SOD523-2
R-short 0831 SCS00006300
DZ4
1 2
<78,82,85> POK
RB751S-40_SOD523-2
SCS00006300
+3VALW TO +3VALW_PCH
JP8
CZ15 2 1
Always Short +3VALW_PCH
UZ4 +3VALW_PCH
DVT1
1U_0201_6.3V6M JP1 JUMP@
+3VALW 1
2 VIN VOUT
7
8
+3VALW_PCH_OUT 1
1 2
2
+3VALW +3VALW_PCH
VIN VOUT
1
JUMP_43X79 CZ38
VCCDSW_EN_GPIO RZ8 1 2 0_0402_5% 3 6 RZ32 1 2 0.1U_0402_16V7K
<59> VCCDSW_EN_GPIO ON CT 1
1
CZ16
1 1 0.1U_0402_10V7K 100K_0402_5% RZ33
+5VALW
4 @ 100K_0402_5%
2
VBIAS
5
CZ18 5 CZ19 2
1 GND
0.22U_0402_16V7K CZ20 9 1000P_0402_50V7K PCH_DPWROK_EC 1
P
<58,59> PCH_DPWROK_EC
2
2 1U_0201_6V3M GND 2 B 4 PCH_DPWROK
O PCH_DPWROK <11>
1 POK 2 1
IMVP_VR_ON&VCCST_PWRGD
A
G
2 TPS22967DSGR_SON8_2X2
CZ40 UZ14 CZ39
3
0.22U_0402_16V7K MC74VHC1G08EDFT2G_SC70 @ 100P_0402_50V8J
2 2
SA0000BIP00
+3VS
2nd should pick CMOS And gate
1
RZ9
R-short 0831 10K_0402_5%
2
RZ10 1 @ 2 0_0201_5% ALL_SYS_PWRGD
<86> 1.2V_VTT_PWRGD ALL_SYS_PWRGD <58,85>
0.1U_0201_16V6K
C C
2
+3VALW
@ESD@
CZ21
+3VALW 07/4 ESD require DZ2 CZ1
@ CZ17 1 2 0.1U_0402_16V7K 2 1
1 2 1
RB751S-40_SOD523-2 UZ1
0.1U_0201_16V6K SCS00006300 1 5
NC VCC
5
SIO_SLP_S3# 1 RZ2 2 2
1 10K_0402_1% A 4 ALL_SYS_PWRGD
1
P
UZ5 2 @ 100P_0402_50V8J
3
2nd should pick CMOS And gate Buffer with Open Drain Output For H_VCCST_PWRGD
UC34
5
MC74VHC1G08EDFT2G_SC70 +3VALW +1.05V_VCCST
SIO_SLP_S3# 1
SA0000BIP00
P
B 4 IMVP_VR_ON_P 0.1U_0402_16V7K 2 1 CZ12
O
1
2
<58> IMVP_VR_EN A
G
UZ3 RZ6 @
3.3Valw 1 5 100K_0201_5%
R-short 0831
3
NC VCC
IMVP_VR_ON_P 2
Change to pop 1.05V
2
A
1
RC282 1 @ 2 0_0201_5% IMVP_VR_ON_EN <88>
4 1
Y VCCST_PWRGD <11>
1 2 RC284 3
GND
0.1U_0402_10V7K
@ RC283 0_0201_5% 100K_0201_5% 2 CZ13 @
@ESD@
CZ14
Change to pop 74AUP1G07GW_TSSOP5 100P_0201_25V8J
VCCSTG 2
2
DVT2_0618 1
+VCC1.05_OUT_FET
+VCC1.05_OUT_FET
DVT1_17
VCCST +3VALW_PCH
+3VALW_PCH
+3VALW_PCH
+3VALW_PCH
UZ8 SIO_SLP_S3# RC4228 1 2 0_0201_5% VCCST_EN_R
1
1
1 +VCCSTG_CPU +3VALW_PCH
VIN1 1
B 2 CZ28 @ RZ20 B
VIN2 0.1U_0201_10V6K 100K_0201_5% CZ29 @
1
+5VALW 7 6 +VCCSTG_R 1 @ 2 2 @ 0.1U_0201_10V6K
VIN thermal VOUT 0_0603_5% RZ17 RZ21 2
5
3 100K_0201_5% UZ11@
VBIAS @ SIO_SLP_S3# 2
R-short 0831
G Vcc
3.3_VCCST_OVERRIDE <11,38,78> SIO_SLP_S3# A VCCST_EN_R
RZ1414 2 @ 1 0_0402_1% VCCSTG_EN 4 5 4
<11> CPU_C10_GATE#
2
ON GND +VCCSTG_CPU VCCIN_AUX_CORE_VID 1 Y
B
6
AOZ1334DI-01_DFN8-7_3X3 D 3.3_VCCST_OVERRIDE RC4215 1 @ 2 0_0201_5% 74LVC1G32GW_TSSOP5
R-short 0831
3
VCCST_OVERRIDE_R# 2 QM1A@ SA000014S00
STG@ 1
STG@ QM1B @ G L2N7002DW1T1G 2N SC88-6
3
CZ25 L2N7002DW1T1G 2N SC88-6 D
0.1U_0201_10V6K <11> VCCST_OVERRIDE_R
5 S +VCCSTG_CPU
1
2 G
1
SB00000PV00
RZ22 S
4 1 @ 2
100K_0201_5% RZ31 0_0603_5%
SB00000PV00
+VCC1.05_OUT_FET
+1.2V_VDDQ TO +1.2V_VCCPLL_OC
2
UZ12
1 +1.05V_VCCST
2 VIN1
VIN2
+5VALW 7 6 +VCCST_R 1 @ 2
VIN thermal VOUT RZ23 0_0603_5%
VCCST_OVERRIDE_R#
to XDP R-short 0831 3
VCCST_OVERRIDE_R# <79> VBIAS
VCCST_EN_R VCCST_EN
R-short 0831
RZ24 1 @ 2 0_0402_1% 4 5 +1.05V_VCCST
ON GND
AOZ1334DI-01_DFN8-7_3X3 1
CZ31
0.1U_0201_10V6K
2
+VCC1.05_OUT_FET
+3VALW_PCH
+3VALW_PCH 1
1 CZ33
1U_0201_6.3V6M
CZ30 @ 2
0.1U_0201_10V6K
2
DVT1_17
5
UC9
2 SN74AUP1G97DRLR truth table
G Vcc
A A
74LVC1G32GW_TSSOP5 RZ27 @
3
SA000014S00 100K_0201_5%
@
2
+VCCIO_OUT
C XDP_PRDY# 1 C
<7> XDP_PRDY# TP147
CMC@TP@
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Debug connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 79 of 101
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 80 of 101
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 08, 2021 Sheet 81 of 100
5 4 3 2 1
A B C D
S
D
5A Z150 20M 1210_2P PSID-2 PSID-3 1 2 PS_ID <58>
8 +19V_ADPIN 1 2
GND 7
GND
1000P_0402_50V7K
1
6 PSID@ PR4
2200P_0402_50V7K
1000P_0402_50V7K
2200P_0402_50V7K
2
10P_0402_25V8J
100P_0201_50V8J
6
100K_0402_1%
1
TVNST52302AB0_SOT523-3
5 10K_0402_1% PR5 PSID@
100P_0201_50V8J
5
@ESD@ PC6
PSID@ PR3
4 2 1 2.2K_0402_5%
4
+5VALW
3
EMI@ PC1
EMI@ PC2
@ESD@ PC5
EMI@ PC3
EMI@ PC4
3
@RF@ PC15
3 2
2
2
@ESD@ PD1
1 1 2
1
1 @EMI@ PL2 C 1
PQ2
5A Z150 20M 1210_2P PSID-1 2
ACES_50458-00601-001 B
1
@PJP2 E @ PR7
3
+5VALW
1
PR6 PSID@
1 2 3
PSID@
100_0402_5%
15K_0402_1%
1 2 1 2 1
JUMP_43X79 EMI@ PL3 2
BLM15AG102SN1D_2P
PSID 1 2 @ PD2
2
BAV99W_SC70-3
1
@ PD3
BAV99W_SC70-3
3
+5VALW
3 3
1
be removed by end user <11,58,63,84,96> HW_ACAV_IN 0_0402_5%
3.3K_1206_5%
1
1 2
H_PROCHOT#
@ PR32
+19V_VIN +3VALW
10K_0402_1%
<7,16,58,84,88> H_PROCHOT# @ PR34
1
1M_0402_1%
3 2
PR33
@ PR35
2
3
PC13 0_0402_5%
L2N7002DW1T1G_SC88-6
.1U_0402_16V7K 1 2
2N7002KDW_SOT363-6
1
PQ12B
@ PQ13B
2
PR36 1 2 5 POK <78,85> 5
6
@ PC14 1M_0402_1%
1
.1U_0402_16V7K
2N7002KDW_SOT363-6
L2N7002DW1T1G_SC88-6
4
1
1
D
@ PQ13A
2
<58,83,84> PBAT_PRES#
PQ12A
1 2 2 @ PQ11 PR40 2 @ PR38
G 2N7002KW_SOT323-3 2 100K_0402_1% 1M_0402_1%
1
100K_0402_1%
S
3
2
1
2
@ PR45
2
PR43
PR44 1M_0402_1%
4 1M_0402_1% 4
@
2
2
1
DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2018/04/01 Deciphered Date 2019/04/01 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_DCIN CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 08, 2021 Sheet 82 of 100
A B C D
A B C D
1 1
+17.4V_BATT+
1
@ PJP3
2
+17.4V_BATT++
1 2
JUMP_43X79
EMI@ PL4
5A Z150 20M 1210_2P
1 2
10P_0402_25V8J
1
1000P_0201_50V7K
0.01UF_0402_25V7K
1
1
@RF@ PC16
EMI@ PC11
EMI@ PC12
@ESD@ PD5 @ESD@ PD6
L03ESDL5V0CG3-2_SOT-523-3-X L03ESDL5V0CG3-2_SOT-523-3-X
PIN1 GND
2
PIN2 GND
PIN3 GND
3
2 2
PBAT_PRES# <58,82,84>
PIN4 SYS_PRES
PIN5 BATT_PRS
@ PBATT1
PIN6 DAT_SMB 1
1
PIN7 CLK_SMB 2
2
3 PR39 PR41
PIN8 Batt+ 3
4
4 SYS_PRES PR37 200_0402_5% 10K_0402_1% +3VALW
5 PBAT_PRES#_R 1 2 1 2
PIN9 Batt+ 5 6 DAT_SMB
100_0402_5%
1 2
PIN10 Batt+ 6
7
7 CLK_SMB 1 2
8
SP021412220 8 9 PR42
9 10 100_0402_5%
10 11
ACES_50458-01001-P01_10P-T GND 12 PBAT_CHG_SMBCLK <58,84>
GND
ACES_50458-01001-P01
PBAT_CHG_SMBDAT <58,84>
99.9
3 3
4 4
DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2018/04/01 Deciphered Date 2019/04/01 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_BATT CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 08, 2021 Sheet 83 of 100
A B C D
A B C D
1M_0402_1%
2
PRB04
Effective
PQB11 PQB12
PRB02
+19VB Lgate LDO output
0.01_1206_1%
2N7002KW_SOT323-3
EMB04N03H_EDFN5X6-8-5 AON7506_DFN3X3-8-5 capacitance Capacitance
1
1 1 1 4 EMI@ PLB02 (post-
1
2 D 2 5A_Z80_0805_2P
+19V_VIN +CHARGER_SRC derating)
PQB30
5 3 2 3 5 2 3 1 2
2200P_0402_25V7K
G
1000P_0402_25V8J
1000P_0402_25V8J
0.1U_0402_25V7K
@ PJPB01
15U_B2_25VM_R100M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
S
3
1 PRB03 2
1 2
3M_0402_5%
10P_0402_25V8J
1 1nF 0.4uF
4
1 2
1
+
PCB70
PCB20
PCB21
EMI@ PCB22
EMI@ PCB23
EMI@ PCB24
EMI@ PCB25
EMI@ PCB26
EMI@ PCB27
@RF@ PCB72
JUMP_43X118
1 2nF 0.4uF 1
2
@ 2
5nF 0.4uF
6.5nF 0.4uF
0.1U_0402_25V6
PCB01 @
1
10nF 0.4uF
3
PRB11 PRB12
1_0402_1% 2_0402_5% @ESD@ PDB13
AZ4024-02S_SOT23
5
CSIP_CHG
CSIN_CHG
PQB13
15nF 0.8uF
AON7506_DFN3X3-8-5 PD14
1
PCB03
0.1U_0402_25V6 3
1 2 BGATE_CHG 4 1
20nF 0.8uF
1
1
PRB07 PRB08 @
4.02K_0402_1% 4.02K_0402_1% +19V_VIN PCB04 PCB05 AZ4024-02S_SOT23 25nF 1uF
0.47U_0402_25V6K
3
2
1
1
0.033U_0402_25V7K 1U_0402_25V6K @ESD@
2
2
PCB28
ASGATE_CHG
CMSRC_CHG
0.1U_0402_25V7K
30nF 1uF
2
1
@
2
PCB06
PRB09
374K_0402_1%
LRB715FT1G_SOT323-3
2 1
PDB01
2
BA_PWR 3
100K_0402_5%
@ PRB14
1
1 <96> ACIN_CHG 0_0603_5%
2 2
2
PRB13
@ PDB14
0.01UF_0402_25V7K
+19V_VIN
PCB02
PRB10
2N7002KW_SOT323-3
RB751V-40_SOD323-2
1
1
D 52.3K_0402_1%
PQB31
2
<58> AC_DIS
2
BOOT1_CHG
G
2
5
S
3
2
1
PRB45
ACIN_CHG
NTC_CHG
UG1_CHG
LX1_CHG
LG1_CHG
AON7408L_DFN8-5
1
100K_0402_1% PRB39
4.7_0402_5%
2 VDD_CHG
PQB26
PRB15 1
10_1206_5% UG1_CHG 4 +17.4V_BATT+_R
2
PCB07 PUB01
16
15
14
13
12
11
10
33
2
9
4.7U_0603_25V6K ISL95522HRZ-T_TQFN32_4X4
2 1 DCIN_CHG ACIN
CSIN
NTC
GND
BOOT
CSIP
UGATE
PHASE
LGATE
PCB19
3
2
1
PRB16 75K_0402_1%
VDDP_CHG
Vmax=5.8V
2 1 17 8 1 2 PRB01
PCB08 DCIN VDDP PLB01
0.01_1206_1%
1 2 VDD_CHG 18 7 ASGATE_CHG 4.7UH_5.5A_20%_7X7X3_M
PRB17 150K_0402_1% VDD ASGATE 2.2U_0402_16V6K LX1_CHG 1 2 1 4
1
1 2 PROG_CHG 19 6 QPCN_CHG
2.2U_0402_16V6K PROG QPCN
2
PRB18
1
200K_0402_1%
ACLIN_CHG 20 5 CMSRC_CHG
2 3 +17.4V_BATT+
PRB25 PCB18
ACLIM CMSRC
1
499K_0402_1% @ PRB19 0.47U_0402_25V6K
4.7_1206_5%
5
1 2 0_0402_5% 21 4 QPCP_CHG 1 2
@EMI@ PRB40
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
AON7506_DFN33-8-5
2
1
<58,83> PBAT_CHG_SMBCLK
PCB30
PCB31
PCB32
PCB33
PCB34
1SNUB1_CHG 2
1
CSOP_CHG
PQB25
1@ PRB21 2 0_0402_5% 23 2
768K_0402_1%
PRB38
<7,16,58,82,88> H_PROCHOT# PROCHOT# CSOP LG1_CHG 4
PRB26
22.6K_0402_1%
2
24 1 CSON_CHG
BATGONE
PROH
ACOK CSON
680P_0402_50V7K
BGATE
CCLIM
@
BMON
AMON
COMP
1 ACOK_CHG
PSYS
2
VBAT
2
@ PRB22 0_0402_5%
3
2
1
@EMI@ PCB29
@ PRB23 PCB09
25
26
27
28
29
30
31
32
3 100K_0402_1% 10P_0402_50V8J 3
2
PRB24 1 2 1 2
100K_0402_1%
BGATE_CHG
COMP_CHG
BATGONE_CHG
VBAT_CHG
2 1
<58,82,83> PBAT_PRES#
PRB31
PRB27 200K_0402_1%
1
VDD_CHG 1 2 PQB28
3
LMUN5113T1G_SOT323-3
0_0603_5%
PRB28 100K_0402_1%
1 2
PRB41
2
2
0_0402_5%
PRB29 @ PCB17
1 2 0_0402_5% 1U_0402_25V6K @
<58> I_BATT_R
2
1 2
PQB29
2200P_0402_25V7K
1
100_0402_5%
LTC015EUBFS8TL_UMT3F
1
1
PRB36 2_0402_5%
10.5K_0402_1%
1
1 2
PCB10
PRB30
0_0402_5%
0.1U_0402_25V6
0.1U_0402_25V6
560P_0402_50V7K
1
PRB33
1
1
PRB34
2
PCB13
PCB15
I_ADP_R
2
BA_PWR
PCB12
PRB37
2
@ <11> SIO_SLP_S5#
2
@ 1 2 0_0402_5%
0.033U_0402_25V7K
2
1
3
PCB11
PRB42
VDD SE000013780 2.2uF_0402_16V 0.55uF 0.4uF
1
10K_0402_5% PRB43
160K_0402_1%
1
4 PRB44 D 4
2
10K_0402_5% 1 2 2 PQB32
G Close to EC ADP_I pin
VDDP SE000013780 2.2uF_0402_16V 0.55uF 0.4uF
0.047U_0402_25V7K
RUM002N02GT2L_VMT3
2
1
RUM002N02GT2L_VMT3
1
@ PCB14
PCB36
D S
3
PQB33
PROH 2 0.1U_0402_25V6
CBOOT SE00000WA00 0.47uF_0402_25V 0.22uF 0.2uF
2
G
2
S
3
LA-F611PR01_0531B.DSN
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2016/01/06 Deciphered Date 2017/01/06 Title
I_SYS change to TSENSE_PSYS(P.72 PUZ01.24) PWR_CHARGER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: Monday, March 08, 2021 Sheet 84 of 100
A B C D
A B C D E
1 1
@EMI@ PL311
HCB2012KF-121T50_2P PR302
1 2 499K_0402_1%
ENLDO_3V5V 1 2 +19VB
@ PR301 PC307
@ PJP301 0_0603_5% 0.1U_0402_10V7K
1
150K_0402_1%
1 2 +19VB_3V BST_3V 1 2 BST_3V_R 1 2
+19VB
1
PR303
JUMP_43X39 PC317
2200P_0402_50V7K
10U_0603_25V6M
10U_0603_25V6M
1000P_0402_25V8J
1000P_0402_25V8J
0.1U_0402_25V6
PU301 1U_0402_25V6K
2
5
1
10P_0402_25V8J
SY8286BRAC_QFN20_3X3
2
BS
IN
IN
IN
IN
1
1
@RF@ PC318
@EMI@ PC301
EMI@ PC302
PC303
PC304
EMI@ PC305
@EMI@ PC306
LX_3V 6 20 PL301
LX LX 1.5UH_9A_20%_7X7X3_M
2
2
@ 7 19 LX_3V 1 2
GND LX +3VALWP
@EMI@ PR305
8 18
GND GND
4.7_1206_5%
+3VLP
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
9 17
PG LDO
1
PC310
PC311
PC312
PC313
PC314
PC316
10 16
NC NC
4.7U_0402_6.3V6M
3VALWP
OUT
2
EN2
EN1
21
NC
FF
GND
1
TDC 6 A
PC308
@ @ @
1 SN_3V 2
PR304
Peak Current 8.5 A
11
12
13
14
15
680P_0402_50V7K
10K_0402_1%
@EMI@ PC309
1 2
+3VALWP OCP Current 10 A
ENLDO_3V5V
2 2
2
<78,82> POK
3
@ESD@ @ PJP302
3
@EMI@ PL511
5A Z150 20M 1210_2P
1
1 2
@ PJP502
@ PR501 1 2
@ PJP501 0_0603_5% PC507 +5VALWP 1 2 +5VALW
1 2 +19VB_5V BST_5V 1 2 BST_5V_R
1 2 JUMP_43X79
+19VB 1 2
JUMP_43X79 0.1U_0402_10V7K @ PJP503
2200P_0402_50V7K
1000P_0402_25V8J
1000P_0402_25V8J
1 2
PU501 1 2
10U_0603_25V6M
10U_0603_25V6M
10P_0402_25V8J
0.1U_0402_25V6
1
SY8288CRAC_QFN20_3X3 JUMP_43X79
1
1
@RF@ PC522
@EMI@ PC501
EMI@ PC502
PC503
PC504
EMI@ PC505
@EMI@ PC506
BS
IN
IN
IN
IN
LX_5V 6 20 PL501
2
@ LX LX 1.5UH_9A_20%_7X7X3_M
7 19 LX_5V 1 2
GND LX +5VALWP
4.7_1206_5%
8 18
GND GND
1
3 3
@EMI@
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PR505
9 17 1 2
PG VCC
1
PC510
PC511
PC514
PC512
PC519
PC513
PC520
PC521
10 16 PC508
@ PR502 NC NC 4.7U_0402_6.3V6M
OUT
LDO
1 SN_5V 2
2
EN2
EN1
0_0402_5% 21
FF
EN_3V 1 2 GND @ @ @
680P_0402_50V7K
11
12
13
14
15
@ PR504
VL
@EMI@ PC509
10K_0402_1%
EN_5V 1 2 +3VALWP 1 2
ENLDO_3V5V
4.7U_0402_6.3V6M
2
1
4.7U_0402_6.3V6M
@ PR503
1
EN_5V
PC2506
PC515
0_0402_5% POK
PR506
2
2.2K_0402_5%
5VALWP
2
1 2
<58> ALWON
@ TDC=6 A
2N7002KW_SOT323-3
PQ501 Peak Current 8 A
1 2 3 1 OCP current 10 A
S
<66> T_CRIT#
4.7U_0402_6.3V6M
@ PR507
1
0_0402_5%
G
2
PC516
<58,78> ALL_SYS_PWRGD
2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_3.3VALWP/5VALWP
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 08, 2021 Sheet 85 of 100
A B C D E
A B C D
1
@EMI@ PLM11 TDC 1.2A
HCB2012KF-121T50_2P PCM12 +1.2VP Peak Current 1.5A
1 2 0.1U_0402_10V7K
2
1 1
+19VB @ PJPM01
+19VB_1.2V UG_1.2V
1 2
+0.6VSP
JUMP_43X39
10U_0603_25V6M
10U_0603_25V6M
10P_0402_25V8J
1000P_0402_50V7K
1000P_0201_50V7K
2200P_0402_50V7K
0.1U_0402_25V6
22U_0603_6.3V6M
1
1
LX_1.2V
@EMI@ PCM22
@EMI@ PCM23
EMI@ PCM01
EMI@ PCM02
PCM03
PCM04
@RF@ PCM24
PCM20
16
17
18
19
20
2
2
@ PUM01
2
VLDOIN
PHASE
UGATE
BOOT
VTT
21
PAD
LG_1.2V 15 1
LGATE VTTGND
PRM03
9.76K_0402_1% 14 2
PGND VTTSNS
1
2 1
PQM01
D1
D1
D1
G1
AONH36334_DFN3X3A8-10 CS_1.2V 13 3
PCM13 CS RT8207PGQW _W QFN20_3X3 GND
10 9 2.2U_0402_6.3V6M
D1 D2/S1 2 1 VDDP_1.2V 12 4 VTTREF_1.2V
PRM04 VDDP VTTREF
5.1_0603_5%
G2
S2
S2
S2
1 2 VDD_1.2V 11 5
VDD VDDQ +1.2VP
1
PGOOD
5
8
2 1 PCM19
TON
2 +5VALW 0.033U_0402_16V7K 2
FB
S5
S3
2
1
1
@ PDM01 PRM05
10
6
PCM14 RB751V-40_SOD323-2 2.2_0603_5%
2.2U_0402_6.3V6M
2
@ PCM17
EN_0.6VSP
EN_1.2V
FB_1.2V
2
TON_1.2V
220P_0402_25V8J
1 2
+5VALW
PLM01
1UH_11A_20%_7X7X3_M <78> 1.2V_VTT_PWRGD PRM10
1 2 6.04K_0402_1%
+1.2VP @ PRM06
+19VB_1.2V 1
PRM07 1 2
+1.2VP
10K_0402_1% 2
1 2
+3VALW 453K_0402_1% +1.2V_DDR
1
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
@ PRM08 PRM11
@ PCM18 TDC 5.5 A
.1U_0402_16V7K Peak Current 7.8 A
1
1
PCM05
PCM06
PCM07
PCM08
PCM09
PCM10
2
1 2
4.7_1206_5%
<78,86> +2.5V_PG OCP Current 9.4 A
2
2
1
@ @ PCM15
0.1U_0402_10V7K
SN_1.2V
2
@ PRM09
0_0402_5%
1
1 2
<8> 0.6V_DDR_VTT_ON
@EMI@ PCM11
1
3 680P_0402_50V7K @ PCM16 3
2
0.1U_0402_10V7K
@ PJPM02
2
1 2 +5VALW _VDD 1 2
+5VALW +1.2VP 1 2 +1.2V_DDR
PR2504 JUMP_43X118
1
2.2_0402_1% PC2504
2.2U_0402_6.3V6M
2
4 5
GND
+3VALW
1 2 +3VALW _2.5V 3
VIN VOUT
6 +2.5VP 1 2
ADJ_2.5V
+0.6VSP +0.6V_DDR_VTT
JUMP_43X39 2 7 JUMP_43X39
22U_0603_6.3V6M
22U_0603_6.3V6M
EN ADJ
1
1
1
1 8
PC2501
PC2502
PGOOD GND PR2502 @ PC2505
21.5K_0402_1% 0.01U_0402_25V7K
2
PU2501
2
RT9059GSP_SO8 @ PJP2502
1 2
+2.5VP +2.5V_MEM +2.5V
PR2501 +2.5V_PG <78,86> Vref=0.8V JUMP_43X39 TDC 0.32 A
1
2 1 EN_2.5V
<11,78> SIO_SLP_S4# Peak Current 0.45 A
2
PC2503
4 4
1
2
+3VALW
Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
Issued Date 2018/04/01 Deciphered Date 2019/04/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+1.2V_MEN/+0.6V/+2.5VP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 08, 2021 Sheet 86 of 100
A B C D
A B C D
@ PL1811 @ PJP1802
HCB2012KF-121T50_2P JUMP_43X79
1 2 1 2
1
PU1801 +1.8VALWP 1 2 +1.8V_PRIM 1
11
10 TP 1 PL1801
@ PJP1801 PVIN NC 1UH_6.6A_20%_5X5X3_M
1 2 +3VALW_1.8V 9 2 LX_1.8V 1 2
+3VALW PVIN LX
+1.8VALWP
JUMP_43X39 8 3
SVIN LX
22U_0603_6.3V6M
7 4 1.8V_PRIM_PG <16,58,91>
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
NC PGOOD
1
PC1801 PC1807
1
6 5
PC1802
PC1803
PC1804
2 FB EN PR1803 @EMI@ PR1804 22P_0402_50V8J +1.8V_PRIM
2
100K_0402_5% 4.7_1206_5% TDC 1.6 A
2
RT8061AZQW_WDFN10_3X3 @
Peak Current 2.3 A
2
EN_1.8V
1
FB=0.6Volt OCP Current 2.8A
2 1
@ PR1801 +3VALW
0_0402_5% PR1807
1 2 20K_0402_1%
<78> PCH_PRIM_EN
1
@EMI@ PC1806
0.1U_0402_10V7K
1
680P_0402_50V7K PR1805
PC1805
2
1
@ PR1802 10K_0402_1%
1M_0402_5%
2
2
@
2
FB_1.8V
2 2
3 3
4 4
+1.05V_VCCST
0.1U_0402_25V6
1
1
45.3_0402_1%
75_0402_1%
100_0402_1%
PCZ01
PRZ04
PRZ02
PRZ03
2
@ PRZ01
2
D 0_0603_5% D
1 2 VR_SCLK VDD_VCCIN 1 2
<14> VR_SVID_CLK
@ 0_0402_5% PRZ06 +5VALW
<14> VR_SVID_ALERT# 1 2 VR_ALERT# PRZ05
@ 0_0402_5% PRZ07 0_0603_5%
0.22U_0402_25V6K
1 2 VR_SDA VIN_VCCIN 1 2
<14> VR_SVID_DATA +19VB_VCCIN
1U_0402_25V6K
@ 0_0402_5% PRZ08
<7,16,58,82,84> H_PROCHOT# PRZ09
1
100_0402_1%
PCZ02
PCZ03
1 2 1 2
2
@ PCZ04 47P_0402_50V8J 1.91K_0402_1% PRZ11
1 2
+3VS
<11> VR_READY
0_0402_5% @ PRZ13
<78> IMVP_VR_ON_EN 1 2
32
31
30
29
28
27
26
25
330P_0402_50V8J 4700P_0402_25V7K PROG1_VCCIN 1 2
1 2 1 2
VR_ENABLE
VR_READY
SCK
SDA
VDD
VIN
VR_HOT#
ALERT#
PROG2_VCCIN 1 2
UGATE2
1U_0402_25V6K
PHASE2
8200P_0402_25V7K
LGATE2
1K_0402_5%
BOOT2
1
ISEN1
ISEN2
ISEN3
FCCM
1 2 1 2 33 GND_PAD
PCZ08
PCZ09
2
68P_0402_50V8J
9
10
11
12
13
14
15
16
1 2
PCZ10 PRZ21
PRZ46 100_0402_5% 270P_0402_50V7K 2K_0402_1% LG_VCCIN2 <89>
+VCCIN 1 2 1 2 2 1 LX_VCCIN2 <89>
UG_VCCIN2 <89>
<14> VCC_SENSE_VCCIN BST_VCCIN2 <89>
@ PRZ43 PCZ12 PRZ22
PCZ11 0_0402_5% 820P_0402_50V7K 499_0402_1% @ PRZ45 0_0402_5%
1 2 1 2 1 2 1 2 1 2
+5VALW
0.082U_0402_16V7K
ISEN2 <89>
330P_0402_50V7K ISEN1 <89> @ PRZ24
1
PCZ13
1 2 1 2 20M_0402_5%
1 2
PCZ15 0.022U_0402_25V7K
PCZ16 0.022U_0402_25V7K
@ PRZ44 @ PRZ49 PRZ23
2
1
2.61K_0402_1%
0.047U_0402_25V7K
0.015U_0402_25V7K
0.1U_0402_25V6
330P_0402_50V7K
<14> VSS_SENSE_VCCIN
PRZ25
11K_0402_1%
PRZ47 100_0402_5%
1
1 2
2
1
1
PCZ40
PCZ18
PCZ19
PRZ26
PRZ27
PHZ02 near PLZ01 Choke Side
1
475_0402_1%
2
1 2 @ PHZ02
Local sense put on HW site
2
B 10K_0402_5%_B25/50 4250K B
PCZ20 PRZ28
2200P_0402_50V7K 3.48K_0402_1%
2
1 2 1 2 ISUMN <89>
1 2
PCZ21
0.01U_0402_16V7K
A A
DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
2014/11/05 2014/12/15 Title
Issued Date Deciphered Date PWR_VCCIN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 08, 2021 Sheet 88 of 100
5 4 3 2 1
5 4 3 2 1
Baseline Baseline
UP3_4+2 15W (U42) UP3_4+2 28W (U42)
Frequency 750KHz ICCMAX=47A ICCMAX=55A
D
TDC=30A TDC=36A D
EMI@ PLZ11
5A Z150 20M 1210_2P
1 2
+19VB_VCCIN
@
<88> UG_VCCIN1 PJZ01 +19VB
1 2
1 2
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_25V7K
33U_D2_25VM_R60M
JUMP_43X118
EMI@ PCZ22
EMI@ PCZ25
PCZ26
PCZ27
1000P_0402_50V7K
1000P_0402_50V7K
0.1U_0402_25V6
1 1
33U_25V_M
5
1
+ +
@EMI@ PCZ28
@EMI@ PCZ29
PCZ23
PCZ24
PQZ1
PRZ29
AON6380_DFN5X6-8-5
2
0_0603_5% 2@ 2
1 2 BST_VCCIN1_R
<88> BST_VCCIN1 4
1 PCZ30
0.22U_0402_25V6K
+VCCIN
2
3
2
1
Rdc=0.9mohm PLZ01
1 4
<88> LX_VCCIN1
2 3
PQZ2
@EMI@ PRZ31
4.7_1206_5%
5
1
ISUMP 1 2
<88> ISUMP 0.15UH_NA__35A_20%
AON6314_N_DFN56-8-5
1
PRZ34
3.65K_0603_1%
PRZ32
1 SNUB_VCCIN1 2
4 100K_0402_1%
<88> LG_VCCIN1
2
ISEN1
<88> ISEN1
3
2
1
V2N 1 2
C C
PRZ35
@EMI@ PCZ31
100K_0402_1%
680P_0402_50V7K
2
ISUMN 1 2 V1N
<88> ISUMN
PRZ33
10_0402_1%
+19VB_VCCIN
<88> UG_VCCIN2
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
EMI@ PCZ32
EMI@ PCZ33
PCZ34
PCZ35
1000P_0402_50V7K
1000P_0402_50V7K
0.1U_0402_25V6
5
1
@EMI@ PCZ36
@EMI@ PCZ37
PQZ3
PRZ37
AON6380_DFN5X6-8-5
2
0_0603_5%
B 1 2 BST_VCCIN2_R B
<88> BST_VCCIN2 4
1
PCZ38
0.22U_0402_25V6K
2
3
2
1
+VCCIN
Rdc=0.9mohm PLZ02
1 4
<88> LX_VCCIN2
2 3
PQZ4
4.7_1206_5%
@EMI@ PRZ38
5
ISUMP 1 2
0.15UH_NA__35A_20%
AON6314_N_DFN56-8-5
PRZ41
3.65K_0603_1% PRZ39
100K_0402_1%
1SNUB_VCCIN2 2
4
<88> LG_VCCIN2
2
ISEN2
<88> ISEN2
3
2
1
V1N 1 2
@EMI@ PCZ39
PRZ42
680P_0402_50V7K
100K_0402_1%
2
ISUMN 1 2 V2N
PRZ40
10_0402_1%
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_VCCIN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 08, 2021 Sheet 89 of 100
5 4 3 2 1
4
3
2
1
@
PCZ107
330U_D2_2.5VY_R9M
2
1
+
PCZ97
330U_D2_2.5VY_R9M
2
1
+
+VCCIN
+VCCIN
A
A
2 1 2 1
PCZ77
@
PCZ89 PCZ100 330U_D2_2.5VY_R9M
47U_0603_6.3V6M 22U_0603_6.3V6M 2
1
+
2 1 2 1
@
PCZ101 PCZ98
47U_0603_6.3V6M 22U_0603_6.3V6M
+VCCIN
2 1 2 1
2 1
@
PCZ88 PCZ81
@
PCZ76 47U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1
2 1
PCZ85 PCZ79
@
PCZ92 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1
2 1
330U_R9
PCZ96 PCZ102
@
PCZ75 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1
2 1
PCZ99 PCZ90
*2
@
PCZ91 22U_0603_6.3V6M 22U_0603_6.3V6M
22U_0603 *14
1U_0201_6.3V6M 2 1 2 1
Primary side :
2 1
@
Main Func = VCCIN/ VCCIN_AUX
PCZ93 PCZ80
@
PCZ94 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1
2 1
@
PCZ95 PCZ84
@
PCZ78 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1
@
PCZ83 PCZ87
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
PCZ82 PCZ86
B
B
22U_0603_6.3V6M 22U_0603_6.3V6M
2
1
+
2 1 2 1 2 1 PCG45
330U_D2_2.5VY_R9M
+VCCIN_AUX
+VCCIN_AUX
C
C
2
1
+
2 1 2 1 2 1 PCG46
330U_D2_2.5VY_R9M
@
Issued Date
2 1 2 1 2 1
Security Classification
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
2 1 2 1 2 1
22U_0603
2018/04/01
PCG24 PCG23 PCG70
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
*1
*25
PCG27 PCG69
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
PCG28 PCG19
22U_0603_6.3V6M 22U_0603_6.3V6M
D
D
Deciphered Date
2019/04/01
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Date:
Title
Document Number
Sheet
90
PWR_VCCIN/ VCCIN_AUX
Compal Electronics, Inc.
of
100
Rev
0.1
4
3
2
1
5 4 3 2 1
D D
EMI@ PLG3
5A Z150 20M 1210_2P
2 1
1
ICCMAX=26A
1
PRG1 1 2
2.2_0603_5% PCG2 PRG2 1 2
0.1U_0402_25V6 0_0805_5% TDC=10A
2200P_0402_50V7K
2
JUMP_43X118
EMI@ PCG58
EMI@ PCG61
DC LL=TBD
10U_0603_25V6M
10U_0603_25V6M
0.1U_0402_25V6
1000P_0402_50V7K
2
1
PCG62
PCG59
OCP is Lowside MOSFET Rdson sense
1
1
1
@EMI@ PCG63
@EMI@ PCG64
AC LL=TBD
1000P_0402_50V7K
BST_AUX
2
0.1U_0402_25V6
2
2
2
5
1
226K x1.2 PQG4
PCG1
255K x1.4
2
PUG1
AON6380_DFN5X6-8-5
10
RT6543AGQW_WQFN20_3X3 PRG38 0_0603_5%
PRG4 UG_AUX 1 2 UG_AUX_R 4 +VCCIN_AUX
BOOT
187K_0402_1%
1 2 CS_DSI_RT6543 1 20 VSYS_RT6543 Rdc=1.19mohm
CS_DIS VSYS
C C
+5VALW PLG2
3
2
1
0.24UH_22A_+-20%_ 7X7X3_M
@ PRG6 0_0603_5%
1 2 PVCC_RT6543 15 11 UG_AUX LX_AUX 1 4
PVCC UGATE
2 1 ISENSEP_AUX 2 3 ISENSEN_AUX
PCG5 1U_0402_6.3V6K PQG3
1
5
1
PRG7 5.1_0603_5%
@EMI@ PRG32
0_0603_5%
4.7_1206_5%
1 2 VCC_RT6543 16 12 LX_AUX
PRG33
VCC PH
AON6314_N_DFN56-8-5
2 1
PCG6 1U_0402_6.3V6K PRG8 @
1 AUX_SNUB
2
2
100K_0402_1% LG_AUX 4
High > 1V +3VALW 1 2 PG_VCCIN_AUX 4
PGOOD LGATE
13 LG_AUX
1ISENSEP_AUX_R
Low <0.4V <58> PG_VCCIN_AUX
1
@
0_0402_5%
@EMI@ PCG57
PRG11
3
2
1
680P_0402_50V7K
PRG37
1 2 EN_RT6543 19 14
<16,58,87> 1.8V_PRIM_PG EN PGND
2
1
10.7K_0603_1%
2
0_0402_5% PCG9
0.1U_0402_25V6 @ PRG12 0_0402_5%
PRG35
2
2
PRG36
@ PRG39 PRG34
2
0_0402_5% 1 2 1 2
@ PRG14 0_0402_5%
ISENSEN_RT6543_R
+3VALW <16,78> AUX_VID0
AUX_VID0 18 3 ISENSEN_RT6543 1 2 ISENSEN_RT6543_R 1.15K_0402_1% 1.5K_0402_1%
1
VID0 ISENSEN
PCG11 +VCCIN_AUX PHG2
1 2
@ PRG16 @ ISENSEN_AUX_NTC 1 2
PRG17 PRG18
100K_0402_1% 0.1U_0402_25V6
1 2 FSWSEL_RT6543 9 8 VOUT_RT6543 1 2 0_0402_5% 2 1 10K_0402_1%_B25/50 3370K
+5VALW FSWSEL VOUT
ISENSEP_RT6543_R
1
100_0402_1% B=3435(B25/85)
@ PRG21 PCG12
B 100K_0402_1% B
2000P_0402_50V7K PRG23 10K_0402_1% @ PCG13 390P_0402_50V7K @ PRG24 1.6K_0402_1%
1
5 COMP_RT6543 1 2 1 2 1 2 1 2 1 2
COMP
2
AUX_VID0 FB_RT6543
6 1 2 1 2
AUX_VID1
5V: 800KHz FB
1
Float: 600KHz PRG27
GND: 400KHz 0_0402_5%
1
7 RGND_RT6543 1 2
RGND VSS_SENSE_AUX <16>
AGND
@ PRG28
2
@ PRG29 PRG30 0_0402_5%
10K_0402_1% 10K_0402_1%
1
VCC_SENSE_AUX <16>
PRG31
2
21
1
100_0402_1%
PCG16
@ PCG17 0.1U_0402_25V6
2
2
1 2
0.082U_0402_16V7K
330P_0402_50V7K
@ PCG18
2 1
VCCIN_AUX VID Follow Intel PDG Rev0.71 @PCG29
1 2
1 0 1.65
A A
1 1 1.8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR VCCIN_AUX
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 08, 2021 Sheet 91 of 100
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 08, 2021 Sheet 92 of 100
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 08, 2021 Sheet 93 of 100
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 08, 2021 Sheet 94 of 100
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 08, 2021 Sheet 95 of 100
5 4 3 2 1
5 4 3 2 1
@ PC902
0.01UF_0402_25V7K
1 2
D +3VLP D
AZV3002
@ PR902 Icc=12uA_max
200K_0402_1%
1 2 Vout=3.15V@Vcc=3.3V and Io=3mA
Vth 1.80V-1.86V-1.93V @ PR903 @ PR901
300K_0402_1% 0_0402_5%
1 2 @ PU900 1 2 ACIN_CHG <84>
L2N7002DW1T1G_SC88-6
AZV3002RL-7_U-FLGA8_1P65X1P65
8
@ PC901 @ PD901
82P_0201_50V8J RB520SM-30T2R_EMD2-2-X
VCC
3
1 2
@ PQ900B
2
+VCCIN @ PR904 IN-1 - 1 NO_SMOKE_OVP 5
OUT1
1U_0201_6.3V6M 1U_0201_6.3V6M
1U_0201_6.3V6M 1U_0201_6.3V6M
200K_0402_1% 3
C IN+1 + C
1
@ PC908
@ PC909
1 2
4
L2N7002DW1T1G_SC88-6
@ PR905 6
-
2
IN-2
6
100K_0402_1% 7
1 2 5 OUT2
IN+2 +
@ PQ900A
@PR906 @ PC903 NO_SMOKE_UVP 2
VEE
0_0402_5% 82P_0201_50V8J
1
@ PC910
@ PC911
1 2 1 2
1
4
+19VB
2
3 @ PR907
2
237K_0402_1%
1 1 2
@ PD902
+3VLP 2 @ PR908 RB520SM-30T2R_EMD2-2-X
43.2K_0402_1%
1
@ PD900 1 2 RB520SM
BAT54CW_SOT323-3
@ PC904
Vf =0.29V@1mA
82P_0201_50V8J @ PR909 Ir =1uA @Vr=10V
1 2 14.7K_0402_1%
B 1 2 B
HW_ACAV_IN <11,58,63,82,84>
@ PC905
1 2
0.22U_0402_10V6K
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NO SMOKE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 08, 2021 Sheet 96 of 100
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 08, 2021 Sheet 97 of 100
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 08, 2021 Sheet 98 of 100
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 08, 2021 Sheet 99 of 100
5 4 3 2 1
5 4 3 2 1
PCZ77=330UF
PCZ79/80/81/82/84/85/86/87/90/96/98/99/100/102=22uF
VCCAUX
Output caps 1+9
PCG46=330UF
PCG19/24/28/50/51/65/71/75/76=22uF
PRZ14/25=2.21Kohm
B PRZ13/24=2.05kohm B
PRZ17/26=3.01Kohm
PRZ48=37.4Kohm
PRZ66=200ohm
PRZ49=12.1Kohm
PRZ53=14.7kohm
PCZ10=82pF
PCZ11=220pF
"
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Changed-List PWR History
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 08, 2021 Sheet 100 of 100
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EE_Change list
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Docum ent Num ber Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K034P
Date: M onday, M arch 08, 2021 Sheet 101 of 101
5 4 3 2 1