RF Performance of AlGaN/GaN High-Electron-Mobility Transistors Grown on Silicon (110)

Diego Marti, C. R. Bolognesi

+
, Yvon Cordier
1
, Magdalena Chmielowska
1
, and Mohammed Ramdani
1
Millimeter-Wave Electronics Group, ETH-Zu rich, Gloriastrasse 35, CH-8092 Zu rich, Switzerland
1
Centre de Recherche sur lHe te ro-Epitaxie et ses Applications, Centre National de la Recherche Scientifique,
Rue B. Gre gory, Sophia-Antipolis, 06560 Valbonne, France
Received April 30, 2011; accepted May 14, 2011; published online June 2, 2011
We report the first microwave performance for AlGaN/GaN HEMT structures grown by molecular beam epitaxy on Si(110) high-resistivity
substrates. Transistors were fabricated with gate lengths of 50, 75, and 100 nm, achieving short-circuit current cutoff frequencies as high as
f
T
70 GHz and maximum oscillation frequencies of f
MAXU
93 GHz. Because complementary metaloxidesemiconductor (CMOS) technology
is compatible with (110) substrates, this demonstration establishes a foundation for the future integration of GaN devices into mainstream CMOS
on a common Si(110) platform. # 2011 The Japan Society of Applied Physics
M
uch eort is being focused on the growth of gallium
nitride (GaN)-based structures on silicon substrates
because of their advantages in terms of cost and
large wafer size availability. Until now, the (111) orientation,
which provides a hexagonally symmetric surface has been
preferred for GaN-based devices grown on silicon because it
is better suited to the epitaxial growth of a wurtzite phase.
Several reports concerning the performance of high-electron-
mobility-transistor (HEMT) structures have established the
interest of this approach.
19)
Nevertheless, the use of silicon
substrates could become of even greater interest if GaN-
based devices were developed on substrates with orientations
used in mainstream silicon technology. Among these, the
(001) orientation presently oers advantages for processing
and integration. However, the square symmetry of the
Si(001) surface and the presence of two types of terraces
with a (2 1) reconstruction alternately rotated by 90

makes the growth of hexagonal GaN more dicult because it

necessitates the use of substrates with a 25

mis-orientation.
Also, more complicated schemes are required to grow crack-
free GaN lms on the (001) Si face, which have a thickness
presently limited to about 1 m and lower crystal qual-
ity,
1012)
leading to limited transistor performances such as
cut-o frequencies of f
T
= 28 GHz and f
MAX
= 46 GHz,
13)
and more recently f
T
= 37 GHz and f
MAX
= 55 GHz, and a
power density up to 2.9 W/mm at 10 GHz.
14)
On the other hand, other silicon substrate orienta-
tions such as (110) are also compatible with MOSFET
fabrication processes and are presently of interest in silicon
electronics because they can oer superior channel transport
properties in advanced metaloxideeld-eect-transistors
(MOSFETs) and could thus enhance the speed of comple-
mentary MOS (CMOS) circuits.
15)
Studies on GaN-based
blue-light-emitting diodes,
16)
long-gate transistors
17)
and
other structures
18)
grown on Si(110) have shown character-
istics comparable to those obtained on Si(111). In the present
work, the DC and RF performance of short-gate-transistor
AlGaN/GaN HEMTs grown on (110) high-resistivity (HR)
Si is reported for the rst time.
The HEMT epilayer structure for this work was grown on
a 2-in. Si(110) HR ( > 5 kcm). The sample was grown
by molecular beam epitaxy (MBE) in a Riber Compact 21
system using ammonia as the nitrogen precursor. Prior to
growth, the substrate oxide was etched in HF/H
2
O and the
wafer was rinsed in deionized water before loading into the
reactor. After the growth of a 43-nm-thick AlN nucleation
layer at 920

C, a stress-mitigating stack is deposited

consisting of 250 nm Al
0:15
Ga
0:85
N (grown at 800

C) and
250 nm AlN (grown at 920

C). Then, a 1.7 m GaN layer

was grown at 800

C, followed by the device active layers.

The HEMT barrier layers consist of a 1 nm AlN spacer to
reduce alloy scattering and enhance the electron mobility,
and an 18 nm undoped Al
0:29
Ga
0:71
N barrier. Finally the
device structure is completed by a 3 nm GaN cap layer.
The main structural and electrical properties of the above
structure are reported in Table I. The full width at half
maximum (FWHM) values of the GaN(0002) and GaN(302)
peaks deduced from the X-ray diraction (XRD) rocking
curve on Si(110) are 1044 and 1764 arcsec, respectively.
The latter is directly connected to the density of threading
dislocations which, according to our previous studies,
19)
is
less than 4 10
9
/cm
2
in the present growth. The mean
strain state of the sample was evaluated by measuring the
bow of the wafer with a stylus prolometer. The convex bow
of the sample indicates slow strain relaxation during the
growth of the thick GaN buer layer, attesting to the quality
of the underlying layers, as previously detailed elsewhere.
19)
Capacitancevoltage (CV) measurements were performed
with a mercury probe to establish the presence of a two-
dimensional electron gas (2DEG) at the AlN/GaN interface
and to study the charge control in the heterostructure. The
2DEG sheet carrier density of N
S
= (0:9{1:0) 10
13
cm
2
is consistent with expected values for the aluminum content
of the AlGaN barrier and previous results on Si(111). The
variation of capacitance in the pinch-o region (V
P
voltage
around 5 V) allows one to deduce an n-type residual carrier
density of about 1 10
14
cm
3
in the GaN buer layer. The
room-temperature low-eld electron transport properties
Table I. Structural and electrical properties of the AlGaN/GaN
heterostructure grown on Si(110).
Substrate Si(110)
GaN thickness (m) 1.7
FWHM XRD (002) (arcsec) 1,044
FWHM XRD (302) (arcsec) 1,764
Substrate bow (m) 50
N
S
(CV) (cm
2
) 1 10
13
V
P
(V) 5:3
GaN background doping, n (cm
3
) 1 10
14
N
S
(Hall) (cm
2
) 9:70 10
12
(Hall) (cm
2
V
1
s
1
) 2,047
+
E-mail address: colombo@ieee.org
Applied Physics Express 4 (2011) 064105
064105-1 # 2011 The Japan Society of Applied Physics
DOI: 10.1143/APEX.4.064105
measured by Hall measurements on van der Pauw structures
reveal that sheet carrier densities of N
S
= (9:1{9:7)
10
12
cm
2
are obtained in agreement with previous CV
measurements. The corresponding electron mobility is
greater than 2,000 cm
2
V
1
s
1
and compares favorably with
the results we previously reported.
1719)
The AlGaN/GaN HEMTs were fabricated by metal
evaporation of Ti/Al/Mo/Au to form ohmic contacts,
followed by a rapid thermal annealing in a H
2
/N
2
forming
gas environment at 850

C. In the second step, mesa

isolation was established by the plasma etching procedure
described in another publication.
20)
TLM measurements
reveal a contact resistance of 1.1 mm and a sheet
resistance of R
SH
= 252 /. T-gates were aligned in the
center between the 1 m sourcedrain spacing by a two-step
electron beam lithography process in a trilayer photoresist
stack consisting of ZEP/PMGI/ZEP. The gate electrodes
consist of a Ni/Pt/Au metallization stack with gate lengths
of L
G
= 50, 75, and 100 nm. The gate stem height and head
width were 120 and 400 nm, respectively. After O
2
plasma
cleaning of the surface, the transistors were passivated with a
75-nm-thick layer of PECVD-deposited SiN
x
. The pattern-
ing of the passivation layer was done by reactive ion etching
with a SF
6
gas chemistry, and the contact pads were nally
formed by Ti/Au overlay metallization.
The DC device characteristics for 75-nm-gate transistors
are shown in Figs. 1 and 2. A maximum drain current of
1.2 A/mm is measured at V
GS
= 0 V and a peak transcon-
ductance of g
m
= 250 mS/mm is obtained at V
GS
= 4:5 V
and V
DS
= 6 V. The gate leakage amounts to 7.5 A/mm at
V
G
= 7 V. The DC performance for all three gate lengths
L
G
of 50, 75, and 100 nm was very similar.
RF measurements were carried out from 0.2 to 40.2 GHz
with an HP8510C vector network analyzer using an LRRM
calibration with o-wafer impedance standards. Before de-
embedding, f
T
= 44 GHz and f
MAX
= 39 GHz. Pads were de-
embedded with on-wafer open/short calibration structures.
Figure 3 shows the transistor microwave performance at the
peak f
T
bias of V
GS
= 4:5 V and V
DS
= 6 V. Extrapolation
of [h
21
[
2
and of Masons unilateral gain U with a 20
dB/dec roll-o yields f
T
= 70 GHz and f
MAX(U)
= 93 GHz.
A comparison of the cuto frequencies f
T
and f
MAX(U)
versus
the gate footprint L
G
, as depicted in Fig. 4, shows the best f
T
for the shortest gate length, whereas for f
MAX(U)
the highest
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0 1 2 3 4 5 6
D
r
a
i
n

C
u
r
r
e
n
t
,

I
D

[
A
/
m
m
]
Voltage Drain, V
DS
[V]
0 V
2 V
4V
6 V
V
GS
= 0 to 6 V (1 V Steps)
2 x (0.075 x 75)
2
m
Fig. 1. Drain characteristic of a 75-nm-gate HEMT measured for V
GS
= 0
to 6 V, in steps of 1 V. The maximum drain current density is
I
DS
= 1:2 A/mm for V
DS
= 0:5 V.
0
0.3
0.6
0.9
1.2
1.5
0
50
100
150
200
250
300
-7 -6 -5 -4 -3 -2 -1 0
D
r
a
i
n

C
u
r
r
e
n
t
,

I
D

[
A
/
m
m
]
T
r
a
n
s
c
o
n
d
u
c
t
a
n
c
e
,

G
M

[
m
S
/
m
m
]
Gate Voltage, V
GS
[V]
V
DS
= 0.5 to 5 V (0.5 V Steps) 2 x (0.075 x 75) m
2
Fig. 2. Transfer characteristic of a 75-nm-gate HEMT for V
DS
= 0:5 to
5 V, in steps of 0.5 V. The peak transconductance is 250 mS/mm at gate-
source voltage V
GS
= 4:5 V.
0
5
10
15
20
25
30
35
40
1 10 100
G
a
i
n

[
d
B
]
Frequency [GHz]
MSG
U
|h
21
|
2
f
T
= 57 GHz
f
MAX(U)
= 93 GHz
2 x (0.075 x 75) m
2
V
GS
= 4.5 V / V
DS
= 6 V
Fig. 3. Microwave performance at V
DS
= 6 V and V
GS
= 4:5 V for the
75 nm HEMT. The extrapolation of [h
21
[
2
and of unilateral gain U at
20 dB/dec yields f
T
= 57 GHz and f
MAX(U)
= 93 GHz.
30
40
50
60
70
80
90
100
110
40 50 60 70 80 90 100 110 120
f
T
f
MAX(U)
C
u
t
o
f
f

F
r
e
q
u
e
n
c
y

[
G
H
z
]
Gate Length, L
G
[nm]
2 x (L
G
x 75)
2
m
Fig. 4. Dependence of f
T
and f
MAX(U)
on gate length L
G
for gate lengths
ranging from 50 to 100 nm.
D. Marti et al. Appl. Phys. Express 4 (2011) 064105
064105-2 # 2011 The Japan Society of Applied Physics
value is achieved for the intermediate gate length of 75 nm,
which can be explained as a trade-o between increased gate
resistance at smaller gate lengths as well as lower f
T
for
larger gate footprints.
We provided the rst demonstration of fully passiviated
AlGaN/GaN HEMTs grown on an HR silicon substrate in
the (110) orientation for transistors with gate lengths ranging
from 50 to 100 nm. Despite a high contact resistance of
1.1 mm, the devices show good DC characteristics and
cuto frequencies as high as f
T
= 70 GHz and f
MAX(U)
=
93 GHz. A comparison of various gate lengths has shown,
that the best f
T
can be achieved with a gate length of 50 nm,
whereas the best f
MAX(U)
was for gate length of 75 nm. The
results indicate that is possible to fabricate GaN HEMTs on
a Si(110) substrate, suggesting that GaN epitaxy on (110) Si
provides a promising avenue for the future integration of
GaN and mainstream CMOS technology on a (110) Si
platform.
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