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    © All Rights Reserved
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    22 views45 pages

    Ixys S A0001802845 1

    Uploaded by

    mstrkoski
    Datasheet

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
    Flag for inappropriate content
    of 45
    — PRELIMINARY PRODUCT SPECIFICATION Z86E04/E08 CMOS Z8 OTP MICROCONTROLLERS PRODUCT DEVICES Part Oscillator Operating Operating ROM Number Type Voc Temperature (ke) Package ZB6E0412PEC Crystal ABV AO°CO5°S i TePin DIP ZB6E0412PSC1866 Crystal a5V-5.5V_ orcr7O°C 1 18-Pin DIP ZB6E0412PSC1903 RC 45V55V O°C770°C 1 Te-Pin DIP Z@6EO412PEC1903 RC, 45V-5.5V =AO°CHO5°S 1 18Pin DIP ‘ZBBEO412SEC Crystal 45V-55V —AOCHIO5*C 1 76-Pin SOIC 286E04128SC1866 Crystal 45V-5.5V OCTOC 7 18-Pin SOIC ‘Z86E0412SSC1903 RC 45V-5.6V OCI70C 1 18-Pin SOIC ‘ZB6E04T2SEC1903 RC. 45V-6.8V _~40°C/105°C 1 18-Pin SOIC. ZB6EOB12PEC Crystal a5V-5.5V 40°C 105°C 2 18-Pin DIP ‘266E0612PSC1866 Crystal aeV-55V OC/70°C 2 iePin OF ZB6E0B12PSC1903 RC 45V-5.5V O°CH7O*C 2 16-Pin DIP ZB6E0812PEC1903 RC ASV-5.5V =40°C/105°C 2 16-Pin DIP ZB6E08125EC Crystal 45V-55V AO°CIOS*C. 2 18-Pin SOIC ‘ZB6E0812SSC1866 Crystal 4V5.5V O°C/70°C 2 18-Pin SOIC ‘786E0812SSC1903 RC. 45V-5.8V DCO 3 18-Pin SOIC ‘Ze6E0812SEC1903 RC, 45V-5.5V =AP°CHO5C 2 18-Pin SOIC ‘Several key product features of the extensive family of Zilog Z86E04/E08 CMOS OTP microcontrollers are presented in the above table. This table enables the user to identify which of the E04/E08 product variants most closely match the us- es application requirements. $$ ee Ds97zax1104 PRELIMINARY 1 Za6E04/E08 ‘CMOS Z8 OTP Microcontrollers Zilog eee FEATURES 14 InpuyOutput Lines Six Vectored, Prioritized Interrupts (G falling edge, 1 rising edge, 2 timers) Two Analog Comparators Program Options: ~ Low Noise = ROM Protect — Auto Latch = Watch-Dog Timer (WOT) ~ EPROMTest Mode Disable Two Programmable 6-Bit Counter/Timers, Each with 6-Bit Programmable Prescaler WDT/ Power-On Reset (POR) On-Chip Oscillator that Accepts XTAL, Ceramic Resonance, LG, RC, or Extemal Clock Clock-Free WOT Reset Low-Power Consumption (50 mw typical) Fast Instruction Pointer (1s @ 12 MHz) RAM Bytes (125) GENERAL DESCRIPTION Zilog’s Z86E04/ED8 Microcontrollers (MCU) are One-Time Programmable (OTP) members of Zilog's single-chip Z8° MCU family that allow easy software development, debug, prototyping, and small production runs not economically, desirable with masked ROM versions. For applications demanding powerful YO capabilities, the Z86E04/E08's dedicated input and output lines are ‘grouped into three ports, and are configurable under soft- ware control to provide timing, status signals, or parallel vo. ‘Two on-chip counteritimers, with a large number of user selectable modes, offload the system of administering real-time tasks such as countingfiming and VO data com- ‘munications. PRELIMINARY Note: All Signals with an overline, “~, are active Low, for ‘example: BAW (WORD is active Low); B/W (BYTE is active Low, only). Power connections follow conventional descriptions be- low: ‘Connection Clreult Device Power Vos oo. Ground GND Vss. Ds97zax1104 Z96E04/E08 Zilog MOS Z8 OTP Microcontrollers Input XTAL Veo GND Register Pointer General-Purpose Register File vo wo (Bit Programmable) Figure 1, Functlonal Ds97Z8x1104 ELIMINARY Za6E04/E08 (CMOS 28 OTP Microcontrollers Zilog GENERAL DESCRIPTION (Continued) 7-0 ROM PROT Low Noise Pat Figure 2. EPROM Programming Mode Block Diagram —— PRELIMINARY Ds97zaxti04 Zilog PIN DESCRIPTION Figure 3, 18-Pin EPROM Mode Configuration Table 1. 18-Pin DIP Pin Identification 286E04/E08 (MOS ZB OTP Microcontrollers Peg P23 P25, P22 P26 Pat Por P20 Veo GND xTALa Po Pot P00 P33 XTALY P3t Figure 4. 18-Pin DIP/SOIG Mode Configuration Table 2. 18-Pin DIP/SOIC Pin Identification EPROM Programming Mode Standard Mode Pint Symbol Function Direction pin Symbol Function Direction 4 _De07T _Data4,5,6,7 In/Oulput_ 7=q_paa-Pa7_Pont2, Pins 45,6,7 _InvOutput ; Voc a ‘Supply 5 Voo Power Supply SEH aeeceaNG) is Connect oni HeE-eaetieeEc 16 XTAL2 Crystal Osc. Clock Output Tt cipenave eit} rat — ett one Close one OE Output Enable Input a Pat Port, Pin 1, ANT Tput a EPM EPROM Prog Mode Input 9 P32, Port, Pin 2, AN Input a Vee Prog Voltage Input 10 P33, Port 3, Pin 3, REF Tnput nN Glear Clear Clock Input TI-13_“POO-PO2 Port 0, Pins 0.1.2 InfOutput 2 Clock ‘Address Input 14 GND Ground SSS 13 FGM Prog Mode Input 5-18 _P20-P23__Port2,Pins0,1,2,3 __In/Output 4 GND Ground i518 B0-03___Data0,t,2,3 __In/Output Ds97Zex1104 PRELIMINARY Zilog en ABSOLUTE MAXIMUM RATINGS ‘Stresses greater than those listed under Absolute Max mum Ratings may cause permanent damage to the de- vice. This s a stress rating only; functional operation of the device at any condition above those indicated in the oper- ational sections of these specifications is not implied. Ex- posure to absolute maximum rating conditions for an ex- tended period may atfect device reliability, Total power dissipation should not exceed 462 mW for the package. Power dissipation is calculated as follows: Total Power Dissipation = Vop x floo-(Sum of lox)] ++ Sum of [(Yoo-Vow) loud + SUM Of (Vou x lou) Parameter Min Max Units Note ‘Ambient Temperature undor Bias 40 105 c Storage Temperature 65 +150, Cc Voltage on any Pin with Respect 10 Ves 07 +12 Vv i Voltage on Vp Pin with Respect 10 Veg 08 7 Vv Voltage on Pins 7, 8, 9, 10 with Respect 10 Veg 06 Vooe Vv 2 Total Power Dissipation 1.65 Ww Maximum Allowable Current out Of Vag 300 mA Maximum Allowable Current into V>5, He 220. 2~OmA Maximum Allowable Current into an input Pin 600 +600 BA 3 Maximum Allowable Current into an Open-Drain Pin 0) +600 yA 4 Maximum Allowable Output Current Sinked by Any VO Pin 25 mA Maximum Allowable Output Current Sourced by Any VO Pin 25 mA ‘Total Maximum Output Current Sinked by a Port 60 mA Total Maximum Output Current Sourced by a Port co mA Notes: 4. This applies to al pins except where otherwise noted. Maximum current into pin must bo + 600 WA. 2. There s no input protection diode from pin to Veo(rot applicable to EPROM Mode). 3. This excludes Pin 6 and Pin 7. 4, Device pin is not at an output Low state. 6 PRELIMINARY DS97Z8x1104 Zilog ‘STANDARD TEST CONDITIONS ‘The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to Ground. Positive current flows into the referenced pin (Fig ure §). 286E04/E08 (MOS ZB OTP Microcontrollers From Output Under Test It tr Figure 5. Test Load Diagram CAPACITANCE T, = 25°C, Vg = GND = OV, f = 1.0 MHz, unmeasured pins returned to GND. Parameter ‘Max input capacitance 10 pF Output capacitance 20 pF WO capacitance 25 pF DS97zax1104 PRELIMINARY Z96E04/E08 ‘CMOS 28 OTP Microcontrollers Zilog DC ELECTRICAL CHARACTERISTICS Standard Temperature Tr=0°Cto470°C Typical Sym Parameter Vec{4] Min Max @26°C Units Conditions Notes: Vinwax Max Input Voltage _46V 72 V_ 1250 pA 7 Sav 2 Vo y<250 pA 1 Vox Clock Input High 45V O8Vcq Voct03 28 V_Drivenby External Voltage Clock Generator BEV 08Voc Vecr03 28 V_Drivenby External Clock Generator Vo. Glock input Low 4BV_ Vag-0S O02Veg 17 V_ Driven by External Voltage Clock Generator BEV Ves-O3 O2Vcg 4.7 V Driven by External Clock Generator Va‘ WnputHighVollage ——«4EV— 2.3 Hysteresis, voc@ soy ‘Z86E04/E08 CMOS 28 OTP Microcontrollers control to be inputs or outputs, independently. Bits pro- grammed as outputs can be globally programmed as eF ther push-pull or open-drain (Figure 8). Port 2 (V0) Auto Latch Option. 5 1 1 I 4 Figure 8. Port 2 Configuration Ds97zaxti04 PRELIMINARY 24 Z86E04/E08 ‘CMOS Z8 OTP Microcontrollers Zilog PIN FUNCTIONS (Continued) Port 3, P83-P31. Port 3 is a 3-bit, CMOS-compatible port These three input lines are also used as the interrupt with three fixed input (P33-P31) lines. These three input sources IRQO-IRQS, and as the timer input signal Tiy (Fig- lines can be configured under software control as digital ure 9). ‘Schmitt-rigger inputs or analog inputs. ze j<-<—__. Port 3 0 = Digtal R247 = POM. 1 = Analog [oy] — TIN a ol. }—B P31 Data Latch CK BEERS eareeeeeaeae Pe EEE EEE: P31 (AN) aN. t j IRs — ne P32 Data Latch , 4 Y IRQO Poe AD (AN2) 33 (REF) -——> P33 Data Latch Reel IRQ 0,1,2 = Falling Edge Detection IRQ3 "= Rising Edge Detection Figure 9. Port 3 Configuration PRELIMINARY (897Z8x1104 Zilog Comparator Inputs. Two analog comparators are added to input of Port 3, P31, and P32, for interface flexibility. The. comparators reference voltage P33 (REF) is common to both comparators. Typical applications for the on-board comparators; Zero ‘crossing detection, A/D conversion, voltage scaling, and threshold detection. In Analog Mode, P33 input functions, serve as a reference voltage to the comparators. ‘The dual comparator (common inverting terminal) features a single power supply which discontinues power in STOP Z86E04/E08 CMOS Z8 OTP Microcontrollers Mode. The common voltage range is 04 V when the Veg is 6.0V; the power supply and common mode rejection ra- tios are 90 dB and 60 dB, respectively. Interrupts are generated on either edge of Comparator 2's output, or on the falling edge of Comparator 1's outpul. ‘The comparator output is used for interrupt generation, Port 3 data inputs, or Ty through P31. Alternatively, the ‘comparators can be disabled, freeing the reference input, (P33) for use as IRQ1 and/or P33 input. FUNCTIONAL DESCRIPTION ‘The following special functions have been incorporated into the 28 devices to enhance the standard Z8 core archi- tecture to provide the user with increased design flexibility. InTose POR (Cold Stan) Par {Stop Mode) RESET. This function is accomplished by means of a Pow- er-On Reset or a Watch-Dog Timer Reset. Upon power- up, the Power-On Reset ctcult waits for Toon ms, plus 18 lock cycles, then starts program execution at address (000 (Hex) (Figure 10). The 28 control registers’ reset val- Ue is shown in Table 3. XTALOSC hip Reset Figure 10, Internal Reset Configuration Power-On Reset (POR). A timer circuit clocked by a ded- cated on-board RC oscilatoris used for a POR timer func- tion, The POR time allows Vog and the oscillator circuit to stabilize before instruction execution begins, The POR timer circuit is @ one-shot timer triggered by one of the four following conditions: mt Power-bad to power-good status mStop-Mode Recovery WOT time-out WOH time-out Ds97zex1104 Watch-Dog Timer Reset. The WDT is a retriggerable ‘one-shot timer that resets the Z8 if it reaches its terminal count. The WOT is intially enabled by executing the WOT struction and is retriggered on subsequent execution of the WOT instruction. The timer circuit is driven by an on- board RC oscillator. PRELIMINARY 23 ZB6E04/E08. CMOS 28 OTP Microcontrollers OOO FUNCTIONAL DESCRIPTION (Continued) Table 3. Control Registers Zilog Reset Condition Addr. Reg. D7 DS SSDS D2_—iD_—~O_ Comments FF SPL csr OLeLree O te O HEE OEC OEEECE OEELO! 3} RP 0 0 OEE EO: OTE Osi OO) zi Fo FlAGS” —SUC‘(UCtCtt CT FB IMR [CSREERS SEEEEEE PETERS DESSEN EERE" EEE EEE) FA IRQ UU 0 «CO SC~ 00 IRBs used for positive edge detection Fe TPR a Fe" POIM. U U Uo uu 0 1 a Fr _PoM Uaseees Use U eee Ui eee Ue ORANG Fe _P2M T1471 11 ___1_Inpute after reset F5 PREO Uses Usatenet Uzteese Uae U ered Ure) Fa TO U U UT uu FB PRE! UU F2 Tt UeesaeH Urea eer ase Osea Uae Fi TMA oO 0 Olt O too. OREO: 2 Note: “Registers are not reset after a STOP-Mode Recovery using P27 pin, A subsequent reset will cause these control registers to be recontigured as shown in Table 4 and the user must avoid bus contention on the port pins or it may affect device reliabilty. 24 PRELIMINARY (0S97Z8x1104 Zilog Program Memory. The Z86E04/E08 addresses up to 1K/2KB of Internal Program Memory (Figure 11). The first 12 bytes of program memory are reserved for the interrupt vectors. These locations contain six 16-bit vectors that cor- respond to the six available interrupts. Bytes 0-1024/2048, are on-chip one-time programmable ROM. ne contre SFFHITFFH Lecaton of On-chip Fest Bjeo! ROM! trsion Broad anerFESEY 2 a " 1805 ot 0 RO on ° Ros oo 8 R08 ost @ trromet 7 noe i Nectar 6 E ost (Lower Bie) 08 s PX trae ost a ont Intrapt =I od Necir Tar H upper sy) © Ra Ee 2 ior oo Figure 11. Program Memory Map 288E04/E08 CMOS ZB OTP Microcontrollers Register File, The Register File consists of three /O port registers, 124 general-purpose registers, and 14 control and status registers RO-R3, R4-F127 and R241~R255, respectively (Figure 12). General-purpose registers occu- by the O4H to 7FH address space. /O ports are mapped as per the existing CMOS Z8. Location 255 (FFH)| ‘Stack Pointer (Bis 7-0) 284 (FE) General-Purpose Register 258 (FD) Register Pointor 252 (FO) Program Contr! Flags 251 (FB) Interupt Mask Rogister 250 (FA) Intorupt Request Register 249 (F8) Interrupt Priority Registor 248 (F6) Ports 0-1 Mode 247 (F7) Port 3 Mode 246 (F0) Port 2 Mode 285 (F5) To Prescaler 284 (F4) TimerfCountar 0 248 (F3) 1 Prescaler 282 (F2) ‘Timer/Counter 1 2a (Fi) Timor Nod [Not implemented 128 127 7H) General-Purpose Registers 4 3 Port3 2 Port2 1 Reserved (00H) Port Ds97zex1104 PRELIMINARY Figure 12, Register File enters SPL. cer RP Fuscs NB Ro eR Pom Pom Pam PRED 10 Pret n wR Pt 25 Z86E04/E08 CMOS ZB OTP Microcontrollers Zilog FUNCTIONAL DESCRIPTION (Continued) ‘The Z8 Instructions can access registers directly of indi- really through an 6-bit address field. This allows short 4-bit register addressing using the Register Pointer. Inthe 4-bit mode, the register file is divided into eight work ing register groups, each occupying 16 continuous loca- tions. The Register Pointer (Figure 13) addresses the starting location of the active working-register group. 766M ‘The pow rine fe ghar fe ukoss proided by tropa ssotos Reactive wotingrogee gum. b= ae Bane oso (ogae Poitey 3 ne i ee 3 2 t z Ars too as ristone® atone ron nae ‘yrange os oc on hapa EN, Gon G awnonnea toe Figure 13. Register Pointer ‘Stack Pointer. The Z8 has an 8-bit Stack Pointer (R255) sed for the internal stack that resides within the 124 gen- eral-purpose registers. General-Purpose Registers (GPR). These registers are Undefined after the device is powered up. The registers keep their last value after any reset, as long as the reset ‘occurs in the Voc voltage-specified operating range. Note: Register R254 has been designated as a general-purpose register and is set to 00 Hex after any reset or Stop-Mode Recovery. Counter/Timer. There_are two B-bit programmable

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