RTL8763B Realtek

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t i z e
RTL8763B Series
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RTL8763BM, RTL8763BF, RTL8763BFR, RTL8763BS, RTL8763BA
f i t h
n
BLUETOOTH 5 DUAL MODE SOC
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e e M E : 2
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PRELIMINARY
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DATASHEET
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(CONFIDENTIAL: Development Partners Only)
R e d o 6
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h e 1 Rev. 0.92
T - 1 rd
13 , November 2017
Track ID: JATR-8275-15
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2 0
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
RTL8763B Series
Datasheet Preliminary
COPYRIGHT
©2017 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
s
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
e
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
i l
Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements
f o
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
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TRADEMARKS
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are trademarks/registered trademarks of their respective owners.
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Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
LICENSE
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This product is covered by one or more of the following patents: US5,307,459, US5,434,872,
i h
US5,732,094, US6,570,884, US6,115,776, and US6,327,625.
USING THIS DOCUMENT
n f ut
o a
This document is intended for the software engineer’s reference and provides detailed programming
information.
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Though every effort has been made to ensure that this document is current and accurate, more information
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may have become available subsequent to the production of this guide.
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ELECTROSTATIC DISCHARGE (ESD) WARNING
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Damage due to inappropriate handling is not covered by warranty.
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This product can be damaged by Electrostatic Discharge (ESD). When handling, care must be taken.
l
a c
Do not open the protective conductive packaging until you have read the following, and are at an
e o
approved anti-static workstation.
R
•
d
Use an approved anti-static mat to cover your work surface.
1 6
•
e
Use a conductive wrist strap attached to a good earth ground
1 -
•
T h
Always discharge yourself by touching a grounded bare metal surface or approved anti-static mat
before picking up an ESD-sensitive electronic component
1
•
•
7 -
If working on a prototyping board, use a soldering iron or station that is marked as ESD-safe
Always disconnect the microcontroller from the prototyping board when it is being worked on
REVISION HISTORY
0 1
Revision
0.92
Release Date
2017/11/14
Summary
2
Preliminary Release.
Bluetooth 5 Dual Mode SOC ii Track ID: JATR-8275-15 Rev. 0.9

RTL8763B Series
Table of Contents
1. GENERAL DESCRIPTION .............................................................................................................................................. 1
2.
3.
e s
FEATURES ......................................................................................................................................................................... 2
SYSTEM APPLICATIONS ............................................................................................................................................... 4
4.
5.
i l
BLOCK DIAGRAM ........................................................................................................................................................... 5
POWER TREE ................................................................................................................................................................... 6
5.1.
5.2. f o
POWER ON SEQUENCE-BATTERY MODE ...................................................................................................................... 7
t
POWER ON SEQUENCE-ADAPTER MODE ...................................................................................................................... 8
6.
6.1.
a l
CLOCK TREE .................................................................................................................................................................... 8
d
OVERVIEW ................................................................................................................................................................... 8
7.
6.2.
t i z e
RESET .......................................................................................................................................................................... 9
PIN ASSIGNMENTS ....................................................................................................................................................... 11
7.1.
7.2.
e n r i
PACKAGE IDENTIFICATION ......................................................................................................................................... 11
PIN OUT (TOP VIEW) RTL8763BM QFN40............................................................................................................ 12
d o
7.3. PIN OUT (TOP VIEW) RTL8763BF/BFR QFN40 .................................................................................................... 13
7.4. PIN OUT (TOP VIEW) RTL8763BS QFN48 ............................................................................................................. 14
8.
7.5.
f i t h
PIN OUT (TOP VIEW) RTL8763BA QFN68 ............................................................................................................ 15
PIN DESCRIPTIONS ...................................................................................................................................................... 16
8.1.
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RF INTERFACE ........................................................................................................................................................... 16
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2
8.2. CRYSTAL OSCILLATOR .............................................................................................................................................. 16
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8.3. GENERAL PURPOSE I/OS ............................................................................................................................................ 16
8.4.
8.5.
t C
POWER MANAGEMENT............................................................................................................................................... 19
1 :
AUDIO CODEC ............................................................................................................................................................ 18
8.6.
8.7.
e k e n
SPI FLASH MEMORY INTERFACE ............................................................................................................................. 20
E 2
SYSTEM...................................................................................................................................................................... 20
9.
t m M :
RF RADIO......................................................................................................................................................................... 21
T 3
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9.1.
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RF RADIO .................................................................................................................................................................. 21
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9.1.1. Transceiver ........................................................................................................................................................... 21
9.1.2. Transmitter ........................................................................................................................................................... 21
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9.1.3. Receiver ................................................................................................................................................................ 21
d
9.1.4. RF IQM and TPM................................................................................................................................................. 22
9.2.
9.3.
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CRYSTAL OSCILLATOR .............................................................................................................................................. 23
CRYSTAL OSCILLATOR 32.768KHZ ............................................................................................................................ 24
9.4.
9.5.
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DSP ........................................................................................................................................................................... 25
1
AUDIO CODEC: DAC ............................................................................................................................................... 26
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9.5.1. Single-Ended Output ............................................................................................................................................ 26
T
9.5.2. Cap-Less Output ................................................................................................................................................... 28
9.5.3. Differential Output ............................................................................................................................................... 29
9.6.
9.7.
1 7
AUDIO CODEC: ADC ............................................................................................................................................... 30
AUDIO DIGITAL MICROPHONE ................................................................................................................................... 31
0
9.8. PCM I2S .................................................................................................................................................................... 33
9.9. UART INTERFACE ..................................................................................................................................................... 34
9.10.
9.11.
9.12.
9.13.
2
I2C INTERFACE .......................................................................................................................................................... 36
SPI INTERFACE .......................................................................................................................................................... 37
NFC ........................................................................................................................................................................... 37
USB INTERFACE ........................................................................................................................................................ 38
Bluetooth 5 Dual Mode SOC iii Track ID: JATR-8275-15 Rev. 0.9
RTL8763B Series
9.14. S/PDIF INTERFACE .................................................................................................................................................... 38
9.15. AUXILIARY ADC INTERFACE ..................................................................................................................................... 39
9.16. BT WI-FI CO-EXISTENCE (PTA)................................................................................................................................ 40
9.17. PWM INTERFACE....................................................................................................................................................... 41
s
9.18. MEMORY MANAGEMENT ........................................................................................................................................... 43
9.19. SERIAL FLASH MEMORY INTERFACE ....................................................................................................................... 44
9.20.
9.21.
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POWER MANAGEMENT UNIT - SWITCH MODE REGULATOR ....................................................................................... 45
BATTERY CHARGER ................................................................................................................................................... 47
i
9.21.1. PMU Protection Scheme.................................................................................................................................. 50
9.22. REFERENCE CIRCUITS ................................................................................................................................................ 54
9.22.1.
9.22.2.
9.22.3. f t o
RTL8763BM Reference Circuits ...................................................................................................................... 54
RTL8763BF/BFR Reference Circuits .............................................................................................................. 55
RTL8763BS Reference Circuits ....................................................................................................................... 56
10.
9.22.4.
a l
RTL8763BA Reference Circuits ....................................................................................................................... 57
d
ELECTRICAL CHARACTERISTICS...................................................................................................................... 58
10.1.
10.2.
t i z e
ABSOLUTE MAXIMUM RATINGS ................................................................................................................................ 58
RECOMMENDED OPERATING CONDITIONS ................................................................................................................. 58
n i
10.3. POWER MANAGEMENT UNIT; SWITCH MODE REGULATOR FOR AUDIO CORE AND AUDIO DRIVE STAGE .................. 59
e r
10.4. POWER MANAGEMENT UNIT; SWITCH MODE REGULATOR FOR DIGITAL CORE, RF, AND SYNTHESIZER ................... 59
10.5. POWER MANAGEMENT UNIT; LOW DROP LINEAR REGULATOR ................................................................................. 59
10.6.
10.7.
10.8. d h o
POWER MANAGEMENT UNIT; BATTERY CHARGER .................................................................................................... 60
i
AUDIO CODEC DAC (IF NOT SPECIALLY MARKED, THE TEST IS WITH AVCC = 2.8V) ................................................. 61
AUDIO CODEC ADC (IF NOT SPECIALLY MARKED, THE TEST IS WITH AVCC= 2.8V).................................................. 62
11.
n f u t
RF CHARACTERISTICS .......................................................................................................................................... 64
11.1.
11.2.
o a
TRANSMITTER BT CLASSIC BASIC DATA RATE (BDR).............................................................................................. 64
TRANSMITTER BT CLASSIC ENHANCED DATA RATE (EDR) ...................................................................................... 64
2 1
11.3.
11.4.
c
TRANSMITTER BT CLASSIC BLUETOOTH LOW ENERGY (BLE IQM) ......................................................................... 65
t
RECEIVER BT CLASSIC BASIC DATA RATE (BDR) .................................................................................................... 66
:
11.5.
11.6.
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RECEIVER BT CLASSIC ENHANCED DATA RATE (EDR) ............................................................................................ 67
E
RECEIVER BT CLASSIC BLUETOOTH LOW ENERGY (BLE) IQM ................................................................................ 68
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11.7.
11.8.
t e e M
RECEIVER BT CLASSIC BLUETOOTH LOW ENERGY (BLE) 2M IQM ......................................................................... 69
m
RECEIVER BT CLASSIC BLUETOOTH LOW ENERGY (BLE) LONG RANGE 500K IQM ................................................ 69
:
11.9.
11.10.
l u W T
RECEIVER BT CLASSIC BLUETOOTH LOW ENERGY (BLE) LONG RANGE 125K IQM ................................................ 69
1 3
ANALOG ADC INPUT ............................................................................................................................................ 70
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11.11. ESD PROTECTION ................................................................................................................................................. 70
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11.12. POWER CONSUMPTION .......................................................................................................................................... 71
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12.
12.1.
d 6
MECHANICAL DIMENSIONS ................................................................................................................................. 73
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PACKAGE DIMENSIONS QFN40 ................................................................................................................................. 73
12.2.
12.3.
e -
QFN40 LAYOUT LAND PATTERN STENCIL OPEN ....................................................................................................... 74
1
SUGGESTED STENCIL OPEN FOR SMT SOLDERING ON EP PAD (EXPOSED PAD UNDER THE CHIP)............................. 74
12.4.
12.5.
T h
PACKAGE DIMENSION QFN48 6X6MM2..................................................................................................................... 75
1
12.6.
12.7.
12.8. -
7
PACKAGE DIMENSION QFN68 8X8MM2..................................................................................................................... 77
12.9.
12.10.
0 1
PCB DESIGN LAYOUT TRACE ROUTING FOR 2-LAYER PCB ................................................................................. 79
2
12.11. REFLOW PROFILE .................................................................................................................................................. 79
12.12. TAPE AND REEL INFORMATION ............................................................................................................................. 80
12.12.1. Tape Information ............................................................................................................................................. 80
12.12.2. Reel Information .............................................................................................................................................. 80
12.12.3. IC Tray Information (QFN40) ......................................................................................................................... 81
Bluetooth 5 Dual Mode SOC iv Track ID: JATR-8275-15 Rev. 0.9

RTL8763B Series
12.12.6. Storage Conditions .......................................................................................................................................... 82
13. ORDERING INFORMATION ................................................................................................................................... 83
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Bluetooth 5 Dual Mode SOC v Track ID: JATR-8275-15 Rev. 0.9
RTL8763B Series
List of Tables
TABLE 1. POWER-ON SEQUENCE-BATTERY MODE ...................................................................................................................... 8
e s
TABLE 2. POWER-ON SEQUENCE-BATTERY MODE ...................................................................................................................... 8
TABLE 3. RF INTERFACE ............................................................................................................................................................ 16
TABLE 4. CRYSTAL OSCILLATOR ............................................................................................................................................... 16
i l
TABLE 5. GENERAL PURPOSE I/OS ............................................................................................................................................. 16
TABLE 6. AUDIO CODEC ............................................................................................................................................................ 18
f o
TABLE 7. POWER MANAGEMENT ............................................................................................................................................... 19
TABLE 8. SPI FLASH MEMORY INTERFACE .............................................................................................................................. 20
l t
TABLE 9. SYSTEM ...................................................................................................................................................................... 20
TABLE 10. CRYSTAL OSCILLATOR............................................................................................................................................... 23
TABLE 11. CRYSTAL OSCILLATOR............................................................................................................................................... 24
i a e d
TABLE 12. AUDIO DIGITAL MICROPHONE TIMING ...................................................................................................................... 32
TABLE 13. UART TIMING CHARACTERISTICS ............................................................................................................................. 35
t z
TABLE 14. UART DATA ERROR RATE ESTIMATION BASED ON VARIOUS BAUD RATES............................................................. 36
TABLE 15. I2C TIMING CHARACTERISTICS .................................................................................................................................. 37
e n r i
TABLE 16. INDUCTOR SELECTION ............................................................................................................................................... 46
TABLE 17. CHARGER MODE DEFINITION ..................................................................................................................................... 47
d o
TABLE 18. LED ........................................................................................................................................................................... 51
TABLE 19. PIN MUX AVAILABLE LIST....................................................................................................................................... 52
f i t h
TABLE 20. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................ 58
TABLE 21. RECOMMENDED OPERATING CONDITIONS ................................................................................................................. 58
TABLE 22. POWER MANAGEMENT UNIT; SWITCH MODE REGULATOR FOR AUDIO CORE AND AUDIO DRIVE STAGE .................. 59
n u
TABLE 23. POWER MANAGEMENT UNIT; SWITCH MODE REGULATOR FOR DIGITAL CORE, RF, AND SYNTHESIZER ................... 59
o a
TABLE 24. POWER MANAGEMENT UNIT; LOW DROP LINEAR REGULATOR ................................................................................. 59
1
c
TABLE 25. POWER MANAGEMENT UNIT; BATTERY CHARGER .................................................................................................... 60
TABLE 26. AUDIO CODEC DAC (IF NOT SPECIALLY MARKED, THE TEST IS WITH AVDD= 2.8V) ................................................ 61
: 2
t C
TABLE 27. AUDIO CODEC ADC (IF NOT SPECIALLY MARKED, THE TEST IS WITH VCC= 2.8V) .................................................... 62
k n
TABLE 28. TRANSMITTER BT CLASSIC BASIC DATA RATE (BDR).............................................................................................. 64
1
e M E
TABLE 30. TRANSMITTER BT CLASSIC ENHANCED DATA RATE (EDR) ...................................................................................... 64
: 2
TABLE 29. HARMONIC ................................................................................................................................................................. 64
e
l t u m
TABLE 31. TRANSMITTER BT CLASSIC BLUETOOTH LOW ENERGY (BLE IQM) ......................................................................... 65
T 3
TABLE 32. RECEIVER BT CLASSIC BASIC DATA RATE (BDR) .................................................................................................... 66
W 1
TABLE 33. RECEIVER BT CLASSIC ENHANCED DATA RATE (EDR) ............................................................................................ 67
e a o c
TABLE 34. RECEIVER BT CLASSIC BLUETOOTH LOW ENERGY (BLE) IQM ................................................................................ 68
TABLE 35. RECEIVER BT CLASSIC BLUETOOTH LOW ENERGY (BLE) 2M IQM.......................................................................... 69
R d
TABLE 36. RECEIVER BT CLASSIC BLUETOOTH LOW ENERGY (BLE) LONG RANGE 500K IQM ................................................ 69
TABLE 37. RECEIVER BT CLASSIC BLUETOOTH LOW ENERGY (BLE) LONG RANGE 125K IQM ................................................ 69
1 6
-
TABLE 38. ANALOG ADC INPUT ................................................................................................................................................. 70
e
TABLE 39. ESD PROTECTION ...................................................................................................................................................... 70
TABLE 40. VBAT=3.7V, RTL8763BFR ONE HEADSET TEST WITHOUT SPEAKER LOADING; RF TX= +2DBM ......................... 71
h
TABLE 41. VBAT=3.7V, RWS HEADSET TEST WITHOUT SPEAKER LOADING; RF TX= +6DBM, TEST WITH HANDSET APPLE
1 1
T
I-PHONE7 PLAYING THE MASTER ROLE, MASTER SIDE ....................................................................................................... 71
TABLE 42. VBAT=3.7V, RWS HEADSET TEST WITHOUT SPEAKER LOADING; RF TX= +6DBM, TEST WITH HANDSET ANDROID
7 -
PHONE/ANDROID7.0 PLAYING THE MASTER ROLE, SLAVE SIDE ......................................................................................... 71
1
TABLE 43. ORDERING INFORMATION .......................................................................................................................................... 83
2 0
List of Figures
Bluetooth 5 Dual Mode SOC vi Track ID: JATR-8275-15 Rev. 0.9
RTL8763B Series
FIGURE 1. BLOCK DIAGRAM ........................................................................................................................................................ 5
FIGURE 2. POWER TREE-1 ............................................................................................................................................................ 6
FIGURE 3. POWER TREE-2 ............................................................................................................................................................ 7
FIGURE 4. POWER-ON SEQUENCE-BATTERY MODE ..................................................................................................................... 7
s
FIGURE 5. POWER-ON SEQUENCE-ADAPTER MODE ..................................................................................................................... 8
FIGURE 6. CLOCK TREE................................................................................................................................................................ 9
FIGURE 7.
FIGURE 8.
l e
RESET ........................................................................................................................................................................ 10
PACKAGE IDENTIFICATION ........................................................................................................................................ 11
i
FIGURE 9. PIN OUT (TOP VIEW) RTL8763BM QFN40 ........................................................................................................... 12
FIGURE 10. PIN OUT (TOP VIEW) RTL8763BF/BFR QFN40 ................................................................................................... 13
FIGURE 11.
FIGURE 12.
FIGURE 13. f
PIN OUT (TOP VIEW) RTL8763BS QFN48 ............................................................................................................ 14
PIN OUT (TOP VIEW) RTL8763BA QFN68 ........................................................................................................... 15
t o
RF RADIO ................................................................................................................................................................. 21
FIGURE 14.
FIGURE 15.
a l
REFERENCE CIRCUIT ................................................................................................................................................. 22
d
40MHZ CRYSTAL SPECIFICATION SUGGESTION ....................................................................................................... 23
i e
FIGURE 16. 32MHZ CRYSTAL SPECIFICATION SUGGESTION ....................................................................................................... 24
FIGURE 17. DSP INTERFACES IN RTL86XX IC PLATFORM .......................................................................................................... 25
FIGURE 18.
FIGURE 19.
n t i z
CODEC AND DAC BLOCK DIAGRAM ......................................................................................................................... 26
RTL8763B MONO .................................................................................................................................................. 27
e r
FIGURE 20. RTL8763B STEREO................................................................................................................................................ 27
FIGURE 21. RTL8763B MONO .................................................................................................................................................. 28
FIGURE 22.
FIGURE 23.
FIGURE 24. d h o
RTL8763B STEREO................................................................................................................................................ 28
i
RTL8763B MONO .................................................................................................................................................. 29
RTL8763B STEREO................................................................................................................................................ 29
FIGURE 25.
FIGURE 26.
n f u t
CODEC AND ADC BLOCK DIAGRAM ......................................................................................................................... 30
RTL8763B DUAL MICROPHONE REFERENCE ........................................................................................................... 30
FIGURE 27.
FIGURE 28.
o a
RTL8763B ONE MICROPHONE AND ONE AUX-IN REFERENCE ............................................................................... 31
AUDIO DIGITAL MICROPHONE .................................................................................................................................. 31
2 1
FIGURE 29.
FIGURE 30.
c
AUDIO DIGITAL MICROPHONE TIMING DIAGRAM..................................................................................................... 32
t
I2S CONNECTION; RTL8763B IN MASTER MODE..................................................................................................... 33
:
FIGURE 31.
FIGURE 32.
k n C
I2S CONNECTION; RTL8763B IN SLAVE MODE........................................................................................................ 33
E 2 1
TIMING DIAGRAM-3 .................................................................................................................................................. 34
FIGURE 33.
t
FIGURE 34.
e m e
UART INTERFACE .................................................................................................................................................... 35
M :
UART INTERFACE TIMING DIAGRAM ....................................................................................................................... 35
T 3
FIGURE 35. I2C INTERFACE TIMING DIAGRAM ............................................................................................................................ 37
a l
FIGURE 36.
FIGURE 37.
u W 1
NEAR FIELD COMMUNICATION ................................................................................................................................. 38
c
USB INTERFACE ....................................................................................................................................................... 38
e o
FIGURE 38. BLUETOOTH SPEAKER APPLICATION ........................................................................................................................ 39
6
FIGURE 39. BLUETOOTH AUDIO RECEIVER APPLICATION ........................................................................................................... 39
R
FIGURE 40.
FIGURE 41.
d 1
AUXILIARY ADC INTERFACE APPLICATION ............................................................................................................. 40
BT WI-FI CO-EXISTENCE (PTA) .............................................................................................................................. 40
FIGURE 42.
FIGURE 43.
e 1 -
PWM INTERFACE ..................................................................................................................................................... 41
COMPLEMENTARY OUTPUT MODE ENABLED BUT NOT SET IN THE DEAD ZONE ...................................................... 42
h
FIGURE 44. MAXIMUM SETTING OF DEAD ZONE ......................................................................................................................... 43
FIGURE 45.
FIGURE 46.
T 1
DEAD ZONE IS LONGER THAN PWM HIGH LEVEL TIMER ........................................................................................ 43
-
DEAD ZONE IS LONGER THAN PWM LOW LEVEL TIMER ......................................................................................... 43
7
FIGURE 47. MEMORY MANAGEMENT .......................................................................................................................................... 44
FIGURE 48. SERIAL FLASH MEMORY; 1 AND 2-BIT MODE ......................................................................................................... 44
FIGURE 49.
FIGURE 50.
FIGURE 51. 1
SERIAL FLASH MEMORY; 4-BIT MODE.................................................................................................................... 45
0
POWER MANAGEMENT UNIT - SWITCH MODE REGULATOR...................................................................................... 45
INDUCTOR SELECTION .............................................................................................................................................. 46
FIGURE 52.
FIGURE 53.
FIGURE 54.
FIGURE 55.
2
BATTERY VOLTAGE VS. CHARGER CURRENT CURVE ............................................................................................... 48
AMBIENT DETECTION FOR BATTERY CHARGE PROTECTION ..................................................................................... 49
PMU PROTECTION SCHEME...................................................................................................................................... 50
LED .......................................................................................................................................................................... 51
Bluetooth 5 Dual Mode SOC vii Track ID: JATR-8275-15 Rev. 0.9
RTL8763B Series
FIGURE 56. I/O MUX ................................................................................................................................................................... 52
FIGURE 57. RTL8763BM REFERENCE CIRCUITS......................................................................................................................... 54
FIGURE 58. RTL8763BF/BFR REFERENCE CIRCUITS ................................................................................................................. 55
FIGURE 59. RTL8763BS REFERENCE CIRCUITS .......................................................................................................................... 56
s
FIGURE 60. RTL8763BS REFERENCE CIRCUITS .......................................................................................................................... 57
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Bluetooth 5 Dual Mode SOC viii Track ID: JATR-8275-15 Rev. 0.9
RTL8763B Series
1. General Description
The RT8763B series are single-chip Bluetooth ROM audio solutions for mono (RTL8763BM) and stereo
s
(RTL8763BF/BFR, RTL8763BS, RTL8763BA) applications. The RT8763B is composed of an ARM
core and an ultra-low power DSP core with high efficiency computing power, high performance audio
controller.
l e
codec, power management unit, ADC, ultra-low current RF transceiver, and smart I/O distribution
f i
The parameter configuration tools, the EVB kits, and the MP kits, including controller hardware and
o
software, provide a simple and flexible procedure for customers to quickly design and proceed to mass
l
fast and highly reliable development path with a very competitive R-BOM. t
production with Realtek’s new generation of audio solutions. These complete total solutions provide a
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d e o r
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Bluetooth 5 Dual Mode SOC 1 Track ID: JATR-8275-15 Rev. 0.9
RTL8763B Series
2. Features
General Features Integrated dual switch mode power regulator,
s
linear regulators, and battery charger;
Bluetooth 5 specification compliant charging current up to 400mA
Supports HFP 1.7, HSP 1.2, A2DP 1.3,
AVRCP 1.6, SPP 1.2 and PBAP 1.0
l e
Built-in battery voltage monitoring and
i
thermal protection scheme with external
Single-end RF radio output with high thermal resistor
performance 10dBm of transmitter power and
-94dBm 2M EDR receiver sensitivity f
SBC, AAC decoder support
t o
Supports Bluetooth classic (BDR/EDR)
a lPackage: 5x5mm2 QFN40 (RTL8763BM,
d
RTL8763BF, RTL8763BFR), 6x6mm2
QFN48 (RTL8763BS) and 8x8mm2 QFN68
i e
Supports Bluetooth Low Energy (BLE)
(RTL8763BA) with 0.4mm pitch
Generic access service
Device information service
n t i z
Supports OTA and USB firmware upgrade
Proprietary services for data

communication
d e o r
GSM 217Hz interference block out design
Low BOM cost
(ANCS)
f i
Apple Notification Center Service
t h
Green (RoHS compliant and no antimony or
halogenated flame retardants)
o n
Real Wireless Stereo (RWS)
a u Supports PTA (Packet Traffic Arbiter) when

1
c
Supports USB type-C audio
co-existing with Wi-Fi
: 2
t
Baseband Features
C 1
Supports iAP2
k
Realtek’s latest RCV (Real Clear Voice)
e e n E
40MHz main clock
2
M :
technology for narrowband and wideband Supports serial flash for FW storage and
t m
voice connection, including wind noise
l
reduction
u T
parameter upgrade
3
a c
Supports high resolution audio codec up to
W 1
Adaptive Frequency Hopping (AFH)
e o
Multi-link support
6
24bits, 192kHz audio data format
R d
Supports dual analog and digital MIC,
Supports Serial Copy Management System
1
(SCMS-T) content protection
-
AUX-IN, I2S digital audio, analog output
e
Supports high speed UART, I2C, SPI and
h 1
RAM and ROM Size
1
USB2.0 compatible interface ROM size 768KB
T
Supports high resolution 12-bits
-
MCU RAM size 16KB x 8 Data RAM + 8KB
multi-channel ADC
Supports PWM I/O and smart LED controller
1 7X 2 cache RAM
DSP RAM 8KB x 22
Supports USB BC1.2 battery charging
Smart I/O distribution scheme with MUX
2 0
Built-in 8Mbits FLASH memory
(RTL8763BF/RTL8763BFR)
RTL8763B Series
RF Supports 8/16 kHz 1/2-mic noise suppression
and echo cancellation
Supports TX +10dBm (typ.) maximum output
power for Bluetooth classic Packet Loss Concealment (PLC) for voice
power for Bluetooth BLE
processing
e s
SBC, and AAC-LC audio codecs supported
power for Bluetooth BLE low power TPM Audio Codec
i l
for BT audio streaming
mode
Receive sensitivity: -94dBm (2Mbps EDR) f t o
Dual operation voltage range 2.8V and 1.8V
l
Supports cap-less, single-ended, and
a d
Receive sensitivity: -97dBm (BLE) differential mode at the DAC path
i e
Receiver sensitivity: -106.5dBm (125K BLE Supports 16ohm and 32ohm speaker loading
t z
long range)
Stereo 24-bit digital-to-analog (DAC) with
component required (when TX power is

e n
Single-end TX/RX RF port without matching 102dBA SNR
r i
Stereo 24-bit analog-to-digital (ADC) with
d o
below +4dBm and using PIFA type PCB
antenna) 97dBA SNR
f i
Crystal oscillator with built-in integrated
t h
5-band configurable EQ at both DAC/ADC
paths
n u
capacitor for clock offset digital tuning
(0~20pF), could save 2-compensation CL cap
o
following Realtek design guidelines
a
Sampling rates of 8, 16, 32, 44.1, 48, 88.2,
and 96kHz are supported.
2 1
MCU
c t
Built-in MIC bias generator
:
k
32-bit ARM Cortex-M4F Processor
n E C
Digital Audio Interface
2 1
e e
1.23 DMIPS/MHz performance (Dhrystone)
t m M :
Supports two PDM digital MIC inputs
Supports hardware Floating Point Unit (FPU)
l u W T 1 3
Supports 24-bit, 192kHz on I2S digital audio
a c
Supports Memory Protect Unit (MPU) Sampling frequency
e o
Supports SWD debug interface 8/16/32/44.1/48/88.2/96/176.4/192kHz
R d
Executed external SPI flash Radio
1 6
-
4-way association cache controller Compliant with Bluetooth Core Specification
h e
DSP Audio Processing
1
including BR/EDR/LE-1M/LE-2M/LE-Coded
(LongRange)
T
Enhanced Tensilica Hi-Fi-mini compatible
24-bit DSP core providing maxima 160-MIPS
- 1
Fully integrated balun and synthesizer
7
minimizes external components.
computation power
1
RF circuit design minimizes
0
2 single-cycle MACs: 24 x 24-bit multiplier power-consumption while keeping excellent
and 56-bit accumulator
2
performance
Supports G.711 A-Law, µ-Law,
continuous-variable-slope-delta (CVSD) and
mSBC voice codecs

RTL8763B Series
PMU Operating Condition
Highly integrated PMU design for the system Operating voltage: 2.8V to 4.35V (VBAT)
application
Temperature range: -40°C to +85°C
Dual switching mode regulator for digital core,
radio and audio codec respectively Package
e s
Built-in LDO for the I/O and FLASH memory
i l
5mmx5mm, QFN40 package (RTL8763BM)
5mmx5mm, QFN40 package
f o
Built-in Li-Ion battery charger with up to
400mA charger current capability (RTL8763BF/BFR)
Supports ambient thermal detection to detect
l t
6mmx6mm, QFN48 package (RTL8763BS)
a d
the battery temperature 8mmx8mm, QFN68 package (RTL8763BA)
i e
Built-in OVP, OCP, UVP protection to
t z
protect the system.
e n r i
3. System Applications
i d h o
Mono headset
n f u t
Stereo headset
o a 2 1
c
Real Wireless Stereo (RWS) headset
Mono speaker
t C 1 :
k
Stereo speaker
e e n E 2
t m T M 3 :
a l c u W 1
Re d o 6
- 1
h e 1
T - 1
1 7
2 0
RTL8763B Series
4. Block Diagram
e s
i l
f t o
a l d
t i z e
e n r i
i d h o
n f u t
o a 2 1
c t :
k n E C 2 1
t e m e M :
l u W T 1 3
e a o c Figure 1. Block Diagram
R d 1 6
e 1 -
T h 1
7-
0 1
2
RTL8763B Series
5. Power Tree
e s
i l
f t o
a l d
t i z e
e n r i
i d h o
n f Figure 2.
t
Power Tree-1
u
o a 2 1
c t :
k n E C 2 1
t e m e M :
l u W T 1 3
e a o c
R d 1 6
e 1 -
T h 1
7 -
0 1
2
RTL8763B Series
AVCC_ MICBIAS
HV_AUDIO LX_AUDIO DRV
AVCC MICBIAS
LDO
BK AUDIO
s
VDD
CORE
e
HV_CORE LX_CORE VD12_
BK CORE SYNC
l
VD12_
RTX
i
Battery
VBAT
pack
Charger
AUXLDO1 VDDIO1 f t o
l
Adapter ADP_IN LDO
i a ADC
e d
AUXLDO2
n t VDDIO2
i z
e r
Internal
SPI Flash
i d PALDO VPA33
h o VD33_SYN
n f u t
1
VD33_PA
c o a 2
C t 1 :
k n
Figure 3. Power Tree-2
e e M E : 2
5.1.
l tPower
u m
On Sequence-Battery Mode
T 3
a c W 1
R e d o 6
- 1
h e 1
T - 1
1 7
2 0
Figure 4. Power-On Sequence-Battery Mode

RTL8763B Series
Table 1. Power-On Sequence-Battery Mode

Parameter Min. Typ. Max. Unit
s
T0 - 58.5 - mS
e
T1 - 6.7 - mS
T2 - 10 - mS
T3 - TBD
i l
- -
5.2. Power On Sequence-Adapter Mode f t o

a l d
t i z e
e n r i
i d h o
n f
Figure 5.
t
Power-On Sequence-Adapter Mode
u
o Table 2.
a
Power-On Sequence-Battery Mode
2 1
Parameter
T0
c Min.
100
t
Typ.
-
Max.
-
Unit
mS
:
k n E C 2 1
6.
t e
Clock Tree
m e M :
6.1.
l Overview
u W T 1 3
a c
The RTL8763B is composed of two clock oscillator circuits, 40MHz and 32.768kHz.
e o 6
40MHz is for the system main clock in active mode, while 32.768kHz is for a low power clock when in
Rsleep mode.
d 1
-
A low power clock from an external 32.768kHz crystal (only RTL8763BA) and its circuitry is optional
e 1
for consideration of minimum power consumption in deep sleep mode. The low power clock could also
h 1
be derived from the internal RCOSC block for cost efficiency and PCB design area optimization.
T -
1 7
2 0
RTL8763B Series
e s
i l
f t o
a l d
t i z e
e n r i
i d h o
n f u t
o a 2 1
c t :
k n E C 2 1
t e m e Figure 6.
M
Clock Tree
:
6.2. l Reset u W T 1 3
e a o c
R d 1 6
The RTL8763B integrates multiple-reset protections to guarantee the system is working under the defined
power range, and to avoid system hang up or FLASH memory corruption issues. The external reset IC is
-
optional if the reset threshold defined by the customer is higher than 1.8V. If the customer would like to
e 1
add an external reset IC, it is required to choose an OPEN drain type as the I/O power domain is different
h
from the HV port.
T - 1
HW_RST# pin is active low to trigger reset behavior, and the drive low should be longer than 8ms (>8ms)
7
to avoid unconditional rest noise from the PCB board.
1
This high reliability design can stabilize the whole system and save the BOM of an external reset.
2 0
RTL8763B Series
e s
i l
f t o
a l d
t i z e
e n r i
i d h o
n f u t
o a 2 1
c t
Figure 7. Reset
:
k n E C 2 1
t e m e M :
l u W T 1 3
e a o c
R d 1 6
e 1 -
T h 1
7 -
0 1
2
RTL8763B Series
7. Pin Assignments
7.1. Package Identification
e s
Green package is indicated by the ‘G’ in GXXXV (Figure 9). The version is shown in the location
marked ‘V’.
i l
f t o
a l d
t i z e
e n r i
i d h o
n f u t
o a 2 1
c t :
k n
Figure 8.
E C
Package Identification
2 1
t e m e M :
l u W T 1 3
e a o c
R d 1 6
e 1 -
T h 1
7 -
0 1
2
RTL8763B Series
7.2. PIN OUT (TOP View) RTL8763BM QFN40
e s
i l
MIC1_P 1
f LDO_A
t o
l
MIC_BIAS HV_A
VREF
i a e dADPIN
t z
AVCC_DRV VBAT
n i
AOUT_RN HV_CORE
e r
AOUT_RP LX_CORE
AVCC
VD12_RTX
i d h o ADPSO
VDDCORE
VD33_PA
n f 41: EP
u t P0_7/ADC_7
RFIQ_IQM
o
10
a
P0_6/ADC_6
2 1
c t :
k n E C 2 1
t e m e M :
l u
Figure 9.
W T
PIN OUT (TOP View) RTL8763BM QFN40
1 3
e a o c
R d 1 6
e 1 -
T h 1
7-
0 1
2
RTL8763B Series
7.3. PIN OUT (TOP View) RTL8763BF/BFR QFN40
MIC2_N/AUXR
MIC2_P/AUXL
s
LDO_AUX2
MIC_BIAS
e
MIC1_N
MIC1_P
HV33
P2_2
P2_1
P2_0
i l
f o
40 31
VREF 1
l tLX_AUDIO
AVCC_DRV
i a e d HV_A
AOUT_LP
n t i z ADPIN
AOUT_LN
d e o r VBAT
i h
AOUT_RN HV_CORE
AOUT_RP
n f u t LX_CORE
AVCC
o a
ADPSO
2 1
VD12_RTX
c t
VDDCORE
:
C 1
41: EP
k n E 2
VD33_PA P0_7/ADC_7
t e
RFIQ_IQM 10
m e M :
P0_6/ADC_6
l u W T 1 3
a c
11 02
Re d o 6
1
HW_RST_N
LDO_AUX1
VD33_SYN
VD12_SYN
-
DIG_OUT
e
VPA33
P1_0
P1_1
1
XO
h
XI
T
Figure 10. PIN OUT (TOP View) RTL8763BF/BFR QFN40
- 1
1 7
2 0
RTL8763B Series
7.4. PIN OUT (TOP View) RTL8763BS QFN48
e s
i l
f t o
a l d
t i z e
e n r i
i d h o
n f u t
o a 2 1
c t :
k n E C 2 1
t e m e M :
l u W T 1 3
e a o c
R d 1 6
e 1 -
T h Figure 11.
1
PIN OUT (TOP View) RTL8763BS QFN48
7-
0 1
2
RTL8763B Series
7.5. PIN OUT (TOP View) RTL8763BA QFN68
e s
i l
f t o
a l d
t i z e
e n r i
i d h o
n f u t
o a 2 1
c t :
k n E C 2 1
t e m e M :
l u W T 1 3
e a o c
R d 1 6
e 1 -
T h Figure 12.
1
PIN OUT (TOP View) RTL8763BA QFN68
7-
0 1
2
RTL8763B Series
8. Pin Descriptions
8.1. RF Interface
RTL
Table 3. RF Interface
e s
l
Pad RTL RTL RTL
Pin Name 8763BF/ Description
Type 8763BM 8763BS 8763BA
i
BFR
f o
Bluetooth radio 50Ω transmitter output
RFIO_IQM RF 10 10 12 17
and receiver input (dual mode)
RFIO_TPM RF - - -
l
14
t
Bluetooth radio 50Ω transmitter output
and receiver input (BLE)
i a e d
8.2. Crystal Oscillator
Table 4.
nt
Crystal Oscillator
i z
Pin Name
Pad
Type
RTL
8763BM
RTL
d
8763BF/
e
RTL
8763BS
RTL
8763BA
o r Description
i h
BFR
XI A 13 13 15 20 Crystal input
XO A 14
n f 14 16 21
ut Crystal output
A: Analog
o 2 1 a
GeneralcPurpose I/Os :
8.3.
k n t C 1
e e M E
Table 5.
2
General Purpose I/Os
:
t m
RTL
T 3
Pad RTL RTL RTL
l u
W 1
BFR
e a P0_0/ADC_0
o c I/O
- - 23 34
Programmable GPIO. Can be
programmed as ADC input pin
6
I/O A
R d
Pull high/low input configurable
1
I/O
-
P0_1/ADC_1 - - 24 35 programmed as ADC input pin
e
I/O A
h I/O
1 1 Programmable GPIO. Can be
T
I/O A
-
7
I/O
1
I/O A
P0_4/ADC_4
I/O
I/O A
2 0 - - - 38

RTL8763B Series
RTL
Pad RTL RTL RTL
BFR
s
I/O I/O
P0_5/ADC_5 - - - 39 programmed as ADC input pin
A
e
l
I/O I/O
P0_6/ADC_6 21 21 27 40 programmed as ADC input pin
i
A
P0_7/ADC_7
I/O I/O
A
22 22 28 41
f t o
l
Programmable GPI and MFB for power
a d
P1_0 I/O 16 16 18 23
on
P1_1 I/O 17 17 19
t i 24
z e
Programmable GPIO
n i
Programmable GPIO
P1_2 I/O - - - 25
P1_3 I/O -
d
-
e - 26
o r Programmable GPIO
P1_4 I/O -
f i - -
t h 27
Programmable GPIO
n u
Programmable GPIO
1
P1_5 I/O - - - 28
P1_6 I/O
c o - - -
a 29
Programmable GPIO
2
:
P1_7
k
I/O - -
n t - 30
C
Programmable GPIO
1
P2_0
e I/O 33
e33 39 54
M E 2
Programmable GPIO
:
l t
P2_1 I/O -
u m 34 40
T
55
3
Programmable GPIO
W 1
e a P2_2 I/O
o c
- 35 - 56
Programmable GPIO
R P2_3 I/O
d - - - 57
1 6 Programmable GPIO
-
Programmable GPIO
e
P2_4 I/O - 41 -
1
h
I/O: Bidirectional digital pad
T 1
7 -
I/O PU: Bidirectional digital pad with pull high resistor inside when input mode
I/O PD: Bidirectional digital pad with pull low resistor inside when input mode
0
I/O A: Bidirectional digital pad and programmable ADC
1
2
RTL8763B Series
8.4. Audio Codec

Table 6. Audio Codec
RTL
s
Pad RTL RTL RTL
e
BFR
l
MIC1 input negative pad. Used as main
MIC in dual MIC application.
i
MIC1_N AH 40 38 48 3
Programmable digital I/O, refer to MUX
f o
table
t
MIC1 input positive pad. Used as main
l
MIC1_P AH 1 39 1 4
i a e d table
MIC2 input negative pad. Used as 2nd
t z
MIC2_N AH - 36(*)
e n
46(*) 1
r i table
(*) AUX input right channel pad.
d o
table
f i t h MIC2 input positive pad. Used as 2nd

n u
MIC2_P AH
o
- 37(**) 47(**)
a
2 table
(**) AUX input left channel pad.
2 1
c t
table
:
SPKR_N
k
AH 5 5
n 7 10
E C 1
Right channel speaker output negative
2
t e m e M
table
:
Right channel speaker output positive
l
SPKR_P AH 6
u
6 8
W
11
T 3
1table
e a o c Left channel speaker output negative
6
SPKL_N AH - 4 6 9 Programmable digital I/O, refer to MUX
R d
table
SPKL_P AH - 3 5 8
- 1
Left channel speaker output positive
h e 1
table
1
MICBIAS PO 2 40 2 5 Microphone bias output
VREF
T PO 3 41 3
-
6
Codec bandgap reference output, add a
1µF cap as close as possible.
AUXIN_R AH - - -
1 7
67
AUX input right channel pad.
0
table
AUX input left channel pad.
AUXIN_L AH -
AH: Analog and digital hybrid programmable

-
2 - 68 Programmable digital I/O, refer to MUX
table

RTL8763B Series
PO: Power output
8.5. Power Management

Pad RTL
Table 7.
RTL
8763BF/
Power Management
RTL RTL
e s
l
Pin Name Description
BFR
VBAT PIO 27 27 33 48
fi Battery input when battery only
o
Battery charge output when in charger
t
mode with adapter in
ADP_IN PI 28 28 34 49 Adapter input for battery charge
HV_CORE PO 26 26 32
a l 47
Switch output for switch mode regulator,
d
add a 4.7µF cap as close as possible
LX_CORE PO 25 25
t i
31 46
z e
Switch mode regulator output, connect to
a 2.2µH inductor as close as possible
n i
Switch mode regulator sense input and
VDDCORE PI 23 23 29 44
digital core power input
HV_AUDIO PO -
d
29
e 35 50
o r
Switch output for switch mode regulator,
add a 4.7µF cap as close as possible
i h
Switch mode regulator output, connect to
LX_AUDIO PO - 30 36 51
a 2.2µH inductor as close as possible
HV_A PO 29
n f - -
u t -
Switch output for LDO, add a 1µF cap as
1
close as possible
LDO_A PO
c o 30 - -
a -
LDO mode regulator output, add a 1µF as
close as possible.
2
AVCC PO 7 7
t 9 12
C 1 :
Switch mode regulator sense input and
power input for codec digital circuitry,
e k e n E
1.8V or 2.8V
2
Power input for codec drive stage, 1.8V
M :
AVCC_DRV PI 4 4 4 7
t m
or 2.8V
VD33_PA
l
VD33_SYN
PI
PI
9
11
u
13
15
11
13
W T
16
18
1 3
3.3V power input for RF PA
3.3V power input for RF synthesizer
e a VPA33 PO
o c
20 20 22 33 3.3V linear regulator output
6
VD12_SYN PI 12 12 14 19 1.2V power input for RF synthesizer
R VD12_RTX PI
d 8 8 10 15
1
1.2V power input for RF circuitry
Programmable linear regulator output for
-
LDO_AUX1 PO 19 19 21 32
e
I/O
LDO_AUX2
h
PO 31 31 37
1
52
1Programmable linear regulator output for
I/O
ADPSO
T
V33_USB PO
PO
-
24
-
24
-
30
-
64
45
Power output, add 1µF cap
DIG_OUT
HV33
PO
PO
15
32
15
32
17
38
1 7 22
53
GND_EP
PO: Power Output

PI: Power Input
GND EP EP
2 0
EP EP Exposed pad with ground connections

RTL8763B Series
PIO: Power Input and Output
8.6. SPI FLASH Memory Interface

Table 8. SPI FLASH Memory Interface
e s
Pin Name
Pad
Type
RTL
8763BM
RTL
8763BF/
BFR
RTL
8763BS
RTL
8763BA
i l Description
SPIFLASH_
SCLK
O 34 - 42 59
f o
Serial flash clock output
t
SPIFLASH_
CS#
I/O 36 - 44
a l 61
Serial flash chip select, low active
d
i e
Serial flash data output for 1-bit mode,
connect to SI pin of external FLASH
SPIFLASH_SI/
SIO0
I/O 35 -
n t
43 60
i z memory
connect to SIO0 pin of external FLASH
d e o r memory
Serial flash data input for 1-bit mode,
i h
connect to SO pin of external FLASH
f t
SPIFLASH_SO/ memory
I/O 37 - 45 62
SIO1 Serial flash data output for 4-bit mode,
o n a u connect to SIO1 pin of external FLASH

memory
1
SPIFLASH_
I/O
c - - - 63
: 2
t
WP#/SIO2
C 1
memory
SPIFLASH_
e k I/O -
e
-
n - 58
E
2
M :
HOLD#/SIO3
memory
l t
O: Digital output
u m T 3
a
I: Digital input
c W 1
Re d o 6
8.7. System
- 1
h e Table 9. System
1
1
RTL
Pad RTL RTL RTL
T
-
BFR
7
System reset input with internal pull high,
1
HW_RST# I_PU 18 18 20 31 low active with at least 5ms low to trigger
system reset
USB_DP
USB_DN
AI/O
AI/O
-
-
I_PU: Input with internal pull high inside

-
-
2 0
-
-
65
66
USB signal positive
USB signal negative

RTL8763B Series
9. RF Radio
9.1. RF Radio
e s
i l
f t o
a l d
Figure 13.
t i RF Radio
z e
9.1.1. Transceiver
e n r i
i d h o
Fully integrated radio transceiver compliant with Bluetooth SIG test specification. Designed for low
power consumption and excellent transmit and receive performance in the ISM band.
n f u t
9.1.2. Transmitter
o a 2 1
c :
The Transmit mixer translates the baseband input signal to form the RF signal. It is designed to provide
t C 1
good stability and modulation characteristics.
k n E
The power amplifier integrated in the chip can provide up to 10 dBm in the ISM band.
e e 2
t m T M 3 :
9.1.3.
a l Receiver
c u W 1
e o
This is a Low Noise Amplifier. It amplifies a low energy RF signal to the desired level without
d 1 6
significantly increasing the noise power. When input power is high, the designed limits non-linearity.
R
The Receive mixer is a device whose input is an RF signal, and the output is an IF signal. The IF signal is
e
then passed along the IF path to the demodulator.
1 -
h
The Synthesizer is a control loop to compare the crystal and VCO during their phases. If the VCO
T 1
frequency shifts, then the phase difference produces an error signal for the control loop.
-
1 7
2 0
RTL8763B Series
9.1.4. RF IQM and TPM

9.1.4.1 RF IQM
The RTL8763B supports Bluetooth classic and Bluetooth BLE for all packages (known as the RF_IQM
path). TX radiation power is up to +10 dBm.
e s
9.1.4.2 RF TPM
i l
As well as RF_IQM, the RTL8763BA supports RF_TPM, which is an extra low current consumption RF
path for Bluetooth BLE. TX radiation power is up to +4 dBm. f t o
the RTL8763B hardware instructions or the RTL8763B reference circuit.
a l
In order to combine RF_IQM and RF_TPM into one antenna port, an SPDT circuit is required; refer to
d
ANT_SW
C45
t i C46
20pF
1
z
L12
3.9nH
e2 RFIO_TPM
n i
10pF U4
6 1 C47 C48
C49 VC1 RF1 0.4pF 1.2pF
e r
20pF
R25 0 5 2
RFC GND
d o
ANT1
C50 C51
1.5pF 1.5pF ANT_SWB 4 3 C52 L13
i h
NPO NPO VC2 RF2 20pF 2.2nH
C53 1 2 RFIO_IQM
TRSW
10pF
f t
L21 C135 C56
0 0.6pF 1.2pF
n u
ACX HI1005-1C
1 2
o a 2 1
c
Figure 14. Reference Circuit
t C 1 :
e k e n E 2
t m T M 3 :
a l c u W 1
Re d o 6
- 1
h e 1
T - 1
1 7
2 0
RTL8763B Series
9.2. Crystal Oscillator

The RTL8763B series has a built-in 40MHz crystal oscillation circuit to provide a stable, controllable
system clock. With the built-in capacitor, the clock offset can be fine-tuned in the mass production
design specification and QVL.

e s
process. The maximum internal cap is 20pF typically, and we suggest following the Realtek crystal
i l
The external capacitors, C1 and C2, can be replaced by an internal cap, reducing the BOM cost,
minimizing PCB dimensions, and providing flexibility for clock fine-tuning. The clock offset calibration
f
procedure is supported with Realtek’s MP GU hardware; contact Realtek’s FAE for details.
Table 10. Crystal Oscillator
t o
Parameter
Frequency (MHz)
Min.
-
a l Typ.
40
d
Max.
-
i e
Frequency tolerance (ppm) - - ±10
t z
Frequency stability (ppm) over
- - ±10
n i
operating temperature
Load capacitance (pF) 7 9 -
Drive Level (µW)
Equivalent Series Resistance (Ohm)
d e -
-
o r-
-
300
50Ω@7pF
Insulation Resistance (MOhm)
f i 500
t h -
40Ω@9pF
-
o n a u 1
c : 2
k n t C 1
e e M E : 2
l t u m T 3
a c W 1
Re d o 6
- 1
e
Figure 15. 40MHz Crystal Specification Suggestion
Example:
h 1 1
T
For a crystal with specification CL=9pF
-
on the PCB trace and IC SMT soldering pad….etc.
1 7
CL= [ (C1 X C2) / (C1+C2) ] + ( Cint / 2 ) + Cparasitic, the parasitic capacitor Cparasitic can be observed
2 0
Rule of thumb says ‘C1 + Cint’ is typically 12~15pF, hence the external capacitor C1 and C2 can be
replaced by the internal capacitor Cint, which can be 20pF at the maximum setting to cover the needs of
external capacitors.

RTL8763B Series
9.3. Crystal Oscillator 32.768kHz

The RTL8763BA has a built-in 32768Hz crystal oscillation circuit to provide a stable, controllable low
power clock. With the internal built-in capacitor, the clock offset can be fine-tuned. The maximum
QVL.
e s
internal cap is 12.8pF typically, and we suggest following the Realtek crystal design specifications and
i l
If the CL specification of the crystal is 7pF, the external capacitor, C1 and C2, can be replaced by an
internal cap, reducing the BOM cost, minimizing PCB dimensions, and providing flexibility for clock
fine-tuning
f
Table 11. Crystal Oscillator
t o
Parameter
Frequency (kHz)
Min.
-
a l Typ.
32.768
d
Max.
-
i e
Frequency tolerance (ppm) - - ±20
t z
Load capacitance (pF) - 7 -
n i
Drive Level (µW) - - 0.5
e r
Equivalent Series Resistance (KOhm) - - 90
Insulation Resistance (MOhm) 500 - -
i d h o
n f u t
o a 2 1
c t :
k n E C 2 1
t e m e M :
l u W T 1 3
e a o c
R d 1 6
-
Figure 16. 32MHz Crystal Specification Suggestion
Example:
h e 1
T
For a crystal with specification CL=7pF
- 1
CL= [ (CA X CB) / (CA+CB) ] + Cparasitic, the parasitic capacitor Cparasitic can be observed on the PCB trace
and IC SMT soldering pad….etc.
CA = C1+Cint
1 7
CB = C2+Cint
2 0
RTL8763B Series
9.4. DSP
The RTL86xx IC platform incorporates a Tensilica Hi-Fi DSP core to enable high-performance signal
processing functions for Bluetooth audio/voice data streaming. With customized powerful instructions
functional blocks.
e s
designed in the DSP, Figure 17 illustrates the DSP architecture and interfaces with other hardware
i l
f t o
a l d
t i z e
e n r i
i d h o
n f u t
o a 2 1
c t :
k n E C 2 1
t e Figure 17.
m e M
DSP Interfaces in RTL86xx IC Platform
:
Key features of this DSP core include:
l u W T 1 3
a c
• 160 MHz clock, providing up to 160 MIPS computation power.
e o
• Dual-issue VLIW architecture
R d
• 32-bit ALU fixed-point DSP core
• Single-cycle flexible multiply-and-add (MAC) supporting capability:
1 6
e
- Dual 24x24-bit MAC units with 56-bit accumulator
1 -
h
- Single 32x16-bit MAC unit with 56-bit accumulator
T
• Variable-length (8/16/32/64-bit) data memory fetch
• Zero overhead looping
- 1
• Zero overhead circular buffering indexing
1 7
0
• Single cycle barrel shifter supporting up to 56-bit operation.
2
• Multi-cycle 32-bit divide
• Low overhead interrupt

RTL8763B Series
9.5. Audio CODEC: DAC
e s
i l
f t o
a l d
t i z e
e n r i
i d
Figure 18.
h o
Codec and DAC Block Diagram
n f u t
1
The RTL8763B supports three types of analog audio output format
• Single-ended output
c o a 2
• Cap-less output
t C 1 :
k n
• Differential output
e e M E : 2
9.5.1.
l t Single-Ended Output
u m T 3
a c W 1
In single-ended output mode, only SPK_P drives the audio signal and bias on VREF DC level. An
external 100µF capacitor is needed to do DC decoupling. The DC voltage must be eliminated as:
R
•
e d o 6
DC voltage will create a large DC current on the speaker unit, which is designed for 16 or 32ohm, and
result in power consumption issues.
- 1
e
• The large DC current will result in heat issues on the speaker unit and possible burn out.
h 1 1
The 100µF cap can be adjusted according to end product requirements.
T -
1 7
2 0
RTL8763B Series
RTL8763B MONO
e s
i l
f t o
a l d
i e
Figure 19. RTL8763B MONO
RTL8763B STEREO
n t i z
d e o r
Crosstalk isolation between Right channel and Left channel should be below -80dB
f i t h
o n a u 1
c : 2
k n t C 1
e e ME : 2
l t u m T 3
a c W 1
Re d o 6
- 1
h e 1
T Figure 20.
- 1
RTL8763B STEREO
1 7
2 0
RTL8763B Series
9.5.2. Cap-Less Output

In cap-less mode, SPK_P drives the audio signal and bias on the VREF DC level. SPK_N drives a bias
VREF DC signal. Both SPK_P and SPK_N are connected to the speaker unit ‘PLUS’ and ‘MINUS’
e s
nodes respectively. The DC signal can be cancelled without the need for a DC decoupling capacitor. The
low frequency response is not degraded because there is no decoupling DC on the PCB path; hence the
low frequency response is not changed.
i l
The advantage: save one or two big capacitors in the BOM, save PCB design area and good audio low
f o
frequency response. The main application is for audio products, mono headset, and stereo headset.
RTL8763B MONO
t
a l d
t i z e
e n r i
i d h o
n f Figure 21.
t
RTL8763B MONO
u
o a 2 1
c
RTL8763B STEREO
t
Crosstalk isolation between Right channel and Left channel is lessened; approximately -50dB ~ -60dB
C 1 :
k n
only.
e e ME : 2
l t u m T 3
a c W 1
Re d o 6
- 1
h e 1
T - 1
1 7
Figure 22.
2 0
RTL8763B STEREO

RTL8763B Series
9.5.3. Differential Output

In differential mode, both SPK_P and SPK_N drive the audio signal and bias on VREF DC level. SPK_P
and SPK_N are in one differential pair and drive a signal with 180o difference (reverse). The
e s
anti-interference performance is best when the signals are routed on the PCB. Both SPK_P and SPK_N
are connected to speaker unit ‘PLUS’ and ‘MINUS’ node respectively. The DC signal can be cancelled
unit will be doubled.
i l
without the need for a DC decoupling capacitor, and the signal swing (peak to peak Vpp) on the speaker
f o
The low frequency response is not degraded as there is no decoupling capacitor on the path, hence the low
t
frequency response is not changed. The advantage: save one or two big capacitors in the BOM, save PCB
l
design area, good audio low frequency response, good anti-interference performance, and good crosstalk
a d
isolation between Right and Left channels. The solution is especially good for headband headset, and
neckband headset.
RTL8763B MONO
t i z e
e n r i
i d h o
n f u t
o a 2 1
c Figure 23.
t
RTL8763B MONO
:
RTL8763B STEREO
k n E C 2 1
t e m e M
Crosstalk isolation between Right channel and Left channel should be below -80dB
:
l u W T 1 3
e a o c
R d 1 6
e 1 -
T h 1
7-
0 1
Figure 24.
2RTL8763B STEREO

RTL8763B Series
9.6. Audio CODEC: ADC
e s
i l
f t o
a l d
t i z e
Figure 25.
e n
Codec and ADC Block Diagram
r i
i d h o
The RTL8763B supports dual analog microphones, MIC2 and MIC1. MIC1 is treated as main
n f
it can be configured as analog line input (AUX IN).
u t
microphone always, and MIC2 as the 2nd auxiliary in dual microphone applications. If MIC2 is not used,
o a 2 1
Main MIC
c 1-MIC Application
MIC1
t
2-MIC Application
MIC1
Note
-
:
k
2nd MIC -
n
MIC2
E C -
2 1
e e
Audio line in (AUX IN) MIC2 - -
t m T M 3 :
l u
Microphone Application with Biasing
a c W 1
e o 6
MICBIAS
MICBIAS
R d
LDO
2.2KΩ
MIC1_P
1uF
-
+
1
e
AMP MIC1
-
1
MIC1_N Main Mic
2.2KΩ
h
1uF
T 1
2.2KΩ
AMP
MIC2_P
1uF
7 - +
-
MIC2
1
MIC3_N 2 nd MIC
2.2KΩ
1uF
Figure 26.
2 0
RTL8763B Dual Microphone Reference
Note: UI configuration to enable MIC1 and MIC2 function; DSP configuration to set the AMP gain.

RTL8763B Series
RTL8763B One Microphone and One AUX-IN
e s
i l
f t o
a l d
t i z e
Figure 27.
e n r
RTL8763B One Microphone and One AUX-IN Reference i
d o
Note: UI configuration to enable MIC1 and AUX_IN function; DSP configuration to set the AMP gain.
i h
9.7.
n
Audio Digital Microphonef u t
o a 2 1
c
AVCC AVCC
MIC
MIC
Select*
t
Select*
C 1 :
e k e n E 2
t
DMIC1
m
DMIC2
T M 3:
l u
(High trigger) (Low trigger)
a c W 1
Re d o 6
1
* Check digital mic specification
e
DMIC DMIC
1 -
h
DATA CLOCK
T
Figure 28.
1
Audio Digital Microphone
-
1 7
2 0
RTL8763B Series
Audio Digital Microphone Timing Diagram
e s
i l
f t o
a l d
t i z e
e n r i
i d h o
n f
Figure 29.
u t
Audio Digital Microphone Timing Diagram
o a 2 1
c Table 12. Audio Digital Microphone Timing
t :
C 1
Min. Typ. Max. Note
FCLOCK
e k 312.5kHz 2.5MHz
e n 5MHz
Supports five clock rates, 312.5K, 625K,
E 1.25M, 2.5M, 5M`

2
t
Clock Duty
Trise
40%
5
m
60%
20
T M -
3 :
a l Tfall
T1 (ns)
5
8
c u 15
20
100
W
-
-
1
Re T2 (ns)
T3 (ns)
d o 8
8
15
15
100
100
6
-
-
T4 (ns) 8 15 100
- 1 -
h e 1
T - 1
1 7
2 0
RTL8763B Series
9.8. PCM I2S

The RTL8763B supports two PCM/I2S digital audio output interfaces. The sampling rate can be from
8kHz to 192kHz to support middle quality and high quality I2S DAC. A MCLK for external DSP chip as
UI tool. The MCLK can be programmed as 128*BCLK or 256*BCLK depending on the DSP
e s
main clock is also available from the RTL8763 PLL, and can be enabled from the I/O MUX table in the
l
specification, and with the I2C controller interface it provides a complete I2S control interface.
i
f t o
a l d
t i z e
e n r i
i d h o
n f u t
o a 2 1
c Figure 30.
t
I2S Connection; RTL8763B in Master Mode
:
k n E C 2 1
t e m e M :
l u T 3
2
I C_CLK
a c
2
I C_DATA
W 1
Re d o 6
I2C LRCLK
- 1 Loud
h e RTL8763B
BLCK
DSP
1
speaker
T
(I2S Slave) ADCDAT
- 1 MIC
7
DACDAT
1
XIN XO
MCLK=
2 0
256*BLCK or 128*BLCK Save a 12.288MHz or 24.576MHz crystal!
Figure 31. I2S Connection; RTL8763B in Slave Mode

RTL8763B Series
e s
i l
f t o
a l d
t i z e
e n r i
i d h o
n f u t
o a 2 1
c t :
k n E C 2 1
t e m e M :
l u W T 1 3
e a o c
R d 1 6
e 1 -
T h 1
-
Figure 32. Timing Diagram-3
Note: ‘SCK’ may to be inverted at any time if required.
1 7
9.9. UART Interface
2 0
The RTL8763B supports a UART interface for FLASH memory parameter programming, and UART
commands for MCU application. For the UART command application, refer to the ‘Realtek UART
command set’ document.
RTL8763B Series
e s
i l
f t o
a l d
t i z e
e n
Figure 33. UART Interface
r i
i d h o
n f u t
o a 2 1
c t :
k n E C 2 1
t e m e M :
l u W T 1 3
e a o c
R d 1 6
e 1 -
T h 1
Figure 34.
-
UART Interface Timing Diagram
7
Parameter
0
Symbol 1
Table 13. UART Timing Characteristics
Min Typical Max
Timing between RX Stop bit and RTS go high
when RX FIFO is full (symbol time)
Timing between CTS go low and device send
first bit (ns)
2
td_rts
td_cts
-
-
-
-
0.5
25

RTL8763B Series
Parameter Symbol Min Typical Max
Timing between CTS go high and TX send stop
tset_cts 75 - -
bit (ns)
e s
Table 14. UART Data Error Rate Estimation Based On Various Baud Rates
UART Classification Baud rate
i
Errorl
-
-
1200
9600
f 0.08%
0.08%
t o
l
- 14400 0.08%
a d
- 19200 0.4%
i e
- 28800 0.28%
- 38400 0.15%
-
-
57600
n
76800 t 0.02%
0.01%
i z
Default Rate
-
d e
115200
128000
o r
0.08%
0
i h
- 153600 0.22%
f t
- 230400 0.08%
n u
- 460800 0.11%
-
-
o
500000
921600
a
0
0.11%
2 1
-
c 1000000
t
0
:
C 1
- 1843200 0.14%
e k -
-
e n
2000000
3000000
E
0
0.3%
2
t
Maximum Rate
m
4000000
T M 0
3 :
a
9.10. lI2C c
Interfaceu W 1
R e d o 6
1
START STOP
e 1 -
h
SDA
T tr tf
- 1
tset_DAT
1 7
SCL
th_STR tlow 2 0 th_DAT thigh tset_STOP

RTL8763B Series
Figure 35. I2C Interface Timing Diagram
Parameter
Table 15. I2C Timing Characteristics
Symbol Min
e sTypical Max
SCL clock frequency (kHz)
High period of SCL (ns)
-
thigh
-
600
i l -
-
400
-
Low period of SCL (ns)
Hold time of START (ns)
tlow
th_STR
f
1300
600
-
-
t o -
-
l
Hold time of DATA (ns) th_DAT 0 - -
a d
Setup time of STOP (ns) tset_STOP 600 - -
i e
Setup time of DATA (ns) tset_DAT 100 - -
t z
Rise time of SCL and SDA (ns)
tr See note - -
(with 4.7k ohm resistor pulled high)
Fall time of SCA and SDA (ns)
e
Note: Depends on the external bus pull up resistor.n tf See note
r i - -
i d h o
9.11. SPI Interface
n f u t
o a
The RTL8763B supports industrial SPI (Serial Peripheral Interface), in both master and slave mode.
2 1
c
The SPI function can be enabled using the I/O MUX settings in the UI tool. Refer to the MUX function
table in the I/O MUX section (page 52).
t :
k n E C 2 1
t e m e M :
9.12.
l NFC
u W T 1 3
a c
NFC (Near Field Communication) is a technology to simplify the establishment of a Bluetooth link
e o 6
between a Bluetooth host and a Bluetooth device. This is often used in smartphone applications with a
R
smartphone APP.
d 1
e
automatically by touching the two devices together.
1 -
The RTL8763B supports the NFC feature to power on the whole system and connect with smart phone
T h 1
The NFC application circuit in the RTL8763B reference circuit is very simple and cost effective with
the BD ADDR in the NFC tag with the memory in the RTL8763B.
7 -
minimum BOM required. In mass production flow, an MP tool also supports an easy way to synchronize
0 1
2
RTL8763B Series
Figure 36. Near Field Communication
9.13. USB Interface
e s
The RTL8763BA supports a USB2.0 full speed interface and the USB BC1.2 USB charger specification.
i l
The USB ports on personal computers, laptop PCs, and USB adapters are convenient for portable devices
to draw current for the audio device to charge the battery. When a device attaches to the USB ports, the
• 2.5mA average if the USB bus is suspended f

USB2.0 specification requires that after connecting a device must draw current less than:
t o
• 100mA if the bus is not suspended and not configured
a l d
i e
• 500mA if the bus is not suspended and configured for 500mA
t z
• Support USB charger with a DCP, such as wall adapter or car power adapter
e n r i
The RTL8763BA follows the USB2.0 and USB BC1.2 specification to draw the charging current from
the USB ports and adjust the current under different USB port states accordingly.
d o
The USB port also supports a FLASH memory parameter update process; refer to MP tool guidelines.
i h
n f u t
o a 2 1
c t :
k n E C 2 1
t e m e M :
l u W T 1 3
e a o c
R d 1 6
e 1 -
h
Figure 37. USB Interface
T - 1
9.14. S/PDIF Interface
1 7
2 0
The RTL8763B supports S/PDIF (SONY/PHILIPS Digital Interface) output; the purpose is to transfer
digital audio data among digital devices with minimum loss.

RTL8763B Series
Bluetooth Speaker Application
e s
i l
f t o
Figure 38.
a l
Bluetooth Speaker Application
d
t i z e
Bluetooth Audio Receiver Application
e n r i
i d h o
n f u t
o a 2 1
c t :
k n E C 2 1
t e m e M :
l u
Figure 39.
W T
Bluetooth Audio Receiver Application
1 3
e a o c
R9.15.
d
Auxiliary ADC Interface
1 6
e -
The RTL8763B supports high quality ADC input, designed-in 12-bit, and can be multiplexed with the
1
h
digital GPIO function. The allowable input swing is from 0V to min (VDDIO, 3V) in normal mode.
T
The allowable input swing is from 0V to 1 in bypass mode.
- 1
1 7
2 0
RTL8763B Series
VBAT:
1.62~5V
LDO
e s
CH0
ch_num[2:0]
i l
Level shift
CH1 ADC_inp SAR
f o
MUX
ADC control
BUS
adc_mode[1:0]
CH6
ADC digital
t
ADC_inn clk
CH7
Input swing :
0~min(VBAT, 3.6V)
a l
data[11:0]
d
t i z e
Figure 40.
n
Auxiliary ADC Interface Application
e r i
9.16. BT Wi-Fi Co-Existence (PTA)
i d h o
f t
The RTL8763B supports a BT/Wi-Fi co-existence scheme, PTA (Packet Traffic Arbiter)
n u
PTA is a handshake algorithm between Wi-Fi and Bluetooth in a Wi-Fi and Bluetooth co-existence
system.
o a 2 1
c t
PTA is used to control the priority of the Wi-Fi and Bluetooth traffic by accessing a 3-wire MAILBOX
:
block to avoid packet collisions in the same shared 2.4GHz ISM frequency band.
k n E C 2 1
e e
The PTA and mailbox signals can be defined via the PIN MUX table in the UI tool.
t m T M 3 :
a l c u W 1
Re d o 6
-1
h e 1
T - 1
1 7
Figure 41.
2 0
BT Wi-Fi Co-Existence (PTA)

RTL8763B Series
PTA and MAILBOX connection
I2C_SCL
3-wire
I2C_INIT
s
MAILBOX
I2C_SDA
BT_CK
BT_ACT
l e
PTA
BT_WLAN_ACT
fi o
t
BT_STE
a l d
9.17. PWM Interface
t i z e
e n r i
The RTL8763B supports up to six PWM signals. (* when applied for different user scenario, some more
timers will be occupied, e.g. RWS, push button, AUX-IN detection and buzzer….etc.)
i d h o
n f u t
o a 2 1
c t :
k n E C 2 1
t e m e M :
l u W T 1 3
e a o c
R d 1 6
e 1 -
T h 1
7-
Figure 42.
0 1
PWM Interface
2
RTL8763B Series
PWM Output Setting
The PWM module is controlled by register [ControlReg] [3].
When [ControlReg] [3] = 1, PWM is enabled and the PWM waveform is derived by controlling
[LoadCount] and [LoadCount2] registers and deciding the level high and level low time interval:
PWM level high timer = (TimerNLoadCount2 + 1) * timer_N_clk clock period
e s
PWM level low timer = (TimerNLoadCount + 1) * timer_N_clk clock period
i l
f
After the PWM timer is enabled, the register [LoadCount]和[LoadCount2] is loaded periodically. PWM
outputs low level during the time interval before LoadCount is decreased to zero; PWM outputs high
t o
l
level during the time interval before LoadCount2 is decreased to zero.
is the same, e.g. (LoadCount + 1) * timer_N_clk clock period.

i a
When [ControlReg] [3] = 0, PWM is disabled, the timer toggle still outputs; the output high and low timer
e d
PWM Complementary Output Setting
n t i z
e r
Only Timer2 and timer3 support PWM complementary output mode.
d o
Taking timer2 as an example, by setting register [PWM_CR2][12] and [PWM_CR3[12] to enable PWM
i h
complementary output and dead zone setting.
f t
When complementary output mode is enabled but not set in the dead zone, PWM_2P will be the same as
TimeGen Demo
n u
o
PWM2, while PWM2_N will be the reverse of PWM2.

em
1
mo
nD
o a
De
mo
e
2
De
G
1 2 3 4 5 6 7 8 9 10
en
o
e
en
c
em
eG
Tim
o o
G
PWM2 e
nD
Tim
m m
:
Tim
Ge
D e
TimeGen Demo
De
e
t
Tim
n n
Tim
e e TimeGen Demo
Time C 1
G G
eG
Tim
Time
en Tim
k n
TimeGen Demo
PWM2_P eG
Tim
De
e
mo en
G
E 2
De
eG
e
mo
nD
e e
en
M :
em
De
PWM2_N
t m
o
mo
l u W T 1 3 TimeGen
e a o c
Figure 43. Complementary Output Mode Enabled But Not Set in the Dead Zone
R d 1 6
The maximum setting of the dead zone is 256/32000 or 256/32768 according to the source of the low
e 1 -
power clock (internal or external 32K clock source).
TimeGen Demo
h
o
When the dead zone is set, the level high output of PWM2_P and PWM2_N contain a time delay
em
T Gen Demo -1 Gen Demo

mo
nD
De
o
Ge
em
1 2 3 4 5 6 7 8 9
en
nD o
e
em
e
eG
Tim
G
PWM2 e
nD
7
Tim
Tim
G e
TimeGen Demo e
Tim Tim
1
eG TimeGen Demo
Tim
Time e
en Tim
Dead Zone
TimeGen Demo
PWM2_P
im eG
Tim
De
e
T en
0
mo
G
De
eG
en
mo
en
De
2
De
mo
Dead Zone
PWM2_N
mo
TimeGen

RTL8763B Series
Figure 44. Maximum Setting of Dead Zone
TimeGen Demo
o
When the dead zone is longer than the PWM high level timer, PWM_P will always be low.
em
s
mo
nD
De
o
e
em
G
e
1 2 3 4 5 6 7 8 9
en
nD o
e
em
e
eG
Tim
mo mo
G
PWM2 Tim
e
nD
Tim
l
e
TimeGen Demo
De Tim
e
DeG
en en
Tim
i
eG TimeGen Demo
e G en
Tim
e G
Tim
TimeGen Demo
Dead Zone
Tim Tim
PWM2_P eG
Tim
De e
mo en
f o
G
De
eG
e
mo
nD
en
t
em
De
PWM2_N
o
mo
a l d
TimeGen
t i
Figure 45.
e
Dead Zone Is Longer Than PWM High Level Timer
z
TimeGen Demo
o
When the dead zone is longer than the PWM low level timer, PWM_N will always be low.
em
mo
on i
nD
De
o
e
em
G
1 2 3 4 5 6 7 8 9
e r
en
nD o
e
em
e
eG
Tim
mo
G
PWM2 e
nD
Tim
m
Tim
e
e e
en d o
G
D e
D
TimeGen Demo
Tim
en
Tim
TimeGen Demo
G
i h G
eG
Tim
e eTim
en
Dead Zone
TimeGen Demo
PWM2_P
Tim Tim eG
Tim
De
e
mo en
f t
G
De
eG
e
mo
nD
en
n u
em
De
1
PWM2_N
o
mo
c o a 2 TimeGen
t
Figure 46.
C :
Dead Zone Is Longer Than PWM Low Level Timer
1
e k e n E 2
t
9.18. Memory
m
Management
T M 3 :
a l c u W 1
The memory management unit manages the data buffer between the MCU and DSP.
e o
• System RAM: 128KB MCU RAM and 16KB cache RAM
R
•
•
d
DSP RAM: 176KB DSP RAM
ROM: 768KB ROM
1 6
•
e -
Serial FLASH support: The RTL8763B supports internal or external serial FLASH interface for IC to
1
h
storage UI, DSP parameter, voice prompt and ROM code fix setting
T 1
The external flash control interface supports 1-bit or 4-bit mode depending on the silicon package.
-
7
• RTL8763BF/BFR and RTL8763BO: Internal FLASH memory, 4-bit mode
•
•
0 1
RTL8763BA: 4-bit mode flash memory control interface
RTL8763BM and RTL8763BS: 1-bit mode flash memory control interface
2
RTL8763B Series
e s
i l
f t o
a l d
Figure 47.
t i
Memory Management
z e
e n r i
9.19.
d
Serial FLASH Memory Interface
i h o
The RTL8763BF/BFR supports 8M-bits on chip serial FLASH memory. We encourage using this
f
solution for sensitive PCB area designs.
n u t
The RTL8763BM, RTL8763BS, RTL8763BA do not support internal FLASH memory, but support a
o a
serial interface to connect to external serial FLASH memory for parameter and data storage purposes; for
2 1
c
example, voice prompt, UI parameters….etc.
t :
C 1
The RTL8763BM and RTL8763BS supports 1-bit and 2-bit mode. The RTL8763BA support 1-bit, 2-bit,
and 4-bit modes.
e k e n E 2
t m T M
The figures below show the connectivity of the serial FLASH memory.
3 :
a l c u W 1
Re d o 6
- 1
h e 1
T - 1
Figure 48.
7
Serial FLASH Memory; 1 and 2-bit Mode
1
2 0
RTL8763B Series
e s
i l
f t o
a l d
i e
Figure 49. Serial FLASH Memory; 4-bit Mode
9.20. n
Power Management Unit - Switch Mode Regulator t i z
d e o r
The RTL8763B series (except for the RTL8763BM) support dual switch mode regulator with planned
f i t h
external components, the inductor can be as small as 2.2µH with capacitor 2.2µF, which is ideal to design
into small PCB applications, for example, wearable devices, earbud headsets, RWS headsets…etc.
VBAT
o n u
HV_Audio
a 1
2
4.7uF 4.7uF
ADP_IN
c Switch
Feedback
t
sense
AVCC
:
C 1
4.7uF mode L1: 2.2uH AVCC/AVCCDRV
LX_
k n
Regulator
E 2
AUDIO 4.7uF
t e m e HV_CORE
M :
T 3
4.7uF
l u
VDDCORE
W 1
Feedback
Switch sense
e a o c mode
Regulator
LX_
CORE
L2: 2.2uH VDDCORE/VD12_SYN/VD12_RF
6
4.7uF
R d
Figure 50. Power Management Unit - Switch Mode Regulator
1
e 1 -
h
The 2.2µH inductor is recommended to be a wire-wound inductor. This has a small DCR (around 0.5Ω)
T 1
for good switching efficiency and good saturation current to guarantee the inductance is enough under
normal operation.
-
For both L1 and L2, the suggested specification is:
1 7
0
• IDC > 500mA
2
• DCR < 0.6Ω
• Wire-wound type

RTL8763B Series
IDC is defined as saturation current, which is further defined as a current that will cause the inductance to
be 20% degraded. This is quite different from the Irms or rated current, generally defined in inductor
specifications as a current that causes an increase in inductor temperature of 20°C, e.g. 20°C → 40°C.
The Irms number or rated current defined in the inductor datasheet may not be the logical buck inductor
following figures show two examples

e s
selection; so always ask the inductor vendor to provide the IDC current vs. inductance curve. The
MANUFACTURER PART
Table 16. Inductor Selection
VALUE (µH) DCR (mΩ)
i l ISAT (mA) Dimension (mm3)
ZENITHTEK
ZENITHTEK
ZADK-252012SB-2R2M
ZWP-0603-2R2K
2.2
2.2 f
93
560
1800
600
t o
2.5 x 2 x 1.2
1.2 x 1.8 x 1
TAIYO NRH3010T2R2MNV 2.2
a l 83 1300
d
3x3x1
t i z e
e n r i
i d h o
n f u t
o a 2 1
c t :
k n E C 2 1
t e m e M :
l u
Figure 51.
W T
Inductor Selection
1 3
•
e a o c
The capacitor 4.7µF specification should be X5R or above in order to ensure the ripple of the buck
R
•
d
output power is small for good RF and audio characteristics
1 6
The specification of the capacitor 4.7µF at VBAT and ADP_IN should be X5R or above
•
e -
The routing trace of LX_AUDIO and LX_CORE on PCB should be short, and as wide as possible.
1
h
The 2.2µH inductor and 4.7µF capacitor should be close to the chip
T - 1
Power Management Unit - Low Drop Linear Regulator
1 7
The RTL8763B supports the low drop linear regulators listed below:
LDO AUX1
2 0
Output with one capacitor 1µF; suggested to be X5R or above.
LDO AUX1 LQ

RTL8763B Series
Shares the same pin of LDO AUX1 as pin out.
LDO AUX2
MICBIAS LDO
e s
LDO VPA33
i l
No need to add output capacitor. The output is adjustable according to the MEMs MIC specification.

f t o
l
The switch mode regulator can be programmed as a low drop linear regulator to eliminate the 2.2µH
inductor if current consumption is not a concern.
i a e d
9.21. Battery Charger
n t i z
e r
The RTL8763B supports an integrated charger for Li-Ion battery application.
protection.
i d h o
The supported charger current can be programmed in the UI tool; maximum is 400mA with thermal
Charger Mode
n f
Battery Voltage
u t
Table 17. Charger Mode Definition
Charger Current Note
Trickle charger mode
o
BAT < 3V
a
0.1C -
2 1
c
Charger current is defined by
:
customer with the UI tool.
t
Constant Current Mode 3.0V ≤ BAT ≤ 4.2V or Customer defined; 400mA
C 1
Customers should pay attention
k n
(CC Mode) 4.35V max.
to the charger current setting
e e M E 2
with regard to their battery pack.
:
The CV mode voltage can be
l t
Constant Voltage Mode
u m T
Controlled by MCU, the
charger current slowly
3
defined with the UI tool.
Customers should set the CV
W 1
BAT = 4.2V or 4.35V
a c
(CV Mode) degrades from CC mode and mode voltage according to the
stops at 0.1C Li-Ion battery specification. Do
Re Re-Charge Mode
d o BAT ≤ 4.0V -
6
not set over specification.
-
- 1
h e
Trickle Charger Mode
1
T 1
If the battery voltage is below 3V, the charger will charge the battery with a low current of 0.1C. If the
-
battery voltage does not rise up to 3.0V before time out, the charger will be in error and stop.
1 7
0
Constant Current Mode
reaches 4.2V. 2
If the battery voltage is over 3.0V, the charger will be in constant current mode until battery voltage
The constant current is defined in the UI tool by customer product definition.

RTL8763B Series
Constant Voltage Mode

If the battery voltage reaches 4.2V or 4.35V, the charger will go into constant voltage mode and the
tool by customer.
e s
charge current will start to drop until reaching 0.1C. Note that the stop current can be defined in the UI
i l
f o
Re-Charge Mode
l t
If the battery charge process is completed, the charger will stop charging the battery. If the adapter is not
removed and battery voltage drops over a period of time, the charger will re-start the charging process
a d
with a 0.25C charge current.
t i z e
** Realtek verified the battery charger on Realtek EVB and branded Li-Ion batteries. Realtek confirm that
the charger design is suitable based on this environment. The result may be changed due to different PCB
n i
layout, schematics design, rBOM, and battery package; customers should verify the battery charger
e r
function themselves in each design to assure the charger design correct for the application.
Charge Curve
i d h o
f t
The figure below is a battery voltage vs. charger current curve across different charger modes.
n u
o a
The Li-Ion battery charger in the RTL8763B series is very flexible for customers using various Li-Ion
2 1
c
batteries. It supports both 4.2V and 4.35V Li-Ion battery packs. The charge to full voltage can be
programmed in the UI tool by the customer.
t C 1 :
e k e n E 2
t m T M 3 :
a l c u W 1
Re d o 6
- 1
h e 1
T - 1
Figure 52.
1 7
Battery Voltage vs. Charger Current Curve
2 0
RTL8763B Series
Battery Charger Protection Scheme
The RTL8763B monitors the safety of the charger process and integrates several protection schemes. If
the battery is damaged or ageing after a long time of operation, the RTL8763 will implement the
following protection:
•
e s
If the battery voltage does not rise to the target voltage in a defined time period, the battery will be
judged as a dead battery and the charger will time out and then disable itself.
i l
• Chip thermal detection will be implemented if the chip temperature rises up continuously and over the
defined threshold. In such cases the charger current will be decreased or stopped.
• Watchdog protection; the system will be reset if the system hangs. f t o
attached to the battery pack.
a l
• Ambient detection design will monitor the battery temperature with an external thermistor close or
d
t i z e
** Realtek verified the battery charger on Realtek EVB and branded Li-Ion batteries. Realtek confirm that
the charger design is suitable based on this environment. The result may be changed due to different PCB
e n r
function themselves in each design to assure the charger design correct for the application.
i
layout, schematics design, rBOM, and battery package; customers should verify the battery charger
i d
Ambient Detection for Battery Charge Protection
h o
n f u t
The RTL8763B supports an excellent, high precision ambient detection algorithm design with the
reference circuit below and with a specified external thermistor located in the battery pack. With this
o a
specified thermistor (QVL: Murata, part number: NCP18WB473D03RB or NCP18WB473F10RB), a
2 1
c
detection temperature of 0~5°C and 40~45°C can be achieved within +/-2°C difference. When in charger
t :
C 1
mode, if the reading temperature of the battery pack is out of (0~45°C) range, the charger will stop until
UI tool.
e k e n
the temperature is back to this range again. The stop and re-start temperature can be programmed with the
E 2
t m
AUXLDO 1.8V
T M 3 :
a l c u W 1
e o
180KΩ+/-1%
R
AUX
LDO
ADC
Core
d
ADC
Battery pack
1 6
-
B+
e 1
Thermistor is suggested to
h
be located in battery pack
Suggested part:
1
RTL8763 Murata NCP18WB473D03RB
T
B-
7 -
Figure 53.
0 1
Ambient Detection for Battery Charge Protection
2
RTL8763B Series
9.21.1. PMU Protection Scheme

OVP
s
OVP (Over Voltage Protection) is used to protect the battery charger. The RTL8763B continuously
e
monitors the battery voltage. If an over voltage condition occurs, the charger will stop immediately. The
OVP threshold is configurable in the UI tool.
OCP
i l
f o
OCP (Over Current Protection) is used to protect the PMU in case of an over current condition occurs. It
limits the regulator output to protect the PMU from burning out.
t
UVP
a l d
i e
UVP (Under Voltage Protection) is used to protect the system from operating under a low voltage
condition. The RTL8763B supports both SW UVP and HW UVP. If the battery voltage is below the
n t i z
lower band of the operating threshold, the system will be in hibernation mode first, and the PMU will
force a stop of the output, or force a reset if the voltage continues to drop below the brown out or black
out threshold.
•
d e o r
SW UVP: Configurable in the UI tool. If the battery voltage is below the pre-defined threshold, FW
•
f i
will turn off the system and hibernate
t h
HW UVP: The RTL8763B supports hardware UVP to protect the system from operating under an
n u
un-defined voltage. There are two thresholds, brown out and black out. The UVP hardware protection
o a 1
2
scheme will be triggered when a low voltage condition occurs. The UVP states will be resolved only
c
when the voltage has recovered from the VLOW+Vthreshold
t :
k n E C 2 1
t e m e M :
l u W T 1 3
e a o c
R d 1 6
e 1 -
T h 1
Figure 54.
-
PMU Protection Scheme
7
LED
0 1
2
The RTL8763B supports dynamic GPIO assignment to drive the LED for status indication. It offers
flexibility to assign the GPIO at the best pin out location to ease PCB trace routing constrictions.

RTL8763B Series
The method of LED indication can be selected in the UI tool and programmed into FLASH memory in
the mass production process. The LED can still be active in deep sleep mode without the need for MCU
control.
s
Table 18. LED
e
Parameter Min. Typ. Max. Unit
l
Driving Capacity - - 12 mA
GPIO VOH 1.8 - 3.6 V
GPIO VOL -
f
0.2
i -
o
-
l t
i a e d
n t i z
de o r
f i t h
o n a u 1
c : 2
k n t C 1
e e M E : 2
l t um T 3
a c W 1
Re d o 6
- 1
h e 1
T - 1
Figure 55.
1 7
LED
0
Where VF is defined in the LED specification, VOL is defined as the GPIO drive low level, typically 0.2V.
2
VOH depends on the LDO_AUX output level. If LDO_AUX=1.8V, then VOH=1.8V. If LDO_AUX=3.3V,
then VOH=3.3V.
R1=330Ω for LED drive with 4mA with LDO_AUX=3.3V.

RTL8763B Series
R1 can be adjusted according to the LED brightness needed.
I/O Mux
e s
i l
f t o
a l d
t i z e
e n r i
i d h o
n f u t
o a 2 1
c t :
k n
Figure 56. I/O Mux
E C 2 1
t e m e M :
T 3
The table below shows a PIN MUX available list. Each function in the table can be directed to the
a l c u
selected GPIO in the UI tool. These parameters can be set and programmed into the IC.
Table 19.
W
PIN MUX Available List
1
Re 0 IDEL
2
d o
qdec_phase_a_z
5 SPI0_CLK 7
KEY_COL_17 0
1
6
SDI (CODEC -
1
2
ADCDAT
1
5 0 (master only) 5 slave) (SPORT0)
0 5
-
1 1
e
HCI_UAR 2 5 SPI0_MO 7 SDO (CODEC - DACDAT
1
1 qdec_phase_b_z KEY_COL_18 0 2
T_TX 6 1 (master only) 6 slave) (SPORT0)
h
1 6
2
T
HCI_UAR 2
T_RX 7
LOG0_UART
_TX
5
2
SPI0_MI
(master only) 7
7
- 1
KEY_COL_19 0
1
LRC_I (PCM)
1
2 MCLK
7
2 7
1
1
I2C1_DA 3 5 8
8 IRDA_TX KEY_COL_0 KEY_ROW_5 0 BT_COEX_I_2 - -
0
T 3 8 3
8
2
1
3 5 8
9 PWM0_P IRDA_RX KEY_COL_1 KEY_ROW_6 0 BT_COEX_I_3 - -
4 9 4
9

RTL8763B Series
1
1 3 DATA_UART 6 8
PWM0_N KEY_COL_2 KEY_ROW_7 1 BT_COEX_O_0 - -
0 5 _TX 0 5
0
1
s
1 3 DATA_UART 6 8
PWM1_P KEY_COL_3 KEY_ROW_8 1 BT_COEX_O_1 - -
1 6 _RX 1 6
e
1
l
1
1 3 DATA_UART 6 8
PWM1_N KEY_COL_4 KEY_ROW_9 1 BT_COEX_O_2 - -
i
2 7 _CTS 2 7
2
f o
1
1 3 DATA_UART 6 8
t
PWM0 KEY_COL_5 KEY_ROW_10 1 BT_COEX_O_3 - -
3 8 _RTS 3 8
3
1
4
PWM1
3
9
SPI1_SS_N_0
(master only)
6
4
KEY_COL_6
8
9
a l
KEY_ROW_11 1
1
d
PTA_I2C_CLK
(slave only)
- -
i e
4
t z
1
1 4 SPI1_SS_N_1 6 9 PTA_I2C_DAT
PWM2 KEY_COL_7 DWGPIO 1 - -
n i
5 0 (master only) 5 0 (slave only)
5
e r
1
1 4 SPI1_SS_N_2 6 9 PTA_I2C_INT_O
d o
PWM3 KEY_COL_8 LRC (SPORT1) 1 - -
6 1 (master only) 6 1 UT
6
1
7
PWM4
4
2
SPI1_CLK
(master only)
f
6
7 i
KEY_COL_9
9
2
t h
BCLK
(SPORT1)
1
1 DSP_GPIO_OUT - -
n u
7
1
PWM5
4
o
SPI1_MO 6
KEY_COL_10
9
a
ADCDAT
1
1 DSP_JTCK - -
2 1
c
8 3 (master only) 8 3 (SPORT1)
8
1 4 SPI1_MI (master 6 9
t DACDAT
1
C 1 :
k n
PWM6 KEY_COL_11 1 DSP_JTDI -
9 4 only) 9 4 (SPORT1)
E 2
9
2
t
PWM7
e4 SPI0_SS_N_0 7
m e
KEY_COL_12
9
SPDIF_TX
M
1
2 DSP_JTDO
: -
T 3
0 5 (slave) 0 5
l u
0
a
2 qdec_phas 4 SPI0_CLK
c
7
KEY_COL_13
9
W
DMIC1_CLK 2
1
DSP_JTMS
1 -
e o
1 e_a_x 6 (slave) 1 6
1
R 2 qdec_phas 4
2 e_b_x 7
d
SPI0_SO (slave)
7
2
KEY_COL_14
9
7
DMIC1_DAT 2
1
1 6
DSP_JTRST -
-
2
h
2 qdec_phas 4
e SPI0_SI (slave)
7
KEY_COL_15
9 LRC_I (CODEC
1
1
2 LRC (SPORT0) -
1
3 e_a_y 8 3 8 - slave)
T
3
2 qdec_phas 4
4 e_b_y 9
SPI0_SS_N_0
(master only)
7
4
KEY_COL_16
9
9
7 -
BCLK_I
(CODEC -
slave)
1
2 BCLK (SPORT0)
4
-
0 1
2
RTL8763B Series
9.22. Reference Circuits

9.22.1. RTL8763BM Reference Circuits
TP1
1
C1
1uF
MIC1_N
e s ADP in reset
(Optional)
1
MICBIAS C4
R1 1uF X5R HW_RST_N
l
2K2
1
3
VDD_ADP
R2 C5
C
2
SPIF_SCLK
2K2 VDD_LDO_AUX2 1uF
SPIF_CS#
SPIF_SO
C3 C6 1 Q1
i
MIC1_N
SPIF_SI
TP2 1uF 1uF X5R VDD_1V2 B 3904
LED1
2
1 MIC1_P LX_CORE L2 2.2uH
E
ZWP-0603-2R2K-V0 R3
C7 1K
2
f o
Analog MIC1 4.7uF
41
40
39
38
37
36
35
34
33
32
31
VDD_1V8 X5R
SO/SIO1
CS#
SI/SIO0
P2_0
HV33
LDO_AUX2
SCLK
EPAD
MIC1_N
NC
NC
Must reserve TP12
TP
t
KEY 2 1 C128
UART_RX 1uF
X5R VDD_ADP
TP13 MIC1_P 1 30
MIC1_P LDO_A LED
l
TP C10
KEY 0 1 MIC_BIAS 2 29 4.7uF R6 D1
UART_TX MICBIAS HV_A VDD_ADP C12 X5R 100 LED
3 28 1uF near Pin 28 LED0
TP14 VDD_1V8 VREF ADPIN VDD_VBAT X5R
a d
TP C9 4 27
LED1 1 1uF C11 AVCC_DRV VBAT VDD_VBAT
LOG X5R 1uF AOUT_RN 5 26 R7 D2
X5R AOUT_RN HV_CORE C14 C15 100 LED
TP15 AOUT_RP 6
RTL8763BM 25 LX_CORE 4.7uF 4.7uF LED1
i e
TP AOUT_RP LX_CORE X5R X5R
HW_RST_N 1 AVCC 7 24 near Pin 27
RESET VDD_1V2 AVCC ADPSO VDD_1V2 C16
C17 8 23 1uF
VD12_RTX VDDCORE
t z
1uF VDD_3V3 C19 X5R
X5R C18 9 22 KEY 1 1uF
1uF VD33_PA P0_7/ADC_7 X5R
X5R C20 RFIO 10 21 KEY 2
Speaker out 1uF RFIO_IQM P0_6/ADC_6
n i
X5R
HW_RST_N
LDO_AUX1
VD33_SYN
VD12_SYN
TP7
DIG_OUT
TP
VPA33
1 AOUT_RN
P1_0
P1_1
XO
e r
XI
TP8 U1
11
12
13
14
15
16
17
HW_RST_N18
19
20
TP RTL8763BM
1 AOUT_RP Frequency Tolerence: 5ppm;Frequency Stability ov er temperature range:15ppm.
d o
DIGOUT
VDD_3V3 R53-027_SX-2520_40MHz_9pF
KEY0
LED0
2 4
XO
GND GND
XI
C21 XI 1 3 XO
i h
VDD_3V3 C22 1uF X1 X2
VDD_1V2 1uF X5R X1
X5R C25 40MHz Xtal
VDD_LDO_AUX2 0.1uF
f t
C23
U2 1uF C24 VDD_LDO_AUX1
MX25R8035F X5R 1uF
8 X5R
VDD 3
n u
SPIF_CS# 1 WP#/SIO2 7 C26
SPIF_SO 2 CS# NC/SIO3 1uF
SO/SIO1
1
SPIF_SI 5 X5R
SPIF_SCLK 6 SI/SIO0 4
SCLK GND
RFIO
c o Button
a 2
:
SW1
TP9 RF Test Point SW-TACT
t
2
PCB Antenna GND KEY 0 VDD_VBAT TP10 VDD_ADP TP49
C 1
Power KEY
RF
L3 TP TP
2.2nH 1 1
1
k n
ACX HI1005-1C
R14 0 1 2 RFIO SW2
SW-TACT
E 2
ANT1
REALTEK Semiconductor Corp.

C28 C29 22pF
1.5pF 1.5pF C27 KEY 1 TP11 TP50
e e
NPO NPO L18 NPO C30 C31 TP TP
0 0.6pF 1.2pF 1 1 Addr: No.2, Innovation Rd. II, Hsinchu Science Park, Hsinchu 30076, Taiwan
TEL: 886-3-5780211
M :
ACX HI1005-1C NP0 NP0
1 2 SW3 Title
SW-TACT RTL8763BM_QFN40_reference design_0V7
t m
KEY 2 Size Document Name Rev
T 3
Antenna Matching Circuit RTL8763BM_QFN40_reference design_0V7 0.7
Value depand on Antenna
l u
Date: Thursday , September 28, 2017 Sheet 1 of 1
W 1
Figure 57. RTL8763BM Reference Circuits
e a o c
R d 1 6
e 1 -
T h 1
7 -
0 1
2
RTL8763B Series
9.22.2. RTL8763BF/BFR Reference Circuits

C1
TP1
1
1uF
MIC1_N LX_AUDIO L1 2.2uH
VDD_1V8 ADP in reset
Frequency Tolerence: 5ppm;Frequency Stability ov er temperature range:15ppm. ZWP-0603-2R2K-V0 (Optional)
1
MICBIAS C2
s
R1 R53-027_SX-2520_40MHz_9pF 4.7uF HW_RST_N
2K2 C4 X5R
1
3
X1 1uF X5R VDD_ADP
R2 40MHz Xtal C5
C
2
e
2K2 1uF
C3 2 4 1 Q1
TP2 1uF GND GND VDD_LDO_AUX2 VDD_1V2 B 3904
2
1 1 3
BUZZER
MIC1_P XI XO C6 LX_CORE L2 2.2uH
MIC1_N
MIC2_N
40 MIC_BIAS
MIC1_P
MIC2_P
X1 X2
E
1uF X5R ZWP-0603-2R2K-V0 R3
KEY2
LED1
l
C7 10K
2
Analog MIC1 4.7uF
X5R
41
39
38
37
36
35
34
33
32
31
C8
i
TP3 1uF
MIC2_P/AUXL
P2_2
P2_1
P2_0
HV33
LDO_AUX2
MIC_BIAS
MIC1_P
GND
MIC1_N
MIC2_N/AUXR
1 MIC2_N
1
MICBIAS VDD_ADP
f o
R4 1 30 LX_AUDIO
2K2 VDD_1V8 VREF LX_AUDIO C10 LED
1
C9 2 29 4.7uF R6 D1
R5 1uF C11 AVCC_DRV HV_AUDIO VDD_ADP C12 X5R 100 LED
2
2K2 X5R 1uF AOUT_LP 3 28 4.7uF near Pin 28 LED0
t
C13 X5R AOUT_LP ADP_IN VDD_VBAT X5R
TP4 1uF AOUT_LN 4 27
2
1 MIC2_P AOUT_LN VBAT VDD_VBAT

AOUT_RN 5 26 R7 D2
AOUT_RN HV_CORE
l
C14 C15 100 LED
AOUT_RP 6 25 LX_CORE LED1
Analog MIC2(Optional) AOUT_RP RTL8763BF LX_CORE
4.7uF
X5R
4.7uF
X5R
AVCC 7 24 near Pin 27
VDD_1V2 AVCC ADPSO VDD_1V2 C16
a d
C17 8 23 1uF
TP5 1uF VDD_3V3 VD12_RTX VDDCORE C19 X5R
TP X5R C18 9 22 KEY 1 1uF
1 AOUT_LN VD33_PA P0_7
1uF
X5R C20 RFIO 10 21 THM_DET
X5R Buzzer and Thermal Detect
HW_RST_N
i LDO_AUX1
e
RFIO_IQM P0_6 (Optional)
VD33_SYN
VD12_SYN
1uF
DIG_OUT
TP6 X5R
VPA33
TP
P1_0
P1_1
1 AOUT_LP
XO
XI
t z
VDD_VBAT
U1
11
12
13
14
15
16
17
HW_RST_N18
19
20
TP7
TP Must reserve
1 AOUT_RN
DIGOUT
VDD_3V3
n i
TP12 R8
KEY0
TP LED0 50 J1
XO
TP8
XI
THM_DET 1
TP UART_RX C21 VDD_LDO_AUX1 1
1 AOUT_RP VDD_3V3 C22 1uF 2 Buzzer
e r
TP13 VDD_1V2 1uF X5R
TP X5R C25
3
KEY 0 1 0.1uF
Speaker out UART_TX C23 R10
C
d o
1uF C24 VDD_LDO_AUX1 180K
TP14 X5R 1uF BUZZER R11 50 1
TP X5R THM_DET B Q2
LED1 1
ADP_IN
E
LOG C26 R13 3904
i h
CON1
TP15 1uF R12 10K
2
5 TP X5R THM
9 GND 4 HW_RST_N 1 MURATA
8 GND ID 3 VDD_ADP RESET NCP18WB473D03RB
7 GND D+ 2 NCP18WB473F10RB
f t
6 GND D- 1 Attached on battery pack
GND VBUS
Micro USB
n u
GPIO define for different application
1
Li-on Battery
RFIO Button SW1 1: 3 Key/2 MIC
o a
TP9 RF Test Point SW-TACT
2 2: 3 Key/1 MIC/Thermal/Buzzer
2
PCB Antenna GND KEY 0 VDD_VBAT TP10
Power KEY
RF
L3 TP
c
2.2nH 1
1
ACX HI1005-1C
R14 0 1 2 RFIO SW2
:
SW-TACT
ANT1

C28 C29 22pF
t
1.5pF 1.5pF C27 KEY 1 TP11
NPO NPO L17 NPO C30 C31 TP
Addr: No.2, Innovation Rd. II, Hsinchu Science Park, Hsinchu 30076, Taiwan
C 1
0 0.6pF 1.2pF 1
ACX HI1005-1C NP0 NP0 TEL: 886-3-5780211
1 2
k n
SW3 Title
SW-TACT RTL8763BF_QFN40_reference design_0V9
E 2
KEY 2 Size Document Name Rev
Antenna Matching Circuit RTL8763BF_QFN40_reference design_0V9 0.9
e e
Value depand on Antenna
t
Figure 58.
m
RTL8763BF/BFR Reference Circuits
T M 3 :
a l c u W 1
Re d o 6
- 1
h e 1
T - 1
1 7
2 0
RTL8763B Series
9.22.3. RTL8763BS Reference Circuits

C1
TP1
1
1uF
MIC1_N Frequency Tolerence: 5ppm;Frequency Stability ov er temperature range:15ppm. LX_AUDIO L1 2.2uH
VDD_1V8 ADP in reset
C2 ZWP-0603-2R2K-V0 (Optional)
1
MICBIAS R53-027_SX-2520_40MHz_9pF 1uF X5R C3
s
R1 4.7uF HW_RST_N
2K2 2 4 X5R
1
3
GND GND VDD_ADP
R2 XI 1 3 XO C4
C
2
SPIF_SCLK
X1 X2
e
2K2 VDD_LDO_AUX2 1uF
SPIF_CS#
SPIF_SO
C6 X1 C5 1 Q1
MIC1_N
MIC2_N
SPIF_SI
MIC2_P
TP2 1uF 40MHz Xtal 1uF X5R VDD_1V2 B 3904
LED1
LED2
2
P2_0
1 MIC1_P LX_CORE L2 2.2uH
E
ZWP-0603-2R2K-V0 R3
l
C9 1K
2
Analog MIC1 U1 4.7uF
49
48
47
46
45
44
43
42
41
40
39
38
37
X5R VDD_ADP
MIC2_P/AUXL
SPIFLASH_CS#
P2_4
P2_1
P2_0
HV33
LDO_AUX2
SPIFLASH_SCLK
SPIFLASH_SO
GND
MIC1_N
MIC2_N/AUXR
SPIFLASH_SI
C8 C7
i
TP3 1uF 4.7uF
1 MIC2_N X5R
MIC1_P 1 36 LX_AUDIO near Pin 39 Must reserve
1
MICBIAS MIC1_P LX_AUDIO
f o
R4 MICBIAS 2 35 TP4
2K2 MICBIAS HV_AUDIO VDD_ADP C10 VDD_VBAT TP
1
3 34 4.7uF 1
KEY 0/SLIDE_SW
R5 VDD_1V8 VREF ADP_IN VBAT X5R C12 UART_TX
2
2K2 C11 4 33 4.7uF
t
C14 1uF C13 AVCC_DRV VBAT X5R TP5
TP6 1uF X5R 1uF AOUT_LP 5 32 near Pin 38 TP
2
1 MIC2_P X5R AOUT_LP HV_CORE C15 KEY 2 1

AOUT_LN 6 31 LX_CORE 4.7uF UART_RX
AOUT_LN LX_CORE
l
X5R
AOUT_RN 7 30
Analog MIC2(Optional) AOUT_RN RTL8763BS ADPSO VDD_1V2 C16
TP7
TP
AOUT_RP 8 29 1uF P2_0 1
Speaker out AOUT_RP VDDCORE C17 X5R LOG
a d
AVCC 9 28 KEY 4/SLIDE_SW 1uF
TP8 VDD_1V2 AVCC P0_7 X5R TP9
TP C18 10 27 KEY 1 TP
1 AOUT_LP 1uF VD12_RTX P0_6 HW_RST_N 1
X5R VDD_3V3 C19 11 26 NFC_DET RESET
i e
0.1uF VD33_PA P0_3
TP10 X5R RFIO_IQM 12 25 THM_DET
HW_RST_N
LDO_AUX1
RF_IQM P0_2
VD33_SYN
VD12_SYN
TP
DIG_OUT
1 AOUT_LN
VPA33
t z
C20
P1_0
P1_1
P0_0
P0_1
VDD_ADP TP12 VBAT
XO
1uF TP13
XI
TP11 X5R TP TP
TP 1 1
13
14
15
16
17
18
19
HW_RST_N20
21
22
23
24
1 AOUT_RN BUZZER
n i
KEY 3
DIGOUT
TP14 VDD_3V3
KEY0
KEY2
TP TP15 TP16
XO
XI
1 AOUT_RP TP TP
e r
1 1
VDD_3V3 C21 C22
NFC_DET VDD_1V2 1uF 1uF
X5R C23 X5R VDD_VBAT
3
d o
TP17 0.1uF
TP C25
1 NFC_SG 2 Q2 1uF C24 VDD_LDO_AUX1 LED LED
STS2306 X5R 1uF VDD_LDO_AUX1
Reserved R6
i h
R7 C26 VDD_LDO_AUX2 VDD_LDO_AUX2 50 J1
1
NP 1uF C27
NFC Optional
1uF
X5R
1
2 Buzzer R8
f t
R9 R10 180K
TP18 power on by button or slide switch 330 330
3
TP SW1 THM_DET
1 SW-TACT
C
Button
n u
KEY 4/SLIDE_SW BUZZER R11 50 1 R12
SW2 D1 D2 B Q3 THM
1
SW-TACT LED LED MURATA
E
C28 R13 3904 NCP18WB473D03RB
0.1uF KEY 4/SLIDE_SW 10K NCP18WB473F10RB
o a
2
Attached on battery pack
2
LED1 LED2
RFIO TP19 RF Test Point SW3 SW4
c
Antenna Matching Circuit 2 SW-TACT SW-TACT
Value depand on Antenna GND
KEY 0 KEY 2
RF
C29 L3 VDD_LDO_AUX2
:
NP0 2.2nH Power KEY
1

20pF ACX HI1005-1C U2
t
R14 0 1 2 RFIO_IQM MX25R8035F
SW5 SW6 8
ANT1 VDD Addr: No.2, Innovation Rd. II, Hsinchu Science Park, Hsinchu 30076, Taiwan
C 1
C30 C31 L19 SW-TACT SW-TACT 3
1.5pF 1.5pF 0 C32 C33 SPIF_CS# 1 WP#/SIO2 7 TEL: 886-3-5780211
KEY 1 KEY 3 SPIF_SO 2 CS# NC/SIO3
k n
NPO NPO ACX HI1005-1C 0.6pF 1.2pF Title
1 2 NP0 NP0 SPIF_SI 5 SO/SIO1
SPIF_SCLK 6 SI/SIO0 4
RTL8763BK_QFN56_reference design_0V7
E 2
SCLK GND Size Document Name Rev
PCB Antenna RTL8763BK_QFN56_reference design_0V7 0.7
e e
t
Figure 59.
m
RTL8763BS Reference Circuits
T M 3 :
a l c u W 1
Re d o 6
- 1
h e 1
T - 1
1 7
2 0
RTL8763B Series
9.22.4. RTL8763BA Reference Circuits

Frequency Tolerence: 5ppm;Frequency Stability ov er temperature range:15ppm. L1 AVCC_DRV
R53-027_SX-2520_40MHz_9pF 2.2uH Audio Reserve for EMI supression Reserve for EMI supression
C1 C2 LX_AUDIO
2
GND GND
4 1uF 1uF ZWP-0603-2R2K-V0 Amplifier GND_A GND_A
X5R X5R C3 >4.7uF, X5R
XI 1 3 XO C4 TP2 C5
s
X1 X2 TP1 L2 BEAD L3 BEAD
C6 4.7uF 1 SPK_O_L_P 680pF 1 2 OUT_LP TP 1SPK_O_R_P680pF 1 2 OUT_RN
TP3 1uF X1 VDD_LDO_AUX2 TP
1 MIC1_N 40MHz Xtal 1 SPK_O_L_N 1 2 1 SPK_O_R_N 1 2 OUT_RP
OUT_LN
AUXIN_DET
BOOST_EN
TP4 TP5
L4 BEAD L5 BEAD
AUXIN_R
1
59 SPIF_SCLK
AUXIN_L
USB_DM
MICBIAS
USB_DP
C7 C8
63 SPIF_SIO2
62 SPIF_SIO1
60 SPIF_SIO0
58 SPIF_SIO3
TP
61 SPIF_CS#
TP
R1 C9 L6 VDD_1V2 680pF 680pF
LED2
LED1
e
GND_AUDIO_DRIVE
2K2 1uF 2.2uH
1
X5R LX_CORE GND_A GND_A

R2 ZWP-0603-2R2K-V0 GND_A
2
2K2 C10 >4.7uF, X5R U2
69
68
67
66
65
64
57
56
55
54
53
52
13
C11 ALC105-VF
TP6 1uF 4.7uF OUT_LP 1 12 G2
DP
V33_USB
SPIFLASH_SCLK
AUXIN_L
SPIFLASH_WP#/SIO2
SPIFLASH_SO/SIO1
SPIFLASH_CS#
SPIFLASH_SI/SIO0
SPIFLASH_HOLD#/SIO3
P2_3
P2_2
P2_1
P2_0
HV33
LDO_AUX2
GND
AUXIN_R
GND
DM
2
1 OUT_LP G2 R3
l
MIC1_P
OUT_LN 2 11 G1 NC
VDD_AMP_DRIVE OUT_LN G1 0.33uF
3 10 C12 R4 0
C13 1uF AOUT_LP
MIC2_N 1 51 LX_AUDIO C14 PVDD1 IN_L/DIFF-
MIC2_N LX_AUDIO
GND_A
4.7uF C15 C16 4 9 C17 C18 1uF AOUT_RP
MICBIAS MIC2_P 2 50 HV_AUDIO PVDD2 IN_R/DIFF+
Analog MIC1 X5R VDD_ADP 0.33uF
i
MIC2_P HV_AUDIO 10uF 0.1uF R5 0
OUT_RN 5 8
MIC1_N 3 49 OUT_RN BYPASS
MIC1_N ADPIN GND_AUDIO_DRIVE C19 2.2uF R6
OUT_RP 6 7
C20 MIC1_P 4 48 VDD_VBAT C21 OUT_RP PD# NC
1uF MIC1_P VBAT 4.7uF
5 47 HV_CORE D1
X5R C22 X5R
f o
1uF MICBIAS HV_CORE Schottky GND_A
X5R AVCC_DRV 6 46 LX_CORE C24 C23 AMP_EN# Reserve for Input attenuation
VREF LX_CORE 4.7uF 4.7uF To have optimized output power
7 45 X5R X5R
AVCC_DRV ADPSO
GND_A
R7 R8
G2
1 AOUT_LP 8 44 R10
TP7 VDDCORE C25 10K 10K R9
AOUT_LP
t
C26 1uF
TP9 1uF TP8 1 AOUT_LN 9 43 X5R VDD_1V2 NC 0
1 MIC2_N AOUT_LN
RTL8763BA 32K_XI
0
GND_A
TP10 1 AOUT_RN 10 42
AOUT_RN 32K_XO R13
1
MICBIAS VDD_AMP L7 VDD_A

R11 TP11 1 AOUT_RP 11 41 KEY5 C27 BEAD R12
AOUT_RP P0_7 1 2 VDD_AMP_DRIVE
2K2 1uF
l
1
12 40 KEY4 X5R
AVCC P0_6 NC 0 0
G1
R14 VDD_1V2
2
2K2 C28 13 39 VDD_A L9 VDD_AMP_DRIVE

C30 1uF VD12_PA P0_5 VBAT L8 BEAD
RFIO_TPM 14 38 NC 1 2
TP12 1uF X5R VDD_1V2
1 2
2
1 MIC2_P C29 RFIO_TPM P0_4
a d
1uF 15 37 NFC_DET C34
X5R VDD_3V3 VD12_RTX P0_3 C31 C32 C33 100uF
C35 16 36 THM_DET 1uF 10uF L11 100uF
1uF VD33_PA P0_2 BEAD
RFIO_IQM 17 35 1 2 1 2
X5R GND_AUDIO_DRIVE
C36 RFIO_IQM P0_1
HW_RST_N
LDO_AUX1
VD33_SYN
VD12_SYN
L10
i e
Analog MIC2 1uF GND_A GND_AUDIO_DRIVE
DIG_OUT
X5R BEAD
VPA33
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
P0_0
XO
XI
VDD_VBAT
18
19
20
21
22
23
24
25
ANT_SWB 26
27
AMP_EN# 28
29
30
HW_RST_N31
32
33
34
Must reserve
t z
VDD_LDO_AUX1 LED LED
ANT_SW
BUZZER
TP13
TP R15
XO
KEY0
KEY1
KEY2
KEY3
XI
VDD_LDO_AUX1 KEY2 1 VDD_LDO_AUX2 VDD_LDO_AUX2 50 J1

U3 UART_RX
6 R16 1
n i
AUXIN_L C37 1uF/X5R 1 VDD_3V3 VDD_1V2 TP14 180K 2 Buzzer
2 R17 C39 VDD_LDO_AUX1 VDD_3V3 TP R18 R19
AUXIN_R C38 1uF/X5R 3 NP 1uF KEY0 1 THM_DET 330 330
3
4 X5R UART_TX
AUXIN_DET 5 C40 C41
C
VDD_LDO_AUX2 HW_RST_N 1uF 1uF C42 C43 TP15 R21
e r
X5R X5R 1uF 1uF TP THM BUZZER R22 50 1
PJ2503B B
R20 X5R X5R LED1 1 MURATA D2 D3 Q1
1M LOG NCP18WB473D03RB LED LED
E
R23 C44 TP16 NCP18WB473F10RB R24 3904
10K 0.1uF TP Attached on battery pack 10K
2
HW_RST_N 1
d o
RESET
LED1 LED2
Audio Jack
i h
Li-Ion Battery
ANT_SW C46 L12 VDD_LDO_AUX2
20pF 3.9nH
C45 1 2 RFIO_TPM U5
f t
10pF U4 MX25R8035F
CON1 6 1 8 VDD_ADP VBAT
C47 C48 TP17 TP18
5 C49 VC1 RF1 0.4pF 1.2pF VDD 3 SPIF_SIO2 TP TP
9 GND 4 20pF SPIF_CS# 1 WP#/SIO2 7 SPIF_SIO3 1 1
8 GND ID 3 USB_DP R25 0 5 2 SPIF_SIO1 2 CS# NC/SIO3
7 GND D+ 2 USB_DM RFC GND SPIF_SIO0 5 SO/SIO1
6 GND D- 1 ANT1 SPIF_SCLK 6 SI/SIO0 4
n u
C50 C51
GND VBUS VDD_ADP 1.5pF 1.5pF ANT_SWB 4 3 C52 L13 SCLK GND
NPO NPO VC2 RF2 20pF 2.2nH TP19 TP20
USB_B TY PE C53 1 2 RFIO_IQM TP TP
1
TRSW 1 1
10pF
SD1 L20 C55 C56
C54 0 0.6pF 1.2pF
SPI FLASH
o a
PESD5V0L1UL
1uF ACX HI1005-1C
1 2
ADP_IN
c 2
NFC_DET
ADP in reset Optional
3
:
(Option) Slide switch application
TP21
TP
1 NFC_SG 2 Q2
t
HW_RST_N SW1 STS2306
BOOST VDD_ADP
SW-TACT
R26 C57
1
3
VBAT SLIDE_SW
C 1
Value depending on
(Option) VDD_ADP D4 R28 charging current C58 1uF NFC NP 1uF
LED 1K U6 R27 2 Q3
APL3202 20K STS2306 C60
k n
1 5 VDD_ADP 0.1uF TP22
U7 C59 2 STAT ISET R29 TP
1
APW7237 4.7uF L14 VDD_AMP VBAT 3 GND 4 10K 1
E 2
10uH-ZAH-7050 BAT+ VIN
1 5 1 2
LX VIN C61
e e
2 D5 4.7uF
GND R30 C62
Schottky
3 4 BOOST_EN 600K 10uF
Button SW2 SW3 SW4
M :
FB EN SW-TACT SW-TACT SW-TACT
Charger KEY0 KEY 2 KEY 4
t m
(Option for charge current > 400mA) power key Addr: No.2, Innovation Rd. II, Hsinchu Science Park, Hsinchu 30076, Taiwan
R31 TEL: 886-3-5780211
T 3
200K SW5 SW6 SW7 Title
SW-TACT SW-TACT SW-TACT RTL8763BA_QFN68_Speaker_ref design_1V0
KEY1 KEY 3 KEY 5 Size Document Name Rev
l u
C RTL8763BA_QFN68_Speaker_ref design_1V0 1.0
a c
Figure 60. RTL8763BS Reference Circuits
W 1
Re d o 6
- 1
h e 1
T - 1
1 7
2 0
RTL8763B Series
10. Electrical Characteristics

10.1. Absolute Maximum Ratings
Item
Table 20. Absolute Maximum Ratings
Min. Typical
e s Max. Unit
Storage Temperature -40
i l - +105 °C
f o
Power Management Unit Min. Typical Max. Unit
t
VDD_CORE VDDCORE - - 1.32 V
l
Synthesizer control VD12_SYNC - - 1.32 V
a d
RF transceiver control VD12_RTX - - 1.32 V
AVCC @ 1.8V mode - - 2.1 V
i e
Codec
AVCC @ 2.8V mode - - 2.9 V
Headphone driver
AVCC_DRV @ 1.8V mode
AVCC_DRV @ 2.8V mode
n t -
-
-
i
- z 2.1
2.9
V
V
VDDIO
ADC Power
VDD_AUX1
VDD AUX2
d e -
-
o r -
-
3.6
3.6
V
V
i h
BAT IN VBAT - - 4.5 V
f t
ADAPTER IN ADP_IN (DC) - - 7 V
o n a u 1
10.2. Recommended
c
Operating Conditions
: 2
k n tItem
Table 21.
C
Recommended Operating Conditions
1 Min. Typical Max. Unit
e e M E
Operating Temperature
: 2 -40 25 +85 °C
l t
VDD_CORE
u m
Power Management Unit
T
VDDCORE
3
Min.
1.14
Typical
1.1
Max.
1.26
Unit
V
a c
Synthesizer control
WVD12_SYNC
1 1.14 1.2 1.26 V
e o
RF transceiver control VD12_RTX 1.14 1.2 1.26 V
R d
Codec
1 6
AVCC @ 1.8V mode
AVCC @ 2.8V mode
1.7
2.6
1.8
2.7
1.98
2.8
V
V
-
AVCC_DRV @ 1.8V mode 1.85 1.9 2.1 V
e
Headphone driver
1
AVCC_DRV @ 2.8V mode 2.7 2.8 2.9 V
T hVDDIO
1
VDD_AUX1 2.8 - 3.6 V
-
ADC Power VDD AUX2 2.8 - 3.6 V
BAT IN VBAT 2.8 - 4.35 V
ADAPTER IN
1 7ADP_IN (DC) 4.5 - 6.5 V
2 0
RTL8763B Series
10.3. Power Management Unit; Switch Mode Regulator for

Audio Core and Audio Drive Stage
s
Table 22. Power Management Unit; Switch Mode Regulator for Audio Core and Audio Drive Stage
e
Item Min. Typ. Max. Unit
l
Input voltage 2.8 - 5 V
Output voltage 1.8 - 2.8 V
Inductor inductance
Inductor specification, saturation current
-
-
2.2
500
fi -
-
µH
mA
o
Inductor specification, DCR
Input capacitor
-
-
0.1
4.7
l
0.6
-
tΩ
µF
a d
Output capacitor - 4.7 - µF
(*1) +/-20%@500mA
z t i e
10.4. Power Management Unit;
e n
Synthesizer r
Switch Mode iRegulator for
d
Digital Core, RF, and
i h o
f t
Table 23. Power Management Unit; Switch Mode Regulator for Digital Core, RF, and Synthesizer
o n
Input voltage
a u 2.8 -
1
5 V
2
Output voltage - 1.2 - V
c
Inductor inductance
t
Inductor specification, saturation current
-
-
2.2
500
:
-
-
µH
mA
k n
Inductor specification, DCR
E C- 0.1
2 1 0.6 Ω
e e
Input capacitor - 4.7 - µF
t m
Output capacitor
T M -
3 :
4.7 - µF
a l c u
10.5. Power Management Unit; Low W Drop Linear Regulator
1
R e d o Table 24.
6
Power Management Unit; Low Drop Linear Regulator
LDO AUX1
- 1
h e Item
Input voltage
1
Min.
2.8
Typ.
-
Max.
5
Unit
V
T
Output voltage
Output current
- 1 2.8
-
-
150(*1)
3.6
-
V
mA
Quiescent current
1 7 - 30 - µA
2 0
RTL8763B Series
LDO AUX1 LQ
s
Output current - 3(*2) - mA
l e
LDO AUX2
Item Min. Typ.
fi Max.
o
Unit
t
l
a d
Quiescent current - 30 - µA
t i z e
PALDO
Item
e n
Min. Typ.
r i
Max. Unit
d o
i h
Output voltage 2.8 3.3 - V
f t
n u
Quiescent current - 30 - µA
o a
(*1) (*3) For external loading use, the maximum is 100mA.
2 1
c
(*2) For external loading use, the maximum is 3mA
t :
C 1
(*4) Not for external use
e k e E
Unit; BatteryMCharger
n 2
t
10.6. Power
m
Management
T 3 :
a l c u
Item
W
Table 25.
1
Power Management Unit; Battery Charger
Min. Typ. Max. Unit
R e d o
ADP_IN input voltage
6
4.5 5 6.5 V
1
Charge current, ADP_IN >=5V - - 400 mA
-
Charge current, 4.5V<ADP_IN<5V - - 200 mA
e
Trickle charge current 5 - - mA(*1)
h
VBAT in Trickle charge mode
1 1 0.5 - 3.0 V
T
VBAT in constant current mode 3.0 - 4.35(*1) V, max programmable
VBAT in constant voltage mode
7 -
Battery charge full, stop current
-
2mA
4.2
0.1C
4.35(*2)
-
V, max programmable
C(*3)
1
Re-charge threshold - 4.0 - V(*4)
2 0
(*1) Adjustable by UI, the max is defined by Li-Ion battery
(*2) Adjustable by UI, the max is defined by Li-Ion battery
(*3) 1C= Li-Ion battery full capacity
(*4) UI configurable
RTL8763B Series
10.7. Audio Codec DAC (If not specially marked, the test is with
AVcc = 2.8V)
s
Table 26. Audio Codec DAC (If not specially marked, the test is with AVDD= 2.8V)
e
Conditions Min Typ. Max Unit
l
Over-sampling rate ( f ) - - 128 - fs
Resolution
-
-
-40
f
- i 25
24
85
-
o
°C
Bits
Output Sample Rate, Fsample 8,16,32,44.1,48,88.2,96kHz
fin=1kHz
l
8 - 96
t kHz
a d
B/W=20~20kHz AVCC=1.80V - 98 -
i e
Signal to Noise Ratio A-weighted
dBA
(SNR @cap-less mode) THD+N < 0.02%
0dBFS signal
Load=100KΩ
n t
AVCC=2.80V -
i z 102 -
Signal to Noise Ratio

fin=1kHz
d
B/W=20~20kHz
e AVCC=1.80V
o r
- 98 -
i h
A-weighted
dBA
(SNR @single-end mode) THD+N < 0.02%
f t
0dBFS signal AVCC=2.80V - 102 -
n u
Load=100KΩ
o a
AVCC=1.80V - 97 -
2 1
c
24-bit mode dB
:
AVCC=2.80V - 101 -
Dynamic range
k n t AVCC=1.80V -
C 96 -
1
E 2
16-bit mode dB
t e m e AVCC=2.80V
M
- 96 -
:
T 3
Digital Gain -65.625 - 0 dB
a l c u
Digital Gain Resolution
W
- 0.375
1
- dB
e o
Analog Gain @headphone stage -9 0 dB
R d
Analog Gain Step
AVCC=1.80V
-
-
1 6 3
16
-
-
dB
-
16Ω load
e
AVCC=2.80V - 40 -
1
Maximum Output Power mW
h
AVCC=1.80V - 8 -
1
32Ω load
T
AVCC=2.80V - 20 -
Allowed Load
Resistive
7 - - 16 O.C. Ω
1
Capacitive 1500 - - pF
0
THD+N @single-end mode, 100KΩ load - 0.02 -
%
2
2.8V or 1.8V, 0dBFS input 16Ω load - 0.04 -
Signal to Noise Ratio 16Ω load, 0dBFS input relative to
- 96 - dB
(SNR @ earphone load) digital silence

RTL8763B Series
L vs. R, measured at
-10dBFS@1kHz input, single-ended - -95 - dB
output, 2.8V@16ohm
e s
l
Crosstalk between channels
-10dBFS@1kHz input, differential - -98 - dB
i
output, 2.8V@16ohm
f o
t
-10dBFS@1kHz input, cap-less - -54 - dB
output, 2.8V@16ohm
Analog supply voltage (AVCC)

(1) For earphone,
AVCC= 1.80V
a l 1.80 2.8
d 3.0 V
i e
(2) For earphone/speakers,
z t
AVCC= 2.80V
10.8. Audio Codec ADC (If n i

d e o r
not specially marked, the test is with
i h
AVcc= 2.8V)
n f
Table 27.
t
Audio Codec ADC (If not specially marked, the test is with Vcc= 2.8V)
u 1
c o
a -
2
-40 25 85 °C
:
Resolution - 24 Bits
k n t
Input sample rate, Fsample
C 1
8,16,32,44.1,48, 88.2, 96kHz
8 96 kHz
E 2
Note: Better to have 88.2,
e e
96kHz
t m T M :
fin=1kHz
3
l u
B/W=20~20kHz
W 1
Signal to Noise Ratio A-weighted
a c
- 97 - dBA
(SNR @Line-in mode) THD+N < 0.1%
R e d o 800mVRMS input
6
(AVCC=2.8V)
- 1 fin=1kHz
e
B/W=20~20kHz
h
(SNR @Line-in mode)
1 1 A-weighted
THD+N < 0.1%
- 96 - dBA
T -
800mVRMS input
(AVCC=1.8V)
1 7 fin=1kHz
B/W=20~20kHz
(SNR @MIC mode)
2 0 A-weighted
THD+N < 0.5%
8mVRMS input
40dB gain
8kHz,
16kHz
- 70 - dBA
(AVCC=2.8V)

RTL8763B Series
AVCC=1.80V - 95 -
Dynamic range dB
Digital Gain
AVCC=2.80V
-
-
-17.625
e s95 -
30 dB
Digital Gain Resolution - -
i l 0.375 dB
f o
MIC Boost Gain 0/20/30/40dB 0 20 40 dB
t
MIC Input full-scale at maximum 5.65*AVD
Gain=40dB - - mVRMS
gain (differential) D
MIC Input full-scale at minimum
gain (differential)
Gain=0dB
a l -
d
0.8*AVDD - VPP
3dB bandwidth
Microphone mode
-
t i
Input impedance
-
-
z e
20
6
-
10
kHz
KΩ
input impedance
THD+N (microphone input)

e n
Input capacitance -
r i 20 - pF
d o
- - 0.03 - %
@30mVRMS input, 20dB gain
THD+N (line input) @-3dBFS
f i AVCC= 1.8 or 2.8V
t h - 0.02 - %
ADC channels
o n -
a u - 2 - ch
1
2
Line-input full-scale AVCC = 2.8V - 2.2 - VPP
c
Line-input full-scale
t
AVCC = 1.8V - 1.4 -
:
VPP
k n
Input impedance -
E C 10 -
2 1KΩ
t e
Line-input input impedance
m e Input capacitance
M - 20
:
- pF
l u Line-in
W T - -98
1 3 - dB
a c
Crosstalk between channels
MIC-IN - -98 - dB
Re d o (1) For BT earphone,
6
1
AVCC=1.80V
Analog supply voltage (AVCC) 1.80 2.8 3.0 V
-
(2) For BT earphone/ speakers,
e
AVCC=2.80V
h
MIC bias
AVCC=2.80V
1 1
AVDD*0.75 - AVDD*0.9
V
T AVCC=1.8V
-
1.5V - -
1 7
2 0
RTL8763B Series
11. RF Characteristics
11.1. Transmitter BT Classic Basic Data Rate (BDR)
Parameter
Table 28.
Min. Typ. Max.
e s
Transmitter BT Classic Basic Data Rate (BDR)
Bluetooth Specification
Transmitter frequency (MHz)
Transmitter Power (dBm)
2402
-
-
10
2480
-
i l 2402 ~ 2480, 79CH
-
Transmitter power control step (dB)
20dB bandwidth (kHz)
-
-
4
900
f -
-
o
2dB ≤ step size ≤ 8 dB
t
1000kHz
l
Initial carrier frequency offset (*1) - ±10kHz - ±75kHz
a d
DH1 - ±10kHz - ±25kHz
i e
Frequency drift (kHz) DH3 - ±10kHz - ±40kHz
DH5 - ±10kHz - ±40kHz
Frequency deviation ∆f1avg (kHz)
Frequency deviation ∆f2max (kHz)
-
n
115 t 160
-
-
-
i z 140~175kHz
≥ 115kHz
f1avg/f2avg
N+2
d e-
-
0.88
-
o r
-
-20
≥ 0.8
≤ -20dBm
i h
Adjacent channel TX N-2 - - -20 ≤ -20dBm
f t
power (dBm) N+3 - - -40 ≤ -40dBm
n u
N-3 - - -40 ≤ -40dBm
o a
(*1) Initial carrier offset should be calibrated in MP process in customer side.
2 1
c t :
C 1
Table 29. Harmonic
nd
e k
Parameter
2 harmonic typical (*3)
2402MHz
e -
n 2440MHz
-50
E
2480MHz
-
2
Unit
dBm
t
3rd harmonic typical (*3)
m
- -50
T M -
3 : dBm
l u W 1
(*3) A π-type matching or a Low Pass Filter (LPF) or a Band Pass Filter (BPF) is needed to suppress the
a c
2nd and 3rd harmonic energy, follow REALTEK design guide.
Re d o 6
11.2. Transmitter BT Classic Enhanced Data Rate (EDR)
- 1
h e 1
Table 30. Transmitter BT Classic Enhanced Data Rate (EDR)
1
Parameter Min. Typ. Max. Bluetooth Specification
T
Transmitter frequency (MHz)
Relative TX power (dB)
2402
-
-
-1
2480
-
-
2402 ~ 2480, 79CH
-4 ~ +1
EDR carrier frequency stability (kHz) - 10 -
1 7 -75≤ωi≤75
-75≤(ωi+ωo) ≤75
0
2M EDR RMS DEVM - - 0.2 ≤ 0.2
2
modulation accuracy Peak DEVM - - 0.35 ≤ 0.35
EDR TX=7.5 dBm 99% DEVM - 100% 99%DEVM ≤ 0.3
3M EDR RMS DEVM - - 0.13 ≤ 0.13
modulation accuracy Peak DEVM - - 0.25 ≤ 0.25

RTL8763B Series
EDR TX=7.5 dBm 99% DEVM - 100% - ≥ 99%
EDR differential phase encoding - 100% - ≥ 99%
s
PTX-26dB(f) ≦ PTXref – 26dB for |M-N|
|M-N| = 1 - - -26 = 1 (M: Tx Channel, N: Adjacent
2M EDR in-band
spurious emission
|M-N| = 2 - - -20
l e Channel)
PTX(f) ≦ -20dBm for |M-N| = 2 (M:
i
(dBm) Tx Channel, N: Adjacent Channel)
PTX(f) ≦ -40dBm for |M-N| ≧ 3 (M:
f o
|M-N| = 3 - - -40
Tx Channel, N: Adjacent Channel)
|M-N| = 1 - -
l
-26
t
PTX-26dB(f) ≦ PTXref – 26dB for |M-N|
= 1 (M: Tx Channel, N: Adjacent
a d
3M EDR in-band Channel)
spurious emission PTX(f) ≦ -20dBm for |M-N| = 2 (M:
i e
|M-N| = 2 - - -20
(dBm) Tx Channel, N: Adjacent Channel)
|M-N| = 3 -
n t - -40
i z
PTX(f) ≦ -40dBm for |M-N| ≧ 3 (M:
Tx Channel, N: Adjacent Channel)
d e o r
11.3. Transmitter BTi h
n f u t
Classic Bluetooth Low Energy (BLE IQM)
1
Table 31. Transmitter BT Classic Bluetooth Low Energy (BLE IQM)
c oParameter
a Min. Typ.
2
Max. Bluetooth Specification
:
Transmitter frequency (MHz) 2402 - 2480 2402 ~ 2480, 40CH
k
In-band
n t
Transmitter Power (dBm)
|M-N| = 2
C
-
-
10
1
-
-
-20
-
PTX ≤ -20 dBm for (fTX ± 2 MHz)
e
emission
(dBm)
e |M-N| ≥ 3
M E -
: 2 - -30
PTX ≤ -30 dBm for (fTX ± [3 + n]
MHz]); where n=0,1,2…
l t
Carrier
u m Fn
T
(*1)
-
3
±10 - f TX – 150kHz ≤ fn ≤ fTX + 150 kHz
W 1
frequency |f0 – fn|, n=2,3,4…k - ±15 - |f0 – fn| ≤ 50 kHz where n=2,3,4…k
a c
offset (kHz) |f1 – f0| ≤ 20 kHz and |fn – fn-5| ≤ 20
|f1 – f0| and |fn – fn-5| - ±15 -
e o
and drift(kHz) kHz
R d
Modulation characteristics ∆f1avg (kHz)
Frequency deviation 99.9% of ∆f2max ≥
1 6 -
-
250
100%
-
-
225~275kHz
≥ 99.9%
-
185kHz
h e f1avg/f2avg
1
- 0.88 - ≥ 0.8
T - 1
(*1) Initial carrier offset should be calibrated in the MP process at the customer side.
1 7
2 0
RTL8763B Series
11.4. Receiver BT Classic Basic Data Rate (BDR)

Table 32. Receiver BT Classic Basic Data Rate (BDR)
Sensitivity, DH1 (dBm)
Sensitivity, DH3/DH5 (dBm)
-94.5
-94.5
-
-
-
-
e s ≤ -70dBm, BER ≤ 0.1%
≤ -70dBm, BER ≤ 0.1%
≦
Co-channel
Adjacent 1MHz
-
-
10
-13
-
-
i l C/Ico-channel (dB)
C/I1MHz
11dB
≦ 0dB
≦ -30dB
f o
C/I carrier over Adjacent 2MHz - -43 - C/I2MHz
≦ -40dB
t
Interference Adjacent ≥ 3MHz - -45 - C/I3MHz
≦ -9dB
l
(dB)
Image interference - -22 - C/IImage
≦ -20dB
a d
Adjacent (1MHz) interference to
- -29 - C/IImage±1MHz
i e
in-band mirror frequency
30MHz ~ 2000MHz -10 - - -10
Blocking (dBm)
2000MHz ~2400MHz
2500MHz ~ 3000MHz
n t -27
-27
-
-
-
i
- z -27
-27
3000MHz ~ 12.75GHz
d
BER @ f1 = 2407MHz & f2 =
e -10
0
-
o r - -10
≦0.1
i h
2412MHz (%)
f t
Max Intermodulation Level
@ f1 = 2407MHz & f2 = 2412MHz -30.0 ≥ -39
o n (dBm)
BER @ f1 = 2397MHz & f2 =
a u ≦0.1 1
2
0
c
2392MHz (%)
2397MHz & f2 = 2392MHz (dBm)

t
Max Intermodulation Level @ f1 =
-30.0
C
≥ -39
1 :
e k BER @ f1 = 2446MHz & f2 =
e
2451MHz (%)
n 0
E ≦0.1
2
t
Inter-modulation
m
2446MHz & f2 = 2451MHz (dBm)
T M-30
3
≥ -39
:
a l(*1) (*2)
u
BER @ f1 = 2436MHz & f2 =
c
2431MHz (%)
W 0
1 ≦ 0.1
Re d o
2436MHz & f2 = 2431MHz (dBm)
-30
6
≥ -39
BER @ f1 = 2485MHz & f2 =
2490MHz (%)
0
-1 ≦0.1
h e Max Intermodulation Level @ f1 =

2485MHz & f2 = 2490MHz (dBm)
-30
1 ≥ -39
T
BER @ f1 = 2475MHz & f2 =
2470MHz (%)
- 1 0 ≦0.1
7
-30 ≥ -39
1
2475MHz & f2 = 2470MHz (dBm)
Maximum input (dBm) ≦0.1% @ -20dBm
0
0 BER
2
RTL8763B Series
11.5. Receiver BT Classic Enhanced Data Rate (EDR)

Table 33. Receiver BT Classic Enhanced Data Rate (EDR)
Sensitivity, 2-DH5 (dBm)
Sensitivity, 3-DH5 (dBm)
-94
-87.5
-
-
-
-
e s
≤ -70dBm, BER ≤ 0.01%
≤ -70dBm, BER ≤ 0.01%
EDR BER Floor performance
Co-channel
-
-
0
10
-
-
i l BER ≤ 0.001%
C/Ico-channel (dB) 13dB ≦
≦ 0dB
f o
Adjacent 1MHz - -12 - C/I1MHz
≦ -30dB
t
EDR-2M Adjacent 2MHz - -42 - C/I2MHz
≦ -40dB
l
C/I carrier over Adjacent ≥ 3MHz - -47 - C/I3MHz
Interference
≦ -7dB
a d
(dB)
i e ≦ -20dB
Adjacent (1MHz)
interference to in-band - -32 - C/IImage±1MHz
mirror frequency
Co-channel
n
- t 17 -
i z C/Ico-channel (dB) ≦ 21dB
≦ 5dB
EDR-3M
Adjacent 1MHz
Adjacent 2MHz
d e -
-
-5
-36
o r -
-
C/I1MHz
C/I2MHz ≦ -25dB
≦ -33dB
i h
C/I carrier over Adjacent ≥ 3MHz - -44 - C/I3MHz
≦ 0dB
f t
Interference
(dB)
n u ≦ -13dB
Adjacent (1MHz)
o
interference to in-band
mirror frequency
-
a
-27 - C/IImage±1MHz
2 1
c
Maximum input (dBm)
t
0 BER ≦0.1% @ -20dBm
:
k n E C 2 1
t e m e M :
l u W T 1 3
e a o c
R d 1 6
e 1 -
T h 1
7 -
0 1
2
RTL8763B Series
11.6. Receiver BT Classic Bluetooth Low Energy (BLE) IQM

Table 34. Receiver BT Classic Bluetooth Low Energy (BLE) IQM
Sensitivity LE 1M
Co-channel
-97
- 6
- -
-
e s
≤ -70dBm, PER ≤ 30.8%
C/Ico-channel (dB) 21dB ≦
≦ 15dB
Adjacent 1MHz
Adjacent 2MHz
-
-
-3
-40
i l
-
-
C/I1MHz
C/I2MHz ≦ -17dB
≦ -27dB
f o
C/I carrier over
Interference (dB) Adjacent ≥ 3MHz - -50 - C/I3MHz
≦ -9dB
Image interference
Adjacent (1MHz) interference to in-band
-
l
-
-29
-30
-
- t
C/IImage
C/IImage±1MHz ≦ -15dB
a d
mirror frequency
i e
30MHz ~ 2000MHz -30 - - -30
2000MHz ~2400MHz -35 - - -35
t z
Blocking (dBm)
2500MHz ~ 3000MHz -35 - - -35
3000MHz ~ 12.75GHz
e n
PER @ f1 = 2407MHz & f2 = 2412MHz
-30
0
r
-
i-
PER
-30
≦30.8%
d o
(%)
i h
-30 ≥ -50
2407MHz & f2 = 2412MHz (dBm)
n f
PER @ f1 = 2397MHz & f2 = 2392MHz
u t 0 PER ≦30.8%
1
(%)
o a
2
-30 ≥ -50
c
2397MHz & f2 = 2392MHz (dBm)
PER @ f1 = 2445MHz & f2 = 2450MHz
(%)
t
0
C
PER ≦30.8%
1 :
e k
Inter-modulation
e n
2445MHz & f2 = 2450MHz (dBm)
-30
E ≥ -50
2
t
(*1) (*2)
m
PER @ f1 = 2435MHz & f2 = 2430MHz
(%)
T M
0
3
PER
:
≦30.8%
a l c u
2437MHz & f2 = 2434MHz (dBm)
W -30
1≦ ≥ -50
e o
PER @ f1 = 2485MHz & f2 = 2490MHz
6
0 PER 30.8%
R d
(%)
2485MHz & f2 = 2490MHz (dBm)
-30
- 1 ≥ -50
h e PER @ f1 = 2475MHz & f2 = 2470MHz

(%)
0
1 PER ≦30.8%
T
2475MHz & f2 = 2470MHz (dBm)
- 1
-30 ≥ -50
≦30.8% @ -10dBm
7
Maximum input (dBm) 0 PER
(*1) fchannel = 2f1-f2, |f2-f1| = n*1 MHz, n=3,4 or 5
0 1
(*2) The value of n (for which the TC is performed) shall be declared by the manufacturer in the IXIT
2
table (See PICS Proforma for Bluetooth low energy RF PHY).

RTL8763B Series
11.7. Receiver BT Classic Bluetooth Low Energy (BLE) 2M

IQM
s
Table 35. Receiver BT Classic Bluetooth Low Energy (BLE) 2M IQM
e
l
Sensitivity LE 2M -94 - - ≤ -70dBm, PER ≤ 30.8%
Co-channel - 6 - C/Ico-channel (dB) 21dB ≦
Adjacent 2MHz
Adjacent 4MHz
-
-
-5
-47
f i -
-
C/I2MHz
C/I4MHz
o
≦ 15dB
≦ -17dB
t ≦ -27dB
C/I carrier over
Adjacent ≥ 6MHz - -51 - C/I6MHz
l
Interference (dB)
Image interference - -30 - C/IImage ≦ -9dB
i a
- -27 -
e d
C/IImage±2MHz ≦ -15dB
n t i z
11.8.
e
Receiver BT Classic Bluetooth Low Energy (BLE) Long
Range 500K IQM
d o r
Table 36.
f i t h
Receiver BT Classic Bluetooth Low Energy (BLE) Long Range 500K IQM
o n
Sensitivity LE Long Range -500K
a u
-100.5 - - ≤ -75dBm, PER ≤ 30.8%
≦
1
2
Co-channel - 1.9 - C/Ico-channel (dB) 17dB
≦ 11dB
c Adjacent 1MHz
t
- -8 - C/I1MHz
≦ -21dB
:
C 1
Adjacent 2MHz - -43 - C/I2MHz
≦ -31dB
k n
C/I carrier over
E 2
Interference (dB) Adjacent ≥ 3MHz - -54 - C/I3MHz
≦ -13dB
t e m e
Image interference -
M
-33 - C/IImage
:≦ -19dB
T 3
- -33 - C/IImage±1MHz
l u
a c W 1
R e
11.9. Receiver o
6
BT Classic Bluetooth Low Energy (BLE) Long
d IQM
Range 125K
- 1
e
Table 37.
h 1
Receiver BT Classic Bluetooth Low Energy (BLE) Long Range 125K IQM
1
T -
Sensitivity LE Long Range -125K
Co-channel
-106.5
≦
-
-
1.9
-
-
≤ -82dBm, PER ≤ 30.8%
C/Ico-channel (dB) 12dB
1 7
Adjacent 1MHz
Adjacent 2MHz ≦
≦ -
-
-16
-50
-
-
C/I1MHz
C/I2MHz
6dB
-26dB
0 ≦
C/I carrier over
Adjacent ≥ 3MHz - -60 - C/I3MHz -36dB
2
Interference (dB)
Image interference ≦ - -34 - C/IImage -18dB
≦ - -38 - C/IImage±1MHz -24dB

RTL8763B Series
11.10. Analog ADC Input

Table 38. Analog ADC Input
Parameter Condition Min Typical Max Unit
Input impedance
Bypass mode(*1)
Normal mode(*2)
-
-
3M
100K
e s -
-
Ω
Ω
Input voltage range

Bypass mode
Normal mode
0
0
-
-
i l 1
3
V
V
f o
Number of ADC ch. P0_0 - P0_7 (*3) - - 8 ch
t
Offset With FT - TBD - mV
Gain error With FT - TBD - %
Internal ref. voltage
Resolution
-
-
-
-
a l 0.5
12
d
-
-
-
bit
ENOB
Test condition: VDDIO=3.3V

-
t i
- 10.3
z e - bit
e n
(*1) Normal mode: with internal resistor divider
r i
d o
(*2) Bypass mode: without internal resistor divider
i
(*3) The ADC input counts is varied depending on part number
f t h
o n
11.11. ESD Protection
a u 1
c : 2
The table below shows the maximum ESD capability of RTL8763B.
k n t C 1
The ESD protection scheme should be applied during manufacture procedure to avoid unconditional ESD
damage.
e e M E : 2
t m
Table 39. ESD Protection
l
Parameter
Human Body Mode
u W T Condition
1 3
All pins, test method: JESD22
Min.
-
Typ.
±2KV (all pins)
Max.
-
e a o c ±200V (all pins
6
Machine Mode All pins, test method: JESD22 - except XI, XO is -
R d
rated at 150V)
Charged Device Model
- 1
All pins, test method: JESD22 - ±400V (all pins) -
e
Latch up All pins, test method: JESD22 ±200mA (all pins) -
h 1 1
T -
1 7
2 0
RTL8763B Series
11.12. Power Consumption

VBAT=3.7V, One Headset Test Without Speaker Loading; RF TX= +2dBm, Test With Handset
s
APPLE i-Phone7
e
Table 40. VBAT=3.7V, RTL8763BFR One Headset Test Without Speaker Loading; RF TX= +2dBm
l
Test Condition Min. Typ. Max. Unit
Power off - TBD - µA
DLPS mode
Standby mode
-
-
TBD
TBD
f
-
-i µA
µA
o
Page mode
Page + Inquiry mode
-
-
TBD
TBD
l
-
-
µA
µA
t
a d
A2DP AAC - TBD - mA
i e
A2DP SBC
- TBD - mA
High quality, bit pool=53
A2DP SBC
Mid quality, bit pool=35
eSCO
nt -
-
TBD
TBD
i z -
-
mA
mA
d e o r
f i
With Handset APPLE i-Phone7 Playing the Master Role, Master Side
t h
VBAT=3.7V, RTL8763BFR RWS Headset Test Without Speaker Loading; RF TX= +6dBm, Test
Table 41.
n u
VBAT=3.7V, RWS Headset Test Without Speaker Loading; RF TX= +6dBm, Test With Handset
o a
APPLE i-Phone7 Playing the Master Role, Master Side
1
c
Test Condition Min. Typ. Max. Unit
: 2
t
Power off - TBD - µA
k
DLPS mode
Standby mode
n -
TBD
TBD
E
-
C µA
µA
2 1
t e Page mode
m e - TBD
M
- µA
:
T 3
Page + Inquiry mode - TBD - µA
a lA2DP AAC
c u
Master headset
Slave headset
TBD
TBD
W
mA
mA
1
e o
Master headset TBD mA
6
eSCO
R d
Slave headset TBD mA
-1
e 1
h 1
APPLE i-Phone7 Playing the Master Role, Slave Side
T
Table 42.
-
Android Phone/Android7.0 Playing the Master Role, Slave Side
Test Condition
Power off
Min.
-
Typ.
TBD
1 7 Max.
-
Unit
µA
DLPS mode
Standby mode
Page mode
Page + Inquiry mode
-
-
-
2 0 22
145
175
310
-
-
-
µA
µA
µA
µA
A2DP SBC Master headset 11 mA

RTL8763B Series
High quality
Slave headset 6.8 mA
(bit pool=53)
Master headset 9.3 mA
eSCO
Slave headset 8.3 mA
e s
i l
f t o
a l d
t i z e
e n r i
i d h o
n f u t
o a 2 1
c t :
k n E C 2 1
t e m e M :
l u W T 1 3
e a o c
R d 1 6
e 1 -
T h 1
7-
0 1
2
RTL8763B Series
12. Mechanical Dimensions

12.1. Package Dimensions QFN40
e s
i l
f t o
a l d
t i z e
e n r i
i d h o
n f u t
o a 2 1
c t :
k n E C 2 1
t e m e M :
l u W T 1 3
e a o c
R d 1 6
e 1 -
T h 1
7-
0 1
2
RTL8763B Series
12.2. QFN40 Layout Land Pattern Stencil Open
e s
i l
f t o
a l d
t i z e
e n r i
i d h o
n f u t
12.3. SuggestedoStencil Open foraSMT Soldering on EP Pad 2 1
c Pad Under thet Chip) :
(Exposed
k n E C 2 1
t e m e M :
l u W T 1 3
e a o c
R d 1 6
e 1 -
T h 1
7 -
0 1
2
RTL8763B Series
12.4. Package Dimension QFN48 6x6mm2
e s
i l
f t o
a l d
t i z e
e n r i
i d h o
n f u t
o a2 1
12.5. QFN48c :
k n t
Layout Land Pattern Stencil Open
C 1
E 2
0.2mm 0.2mm
e e
0.4mm
t m T M 3 :
a l c u W 1 0.6mm
R e d o 6
1
0.4mm
4.0mm
e 1 -
T h 1
7 -
0 1
2
RTL8763B Series
12.6. Suggested Stencil Open for SMT Soldering on EP Pad

(Exposed Pad Under the Chip)
s
0.2mm 0.4mm 0.2mm
l e
f
0.3mm i o
0.4mm 9.3mm
l t
i a e d
n t i z
d e o r
f i t h
o n a u 1
c : 2
k n t C 1
e e M E : 2
l t u m T 3
a c W 1
Re d o 6
-1
h e 1
T - 1
1 7
2 0
RTL8763B Series
12.7. Package Dimension QFN68 8x8mm2
e s
i l
f t o
a l d
t i z e
e n r i
i d h o
n f u t
o a 2 1
c t :
k n E C 2 1
t e m e M :
l u W T 1 3
e a o c
R d 1 6
e 1 -
T h 1
7-
0 1
2
RTL8763B Series
12.8. QFN68 Layout Land Pattern Stencil Open
e s
i l
f t o
a l d
t i z e
e n r i
i d h o
n f u t
o
12.9. Suggested Stencil
a
Open for SMT Soldering on EP Pad
2 1
c
(Exposed Pad Under the Chip)
t :
k n E C 2 1
t e m e M :
l u W T 1 3
e a o c
R d 1 6
e 1 -
T h 1
7 -
0 1
2
RTL8763B Series
12.10. PCB Design Layout Trace Routing for 2-Layer PCB

For cost consideration, 2-layer PCB is often used, however, cost and performance tradeoff is always an
issue. For a robust design in a 2-layer PCB, a layout route pattern is suggested in the ‘RTL8763 layout
guide’. A 2-layer PCB is simple with the RTL8763BM/BF/BFR audio solution
e s
l
Advantages of the RTL8763Bx series:
i
• Simple and optimized reference BOM list
• Availability of small component pattern
f t o
12.11. Reflow Profile
a l d
t i z e
e n r i
i d h o
n f u t
o a 2 1
c t :
k n E C 2 1
t e m e M :
l u W T 1 3
e a o c
R d 1 6
e 1 -
T h 1
7 -
0 1
2
RTL8763B Series
12.12. Tape and Reel Information

12.12.1. Tape Information
e s
i l
f t o
a l d
Package Code Number of Pins
t i
Body Size (mm2)
P (mm)
z e
Package Pitch: Hole Pitch:
P0 (mm)
QFN40
QFN48
40
48
e n 5X5
6X6
r
8
12
i 4
4
d o
QFN68 68 8X8 12 4
12.12.2. Reel Information

f i t h
o n a u 1
c : 2
k n t C 1
e e M E : 2
l t u m T 3
a c W 1
Re d o 6
- 1
h e 1
T - 1
7
Package Code Number of Pins Reel Diameter Reel Width
1
QFN40 40 330mm 12mm
0
QFN48 48 330mm 12mm
QFN68 68 330mm 12mm
2
RTL8763B Series
12.12.3. IC Tray Information (QFN40)
e s
i l
f t o
a l d
t i z e
e n r i
i d h o
12.12.4.
n f
IC Tray Information (QFN48)
u t
o a 2 1
c t :
k n E C 2 1
t e m e M :
l u W T 1 3
e a o c
R d 1 6
e 1 -
T h 1
7-
0 1
2
RTL8763B Series
12.12.5. IC Tray Information (QFN68)
e s
i l
f t o
a l d
t i z e
e n r i
i d h o
n f u t
o a 2 1
c t :
C 1
12.12.6. Storage Conditions
e k e
MIN.
n E
TYP. MAX.
2
M :
Storage Temperature - - 30°C
l t
Storage Humidity
u m -
T
-
3
60%
a c W 1
Re d o 6
- 1
h e 1
T - 1
1 7
2 0
RTL8763B Series
13. Ordering Information

Table 43. Ordering Information
Part Number Package Status
RTL8763BM
RTL8763BF
QFN-40, 5mm x 5mm Outline; ‘Green’ Package
e s MP
MP
RTL8763BFR
RTL8763BS
i l MP
MP
f o
RTL8763BA QFN-68, 8mm x 8mm Outline; ‘Green’ Package MP
t
Note: See page 11 for package identification information.
a l d
t i z e
e n r i
i d h o
n f u t
o a 2 1
c t :
k n E C 2 1
t e m e M :
l u W T 1 3
e a o c
R d 1 6
e 1 -
T h 1
7 -
Realtek Semiconductor Corp.
0 1
Headquarters
No. 2, Innovation Road II
Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
2
RTL8763B Series
www.realtek.com
e s
i l
f t o
a l d
t i z e
e n r i
i d h o
n f u t
o a 2 1
c t :
k n E C 2 1
t e m e M :
l u W T 1 3
e a o c
R d 1 6
e 1 -
T h 1
7-
0 1
2

RTL8763B Realtek

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Bluetooth 5 Dual Mode SOC ii Track ID: JATR-8275-15 Rev. 0.9

Bluetooth 5 Dual Mode SOC iv Track ID: JATR-8275-15 Rev. 0.9

a lPackage: 5x5mm2 QFN40 (RTL8763BM,

Proprietary services for data

a u Supports PTA (Packet Traffic Arbiter) when

component required (when TX power is

Bluetooth 5 Dual Mode SOC 3 Track ID: JATR-8275-15 Rev. 0.9

Supports ambient thermal detection to detect

Bluetooth 5 Dual Mode SOC 7 Track ID: JATR-8275-15 Rev. 0.9

Table 1. Power-On Sequence-Battery Mode

5.2. Power On Sequence-Adapter Mode f t o

7.2. PIN OUT (TOP View) RTL8763BM QFN40

7.3. PIN OUT (TOP View) RTL8763BF/BFR QFN40

7.4. PIN OUT (TOP View) RTL8763BS QFN48

7.5. PIN OUT (TOP View) RTL8763BA QFN68

1 1 Programmable GPIO. Can be

Bluetooth 5 Dual Mode SOC 16 Track ID: JATR-8275-15 Rev. 0.9

8.4. Audio Codec

f i t h MIC2 input positive pad. Used as 2nd

e a o c Left channel speaker output negative

AH: Analog and digital hybrid programmable

Bluetooth 5 Dual Mode SOC 18 Track ID: JATR-8275-15 Rev. 0.9

8.5. Power Management

fi Battery input when battery only

PO: Power Output

Bluetooth 5 Dual Mode SOC 19 Track ID: JATR-8275-15 Rev. 0.9

8.6. SPI FLASH Memory Interface

o n a u connect to SIO1 pin of external FLASH

I_PU: Input with internal pull high inside

Bluetooth 5 Dual Mode SOC 20 Track ID: JATR-8275-15 Rev. 0.9

9.1.4. RF IQM and TPM

9.2. Crystal Oscillator

design specification and QVL.

Insulation Resistance (MOhm)

Bluetooth 5 Dual Mode SOC 23 Track ID: JATR-8275-15 Rev. 0.9

9.3. Crystal Oscillator 32.768kHz

Bluetooth 5 Dual Mode SOC 25 Track ID: JATR-8275-15 Rev. 0.9

9.5. Audio CODEC: DAC

9.5.2. Cap-Less Output

Bluetooth 5 Dual Mode SOC 28 Track ID: JATR-8275-15 Rev. 0.9

9.5.3. Differential Output

unit will be doubled.

Bluetooth 5 Dual Mode SOC 29 Track ID: JATR-8275-15 Rev. 0.9

9.6. Audio CODEC: ADC

Bluetooth 5 Dual Mode SOC 30 Track ID: JATR-8275-15 Rev. 0.9

E 1.25M, 2.5M, 5M`

9.8. PCM I2S

Figure 31. I2S Connection; RTL8763B in Slave Mode

Bluetooth 5 Dual Mode SOC 33 Track ID: JATR-8275-15 Rev. 0.9

Bluetooth 5 Dual Mode SOC 35 Track ID: JATR-8275-15 Rev. 0.9

th_STR tlow 2 0 th_DAT thigh tset_STOP

Bluetooth 5 Dual Mode SOC 36 Track ID: JATR-8275-15 Rev. 0.9

9.13. USB Interface

• 2.5mA average if the USB bus is suspended f

Bluetooth 5 Dual Mode SOC 38 Track ID: JATR-8275-15 Rev. 0.9

Bluetooth 5 Dual Mode SOC 40 Track ID: JATR-8275-15 Rev. 0.9

is the same, e.g. (LoadCount + 1) * timer_N_clk clock period.

PWM2, while PWM2_N will be the reverse of PWM2.

T Gen Demo -1 Gen Demo

Bluetooth 5 Dual Mode SOC 42 Track ID: JATR-8275-15 Rev. 0.9

Bluetooth 5 Dual Mode SOC 45 Track ID: JATR-8275-15 Rev. 0.9

(1) fchannel = 2f1-f2, |f2-f1| = n1 MHz, n=3,4 or 5