Complete PnR flow from RTL to GDSII

What are pre-synthesis sanity checks.

Pre-Synthesis checks:
1. All RTLs must available in hierarchical mode
 Modules, subsystems, components, std. cells, special cells by RTL team uses & so on
2. All required libraries for each corner
 Mostly synthesis is done for setup (worst case PVT) corner, unless it required performance target in other
corners by Dynamic Voltage Frequency Scaling (DVFS) i.e., changing voltage directly changes frequency
(V↑ ∝ F↑ ∝ D↓).
3. Use NLDM libraries for net delay model
 Synthesis uses NLDM (Non-Linear Delay Model) which is voltage-based libraries & have less parameters
(RC, i/p trans, o/p load & fanout). Less accurate, sufficient to do synthesis as it uses WLM & no physical
information.
 PnR uses CCS & LVF for implementation because of its accuracy.
 In CCS (Composite Current Source), concurrent current source helps to create more accurate model for
delay & transition of standard cells.
 CCS-LVF (Liberty Variation Format) used for advanced nodes below 10nm, which has variation information
in .lib library itself.
4. Use correct libraries for Macros & Std. cells
5. Use correct constraints for timing
 presents all clock definitions,
 all flops in design constraints viz shouldn’t be unconstraint end points, un-clock registers, no registers
driven by multiple clocks, no missing I/O port delays, undriven i/p’s, undefined load o/p, missing
slew/load constraints, timing loops, timing groups & clock groups.
6. Use UPF available for low power designs
 check_mv_design – making sure UPF file is matching with design & all the design is correctly defined in
UPF viz voltages, voltages domains, power scenarios, power domains, logic ports should define correctly,
For initial synthesis check:
 At block level, mostly receives floor plan information from top level
 Check all ports defined in LEF file
 Initial check for FP, should have sufficient area on FP starting with low enough utilization
 There are no overlapping ports, ports are in correct metal layers, ports are not close to each other, should
be meeting design rules (DRC).
What are post-synthesis sanity checks and challenges faced in synthesis
1. log file Checks 1. Compile related errors & warnings in design;
2. Linking issue
3. check for duplicate design/module, e.g if adder module is defined in two
different file;
4. No black boxes should report in log file for missing RTL design/sub-module;
2. check_design 1) Duplicate designs;
2) No Multi-Driven Nets  Uncertain/unpredictable signals
3) No floating i/p’s or nets  Floating poly is never allowed & issue with
functionality  DRC violation
4) No floating cells;
5) No floating ports;
6) No I/P or O/P connected to PGs  Short ckt i.e, direct path b/w VDD to VSS
 huge power drain; always connect i/p’s to TIE cells for constant i/p’s
7) No Black boxes or empty Modules
8) No Combinational Feedback Loops  Unstable signal due to switching
continuously  setup timing issue
9) No Assign Statements  causes high net delay; mess up timing constraints;
can’t estimate area & affect functionality.
3. check_timing 1. Un-constrained endpoints: Warns about unconstrained timing endpoints.
checks the timing This warning identifies the reason of the unconstrained endpoints
attributes placed on the 2. un-clocked register(UCR): Warns if no clock reaches a register clock pin. In
current design and issues this case, no setup or hold checks are performed on data pins related to
that clock pin, and the path starting at the clock pin is not relative to a
warning messages as
clock.
needed. The messages 3. multiple clocks: multiple clocks reach a register clock pin  apply
provide information that set_case_analysis to avoid propagating multiple clks simultaneously.
identifies and corrects 4. Missing I/O port delays  IO delay modelling  Use
potential errors. The set_input_delay/set_output_delay
warnings do not 5. Missing slew constraints  IO delay modelling  Use
necessarily indicate set_input_transition/set_load/set_driving_cell
6. Combinational loops switching continuously, so NO stable data  leads
design problems.
setup timing issue; Warns of combinational feedback loops. If the
feedback loop is not broken by the set_disable_timing command, it is
This command automatically broken by disabling one or more timing arcs.
performs the default 7. I/O delay not defined
checks when no options 8. undefined load constraints
are specified: 9. Missing driving cell (not defined)
o gated_clock 10. Clock groups – relative clks defined in diff. clk groups
11. gated_clock  Warns if the gated clock doesn't reach any register CP pin.
o generated_clock
The check only performs for ICG cells.
o loops
12. generated_clock: Checks the generated clock network. Five types of
o no_clock
issues are reported:
o no_input_delay
 The definition point of the generated clock has no path to the source
o
point.
unconstrained_endpoint
 The generated clocks form a loop.
s
 The specified edge mismatch
 The generated clock is unexpanded
 The generated clock without clock period.
4. check_qor for PPA - report_area; report_timing; report_power – gives over all area, timing &
goals power of design respectively.
- Report_qor gives each of the above & WNS/TNS/NFP timing for each clock
 domain of design.
- In PT, can use cmd “report_constraint -all_violators” to see all violators in
design.
5. check_mv_design for - ports not connected to voltage domain;
consistency UPF w.r.t - hierarchy not correctly define in voltage domain;
design & its issues - incorrect domain definition;
- should define voltage domain correctly & matches design viz., ISO, LS, Ports,
power scenarios;
6. Area can high Due to tight constraints tools uses high drive cells, etc.
Power high Clock gating not sufficient  use physical aware clock gating
High LOL (Level of logic) Use multibit flops to save power
Path group for certain design violation
No Vts used.
7. Timing challenges By default, synthesis uses unique type Vt cells say HVT/SVT
We can allow tool to use LVT/ULT cells by enabling other cells apps.
8. Path grouping More effective in synthesis than PnR.
9. Constraint quality Check for false path missing for edges not aligned by few psec.
Check for MCP missing.
10.Tighten the Tighten the constraints by increasing uncertainty if path fails by ~200ps.
constraints Tool can try diff. logic optimization for better timing (only happen in synthesis)
11. Data path Data path optimization in DC by changing enabling respective app.
optimization
12. Increase clock Increase clock gating coverage by reducing fanout limits to drive enough cells.
gating coverage More type of ICGs to include.
Builds virtual clock & checks for power issues, sufficient & enough coverage of
ICGs.
Fanout limit: 10-30; Tighter fanout breaks all fanout into smaller & more
branches.
Transition limit: 25% data path of clock period;
10% clk path of clk prd.
Tighter trans: Uses lot higher drive cells
Buffer insertion
Power & area are more

What are the signoff checks after routing or different checks done in physical verification
I. Logical 1. LEC(Logical Equivalence Checks)
checks – Functional check b/w
RTL Vs Netlist
Ref. Netlist Vs Golden Netlist
1. STA/Timing Closure
II. Physical 2. LVS (Layout vs Schematic)
checks - Compare Layout & Schematic by spice
- Compare no. of devices & its type; No. of nets
- Shorts, Opens, missing component
- component mismatches, parameter mismatch
1. DRC (Design Rule Check)
- Checks for min. metal width, pitch & spacing required for diff layers
w.r.t diff manufacturing process
- Typical rules are Interior, Exterior, Enclosure & Extension
- Density rules for CMP (Chemical Mechanical Polishing)
2. ERC (Electrical Rule Check) – Calibre tool
- Well & subtract area for proper contact & spacing
- Unconnected i/p or shorted o/p
 - Gates should not connect directly to supply  use Tie cells
 Floating gate error could lead to leakage issues
 VDD/VSS errors:
 The well geometries need to be connected to power/gnd
 If the PG connection is not complete or if the pins are not
defined, the whole layout can report errors like “NWELL not
connected to VDD
3. Antenna Check
III. Power 1. Dynamic IR
checks 2. EM (Electro Migration)
basics of timing constraints - clock definitions, virtual clocks, FP, MCP, clock groups, disable_timing, case_analysis etc.
SDC/Netlist will be provided by either RTL Designer or Synthesis Engineer.
1. Clock details Port, Name, Freq, waveform, Master clock, Generated

2. Source Clock creat_clock –name clk_500M –period 2 –waveform {0 1} [get_ports clka_port]

3. Generated clock creat_generated_clock –name clk_250M –master_clock clk_500M –period 2 –

divide_by 2
4. Clock Latency (src, n/w) set_clock_latency –source latency

5. Uncertainty set_clock_uncertainty  effective clk period

6. Clock groups set_clock_groups  Synchronous & Asynchronous (logical & physical

exclusive).
7. DRV constraints set_clock_transition  Clock i/p tran = 10% of clk period
set_max_transition  Data i/p tran = 25% of clk period
set_max_capacitance
set_max_fanout => Fo↑ => CL ↑; [CL = Cnet + Cpin]
8. I/O Delay Modelling set_input_transition/set_driving_cell
set_load
set_input_delay  60% of clk period data arrived at i/p port
set_output_delay  60% of clk period o/p required time
9. Constant value set_case_analysis

10. Feed through set_max_delay; set_min_delay

constraints b/w two - To optimise the ckt
points - Before placement use above cmds to optimize the cell low as possible
11. Timing Exceptions False path, MCP