Lab title:

Design and implementation of a digital clock/stopwatch on Spartan 3 FPGA kit.

Objectives:
In this lab the student would design and implement a digital clock/stop watch and display the result
on seven segment display of the Spartan 3 FPGA kit.
Literature Background:
Students are required to have the knowledge of
• Chapter 2 uploaded on the student portal.
• User manual for Spartan 3kit.
• User manual for Xilinx ISE design tool.
• Student should have done Lab # 7

Task 1: Watch
Modules Disp_hex
timescale 1ns / 1ps timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
//////////// ///
// Company: // Company:
// Engineer: // Engineer:
// //
// Create Date: 23:36:36 12/12/2023 // Create Date: 23:34:03 12/12/2023
// Design Name: // Design Name:
// Module Name: watch_if // Module Name: disp_hex_mux
// Project Name: // Project Name:
// Target Devices: // Target Devices:
// Tool versions: // Tool versions:
// Description: // Description:
// //
// Dependencies: // Dependencies:
// //
// Revision: // Revision:
// Revision 0.01 - File Created // Revision 0.01 - File Created
// Additional Comments: // Additional Comments:
// //
////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
//////////// ///
// Listing 4.18 // Listing 4.15
module stop_watch_if module disp_hex_mux
( (
input wire clk, input wire clk, reset,
input wire go, clr, input wire [3:0] hex3, hex2, hex1, hex0, // hex
output wire [3:0] d2, d0,d3, d1 digits
); input wire [3:0] dp_in, // 4 decimal points
output reg [3:0] an, // enable 1-out-of-4 asserted
// declaration low
localparam DVSR = 5000000; output reg [7:0] sseg // led segments
reg [22:0] ms_reg; );
wire [22:0] ms_next;
reg [3:0] d2_reg,d0_reg,d3_reg, d1_reg; // constant declaration
reg [3:0] d2_next, d0_next,d3_next,d1_next; // refreshing rate around 800 Hz (50 MHz/2^16)
wire ms_tick; localparam N = 18;
// internal signal declaration
// body reg [N-1:0] q_reg;
 // register wire [N-1:0] q_next;
always @(posedgeclk) reg [3:0] hex_in;
begin regdp;
ms_reg<= ms_next;
d3_reg <= d3_next; // N-bit counter
d2_reg <= d2_next; // register
d1_reg <= d1_next; always @(posedgeclk, posedge reset)
d0_reg <= d0_next; if (reset)
end q_reg<= 0;
else
// next-state logic q_reg<= q_next;
// 0.1 sec tick generator: mod-5000000
assign ms_next = (clr || (ms_reg==DVSR && // next-state logic
go)) ? 4'b0 : assign q_next = q_reg + 1;
(go) ?ms_reg + 1 :
ms_reg; // 2 MSBs of counter to control 4-to-1 multiplexing
assign ms_tick = (ms_reg==DVSR) ? 1'b1 : // and to generate active-low enable signal
1'b0; always @*
// 3-digit bcd counter case (q_reg[N-1:N-2])
always @* 2'b00:
begin begin
// default: keep the previous value an = 4'b1110;
d0_next = d0_reg; hex_in = hex0;
d1_next = d1_reg; dp = dp_in[0];
d2_next = d2_reg; dp = dp_in[0];
d3_next = d3_reg; end
if (clr) 2'b01:
begin begin
d0_next = 4'b0; an = 4'b1101;
d1_next = 4'b0; hex_in = hex1;
d2_next = 4'b0; dp = dp_in[1];
d3_next = 4'b0; end
end 2'b10:
else if (ms_tick) begin
if (d0_reg != 9) an = 4'b1011;
d0_next = d0_reg + 1; hex_in = hex2;
else // reach XX9 dp = dp_in[2];
begin end
d0_next = 4'b0; default:
if (d1_reg != 5) begin
d1_next = d1_reg + 1; an = 4'b0111;
else // reach X99 hex_in = hex3;
begin dp = dp_in[3];
d1_next = 4'b0; end
if (d2_reg != 9) endcase
d2_next = d2_reg + 1;
else // reach 999 // hex to seven-segment led display
always @*
begin begin
d2_next = 4'b0 ; case(hex_in)
4'h0: sseg[6:0] = 7'b1000000;
if (d3_reg != 5) 4'h1: sseg[6:0] = 7'b1111001;
d3_next = d3_reg + 1; 4'h2: sseg[6:0] = 7'b0100100;
4'h3: sseg[6:0] = 7'b0110000;
else 4'h4: sseg[6:0] = 7'b0011001;
4'h5: sseg[6:0] = 7'b0010010;
begin 4'h6: sseg[6:0] = 7'b0000010;
4'h7: sseg[6:0] = 7'b1111000;
 d0_next = 4'b0; 4'h8: sseg[6:0] = 7'b0000000;
4'h9: sseg[6:0] = 7'b0011000;
d1_next = 4'b0; 4'ha: sseg[6:0] = 7'b0001000;
4'hb: sseg[6:0] = 7'b0000011;
d2_next = 4'b0; 4'hc: sseg[6:0] = 7'b1000110;
4'hd: sseg[6:0] = 7'b0100001;
d3_next = 4'b0; 4'he: sseg[6:0] = 7'b0000110;
default: sseg[6:0] = 7'b0001110; //4'hf
end endcase
end sseg[7] = dp;
end end

end
end
// output logic
assign d0 = d0_reg;
assign d1 = d1_reg;
assign d2 = d2_reg;
assign d3 = d3_reg;
endmodule
endmodule
///////test///////
`timescale 1ns / 1ps
///////////////////////////////////////////////////////////////////////////////
///
// Company:
// Engineer:
//
// Create Date: 23:38:07 12/12/2023
// Design Name:
// Module Name: watch_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
///////////////////////////////////////////////////////////////////////////////
// Listing 4.19
module stop_watch_test
(
input wire clk,
input wire [1:0] btn,
output wire [3:0] an,
output wire [7:0] sseg
);
// signal declaration
wire [3:0] d3, d2, d1, d0;
// instantiate 7-seg LED display module
disp_hex_muxdisp_unit
(.clk(clk), .reset(1'b0),
.hex3(d3), .hex2(d2), .hex1(d1), .hex0(d0),
.dp_in(4'b1101), .an(an), .sseg(sseg));

// instantiate stopwatch
stop_watch_ifcounter_unit
(.clk(clk), .go(btn[1]), .clr(btn[0]),
.d2(d2), .d1(d1), .d0(d0),.d3(d3) );

endmodule
 Figure 1 result of watch on Spartan 3

Task#2:Stop Watch
`timescale 1ns / 1ps d2_reg <= d2_next;
///////////////////////////////////////////////////////////////////////////// d1_reg <= d1_next;
///// d0_reg <= d0_next;
d3_reg <= d3_next;
// Company:
// Engineer: end
//
// Create Date: 11:37:45 12/11/2023 // next-state logic
// Design Name: // 0.1 sec tick generator: mod-5000000
// Module Name: stopwatch assign ms_next = (clr || (ms_reg==DVSR && go)) ? 4'b0 :
// Project Name: (go) ? ms_reg + 1 :
// Target Devices: ms_reg;
assign ms_tick = (ms_reg==DVSR) ? 1'b1 : 1'b0;
// Tool versions: // 3-digit bcd counter
// Description: always @*
// begin
// Dependencies: // default: keep the previous value
// d0_next = d0_reg;
// Revision: d1_next = d1_reg;
// Revision 0.01 - File Created d2_next = d2_reg;
d3_next = d3_reg;
// Additional Comments:
if (clr)
// begin
///////////////////////////////////////////////////////////////////////////// d0_next = 4'b0;
///// d1_next = 4'b0;
module stopwatch( d2_next = 4'b0;
input [1:0] btn, d3_next = 4'b0;
input clk, d3_next = 4'b0;
output [3:0] an, end
else if (ms_tick)
output [7:0] sseg if (d0_reg != 9)
); d0_next = d0_reg + 1;
wire [3:0] d0,d1,d2,d3; else // reach XX9
watch begin
u1(.clk(clk),.go(btn[1]),.clr(btn[0]),.d0(d0),.d1(d1),.d d0_next = 4'b0;
2(d2),.d3(d3)); if (d1_reg != 5)
disp_hex_mux d1_next = d1_reg + 1;
u2(.hex0(d0),.hex1(d1),.hex2(d2),.hex3(d3),.clk(clk), else // reach X5 9
begin
.dp_in(4'b1011),.reset(1'b0),.an(an),.sseg(sseg)); d1_next = 4'b0;
if (d2_reg != 9)
endmodule d2_next = d2_reg + 1;
// Listing 4.15 else // reach 999
module disp_hex_mux begin
(
 d2_next = 4'b0;
if(d3_reg !=5)
d3_next = d3_reg+1;
else
d3_next = 4'b0;
end
end
end
end

// output logic
assign d0 = d0_reg;
assign d1 = d1_reg;
assign d2 = d2_reg;
assign d3 = d3_reg;

endmodule

Results:

Figure 2 result of stop watch on Spartan 3