KANDASWAMI KANDAR’S COLLEGE, VELUR

DEPARTMENT OF COMPUTER SCIENCE

Class: I B.SC(CS) & BCA Unit: IV

Paper Name: COA

UNIT - IV
Arithmetic Circuits: Arithmetic Building Blocks – The Adder - Subtractor – Fast Adder – Arithmetic
Logic Unit – Binary Multiplication and Division. Clocks and Timing Circuits: Clock Waveforms.
Flip- Flops: RS Flip-flops – Edge-triggered D Flip-flops - Edge triggered JK Flip-flops – JK Master-
slave Flip-flops.

ARITHMETIC BUILDING BLOCKS:

 Digital computers perform various Arithmetic Building Blocks.
 Three basic circuits are used as building blocks. These building blocks are the half-adder, the full-
adder, and the controller inverter.

Half-Adder:
 The most basic operation is the addition of two binary digits. This simple addition consists of
four possible elementary operations, namely,

 The first three operations produce a sum whose length is one digit, but when the last operation is
performed sum is two digits.
 The half adder operation needs two binary inputs: augend and addend bits; and two binary
outputs: sum and carry.
 The higher significant bit of this result is called a carry, and lower significant bit is called sum.

 The logic circuit which performs this operation is called a half-adder.

1
 The half adder circuit has two inputs: A and B, which add two input digits and generate a carry
and sum.
Full-Adder:
 The full adder circuit has three inputs: A and C, which add the three input numbers and generate
a carry and sum.
 This implies that we need a logic circuit with three inputs and two outputs
 A full adder is a combinational circuit that forms the arithmetic sum of three input bits. It
consists of three inputs and two outputs.

2
 The first two inputs are A and B and the third input is an input carry as C-IN.
 The output carry is designated as C-OUT and the normal output is designated as S.

K-map simplification for carry and sum

Controlled Inverter:
 When INVERT is low, it transmits the 8-bit input to the output; when INVERT is high, it
transmits the l's complement. For instance, if the input number is
A7 --- A0=0110 1110

a low INVERT produces

Y7 --- Y0=0110 1110

3
But a high INVERT results in
Y7 Y0=1001 0001
The controlled inverter is important because it is a step in the right direction. During a subtraction,
we first need to take the 2's complement of the subtrahend. Then we can add the complemented
subtrahend to obtain the answer. With a controlled inverter, we can produce the l's complement.

THE ADDER- SUBTRACTER:

We can connect full-adders to add or subtract binary numbers. The circuit is laid out from right to
left, similar to the way we add binary numbers. Therefore, the least-significant column is on the
right, and the most-significant column is on the left. The boxes labeled FA are full-adders.

The mode SUB input controls the operation as the following: 0 →adder. 1→ subtractor
The CARRY OUT from each full-adder is the CARRY IN to the next-higher full-adder. The
numbers being processed are A7 ... A0 and B7 ... B0, and the answer is S7 ... S0. With 8-bit arithmetic,
the final carry is ignored for reasons given earlier. With 16-bit arithmetic, the final carry is the carry
into the addition of the upper bytes

Addition:
The addition appears as,

 During an addition, the SUB signal is deliberately kept in the low state. Therefore, the binary
number B7 ... B0 passes through the controlled inverter with no change. The full-adders then
produce the correct output sum. They do this by adding the bits in each column, passing carries
to the next higher column, and so on.
 For instance, starting at the LSB, the full-adder adds A0, B0, and SUB. This produces a SUM of
S0 and a CARRY OUT to the next-higher full-adder. The next-higher full-adder then adds A1, B1,
and the CARRY IN to produce S1 and a CARRY OUT.
 Example:
4
 11011 + 1001010 = 1100101: 1010110 + 110100 = 10001010:

1 1 1 1 1 1 1

1 1 0 1 1 0 1 0 1 0 1 1 0

+ 1 0 0 1 0 1 0 + 0 0 1 1 0 1 0 0

1 1 0 0 1 0 1 1 0 0 0 1 0 1 0

No overflow. Sum is correct.

Subtractor:
The subtraction appears as,

During a subtraction, the SUB signal is deliberately put into the high state. Therefore, the controlled
inverter produces the l's complement of B7 ••• B0. Furthermore, because SUB is the CARRY IN to
the first full-adder, the circuit processes the data like this:

When A7 ... A0 = 0, the circuit produces the 2's complement of B7 ••• B0 because 1 is being added to
the l's complement B7 ••• B0. When A7 ••• A0does not equal zero, the effect is equivalent to adding
A7 ••• A0 and the 2's complement of B7 ••• B0.
Example: The numbers are +82 and +17. Then A7 ••• A0= 0101 0010 and B7 ••• B0= 0001 0001. The
controlled inverter produces the l's complement of B, which is 1110 1110. Since SUB = 1 during a
subtraction, the circuit performs the following addition:

For 8-bit arithmetic, the final carry is ignored; therefore, the answer is

FAST ADDER:
 Fast adder is also called parallel adder or carry look ahead adder because it attains high speed in
addition operation.
 A carry-look ahead adder improves speed by reducing the amount of time required to determine
carry bits.

5
  Consider, the worst case scenario when two four bit numbers A: 1111 and B: 0001 are added.
This generates a carry in the first stage that propagates to the last stage as shown next.
Carry: 111
A: 1111
B: 0001
10000
 Addition such as binary adder-subtractor is called serial addition or ripple carry addition.
For 32-bit serial addition there will be 32 stages working in serial. In worst case, it will require 2 x
32 = 64 gate delays to generate the final carry. Though each gate delay is of nanosecond order, serial
addition definitely limits the speed of high speed computing. Parallel adder increases the speed by
generating the carry in advance (look ahead) and there is no need to wait for the result from previous
stage. The logic expressions for si (sum) and c i+1 (carry-out) of stage ith are

6
Therefore, independent of n, the number of stages, the n-bit addition process requires only four gate
delays.

7
Now, consider the design of a 4-bit parallel adder. The carries can be implemented as

The complete 4-bit adder is shown in Figure b where the B cell indicates Gi, Pi & Si generator. The
carries are implemented in the block labeled carry look-ahead logic. An adder implemented in this
form is called a carry look ahead adder. Delay through the adder is 3 gate delays for all carry bits
and 4 gate delays for all sum bits. In comparison, note that a 4-bit ripple-carry adder requires 7 gate
delays for S3(2n-1) and 8 gate delays(2n) for c4.

ARITHMETIC LOGIC UNIT:

Arithmetic Logic Unit, popularly called ALU is multifunctional device that can perform both
arithmetic and logic function. Other than normal addition, subtraction it can also perform increment,

8
decrement operations. As logic unit it performs usual AND, OR, NOT, EX-OR and many other
complex logic functions. It also comes with PRESET and CLEAR options, invoking which all the
function outputs are made 1 and O respectively. Normally, a mode selector input (M) decides
whether ALU performs a logic operation or an arithmetic operation. In each mode different
functions are chosen by appropriately activating a set of selection inputs.

The outputs Cout, G3_0 and P3_0 are useful when addition and subtraction of more than 4-bits are
performed using more than one IC 74181

9
Logic operations are done bit-wise by making M = l and choosing appropriate select inputs. For
arithmetic operations M = 0 to be chosen and we have to appropriately place Cin (active low),

BINARY MULTIPLICATION AND DIVISION:

 Typical 8-bit microprocessors like the 6502 and the 8085 use software multiplication and
division. In other words, multiplication is done with addition instructions and division with
subtraction instructions. Therefore, an adder-subtracter is all that is needed for addition,
subtraction, multiplication, and division.
 For example, multiplication is equivalent to repeated addition. Given a problem such as
8x4=?
 The first number is called the multiplicand and the second number, the multiplier. Multiplying 8
by 4 is the same as adding 8 four times:
8+8+8+8=?
 One way to multiply 8 by 4 is to program a computer to add 8 until a total of four 8s have been
added. This approach is known as programmed multiplication by repeated addition.
 There are other software solutions to multiplication and division that you will learn about if you
study assembly-language programming.
 There are ICs available that will multiply two binary numbers. For instance, the 74284 and the
74285 will produce an 8-bit binary number that is the product of two 4-bit binary numbers.
These I Cs are very fast, and the total multiplication time is only about 40 nanoseconds (ns)!

10
CLOCKS AND TIMING CIRCUITS
 The heart of every digital system is the system clock. The system clock provides the
heartbeat without which the system would cease to function.
 Propagation delay is the time required for a signal to pass from the input of a circuit to its
output.
 A monostable is a basic digital timing circuit that is used in a wide variety of timing
applications.

CLOCK WAVEFORMS:
 The digital system signals are not digital logic levels but change with time, i.e. they are
dynamic. The clock signals advances the system logic through its sequence of steps.
 Ideal clock waveform:
 The ideal clock waveform is as shown below:

Clock cycle time:

 Each signal defines a basic timing interval during which logic operations must be performed.
 This basic timing interval is defined as the clock cycle time, and it is equal to one period of
the clock waveform.
Example:
What is the clock cycle time for a system that uses a 1 MHz clock?
Solution:

Synchronous Operation:
Most of the digital system change states in .Synchronism with the system clock. A change of
state will either occur as the clock transitions from low to high or as it transitions from high to
low.
1. Positive transition:
The low-to-high transition is frequently called the positive transition (PT). The PT is given
emphasis by drawing a small arrow on the rising edge of the clock waveform as shown in figure
below

11
A circuit that changes state at this time is said to be positive-edge-triggered.

2. Negative transition:
The high-to-low transition is called the negative transition (NT). The NT is emphasized by
drawing a small arrow on the falling edge of the clock wavefom1.

A circuit that changes state at this time is said to be negative edge- triggered.

Characteristics of an ideal clock:

1. The clock levels must be absolutely stable.
2. When the clock is high, the level must hold a steady value of +5 V. When the clock is
low, the level must be an unchanging O V.
3. Clock should have zero transition time
4. The frequency of the clock should be steady and unchanging over a specified period of
time.

Propagation Delay Time:

Propagation delay tp is the time between a PT (or an NT) at the input of a digital circuit and the
resulting change at the output. As shown in figure below, tpLH is the delay time when the output
is transitioning from low to high. tpHL is the delay time when the output is transitioning from high
to low. Usually tpHL > tpLH. We can assume that

12
Practical waveforms:

FLIP- FLOPS: Introduction

 A flip-flop is a bistable electronic circuit that has two stable states. The first electronic flip-flop
was invented by British physicists William Eccles and F. W. Jordan in 1918. It was initially
called the Eccles- Jordan trigger circuit.
 Flip-flops can be either simple (transparent) or clocked. The transparent ones are commonly
called latches. It is called a latch since it will hold, or latch, in either stable state. The word latch
is mainly used for storage elements, while clocked devices are described as flip-flops.

Flip-Flop States
The flip-flop output is either low state (state 0) or high state (state 1) as shown below:

13
Basic Flip-Flop
 One of the easiest ways to construct a flip-flop is to connect two inverters in series.
 The line connecting the output of inverter B (INV B) back to the input of inverter A (INV A) is
referred to as the feedback line. The latch using two inverters is as shown:

 Remove the feedback line and consider V1 as the input and V3 as the output as shown in below
fig. There are only two possible signals in a digital system, and in this case we will define L = 0
= 0V de and H = 1 = + 5 V de.

NOR-Gate latch:
The basic flip-flop can be improved by replacing the inverters with either NAND or NOR gates. The
additional inputs on these gates provide a convenient means for application of input signals to switch
the flip-flop from one stable state to the other.

RS Flip-flops using NOR gates:

Two 2-input NOR gates are connected to form a flip-flop. The two inputs labeled R and S, this
circuit will function exactly as bistable circuit.

14
The latch has two inputs reset (R) and set (S). It has two complementary outputs Q and Q . When
Q is set, Q will be reset and vice-versa. Consider the truth table of NOR gate as shown below:

From the truth table it is noted that if one of the input of NOR gate is logic 1, the output is logic is 0
irrespective of the logic present on the other input. One input of NOR gate A is called reset (R) since
it resets the output(Q=0) and similarly one input of NOR gate B is called set (S) since it resets the
output Q , there by setting the output Q to 1.

Working with RS latch:

1. The first input condition in the truth table is R = 0 and S = 0. Since a O at the input of a NOR
gate has no effect on its output, the flip-flop simply remains in its present state; that is, Q
remains unchanged.
2. The second input condition R = 0 and S = 1 forces the output of NOR gate B low. Both inputs
to NOR gate A are now low, and the NOR-gate output must be high. Thus a I at the S input is
said to SET the flip-flop, and it switches to the stable state where Q = 1.
3. The third input condition is R = I and S = 0. This condition forces the output of NOR gate A
low, and since both inputs to NOR gate B are now low, the output must be high. Thus a 1 at
the R input is said to RESET the flip-flop-'-and it switches to the stable state where Q = 0 (or
Q = 1).
4. The last input condition in the table, R = 1 and S = 1, is forbidden, as it forces the outputs of
both NOR gates to the low state. (Both Q = 0 and Q = 0 at the same time!)
The RS flip-flop working is summarized as shown below:

15
The standard logic symbols for an RS flip-flop is

RS Flip-flops using NAND-Gate latch:

A slightly different latch can be constructed by using NAND gates and we will call this latch an
R S flip-flop. To understand how this circuit functions, recall that a low on any input to a NAND
gate will force its output high. Thus a low on the S input will set the latch (Q = 1 and Q = 0). A
low on the R input will reset it (Q = 0). If both R and S are high, the flip-flop will remain in its
previous state. Setting both R and S low simultaneously is forbidden since this forces both Q and
Q high.

16
EDGE-TRIGGERED D FLIP-FLOPS:
The logic circuit of a positive-edge triggered D flip-flop is as shown below. The narrow positive
pulse (PT) enables the AND gates for an instant. The effect is to activate the AND gates during the
PT of C, which is equivalent to sampling the value of D for an instant. At this unique point in time,
D and its complement hit the flip-flop inputs, forcing Q to set or reset (unless Q already equals D).
Again, this operation is called edge triggering because the flip-flop responds only when the clock is
in transition between its two voltage states. The triggering occurs on the positive-going edge of the
clock; this is why it's referred to as positive-edge triggering.

On the leading edge of the clock (PT), the data bit is loaded into flip-flop and Q takes on the value of
D. the truth table is as shown below:

17
When power is first applied, flip-flops come up in random states. We can make the flip-flop to have
the desired starting state. Additional PRESET and CLEAR inputs are used. The PRESET and
CLEAR are called asynchronous inputs because they activate the flip-flop independently of the
clock. The D input is a synchronous input because it has an effect only with PTs of the clock. The
RS flip-flop can be converted into a D flip flop with additional PRESET and CLEAR inputs as
shown below:

Pressing the RESET button will set Q to 1 on the first PT of the clock. Q will remain high as long as
the button is pressed and the first PT of the clock after releasing the button will set Q according to
the D input. A high PRESET forces Q to 1, and a high CLEAR resets Q to 0

D Flip-Flop Symbols
The different D flip-flop symbols are as shown below:

EDGE TRIGGERED JK FLIP-FLOPS:

Setting R = S = I with an edge-triggered RS flip-flop forces both Q and Q to the same logic level.
This is an illegal condition, and it is not possible to predict the final state of Q. The JK flip-flop
accounts for this illegal input, and is therefore a more versatile circuit.

Positive-Edge Triggered JK Flip-Flop:

The pulse-forming box changes the clock into a series of positive pulses, and thus this circuit will be
sensitive to PTs of the clock.

18
The basic circuit is identical to the previous positive-edge-triggered RS flip-flop, with two important
additions:
1. The Q output is connected back to the input of the lower AND gate.
2. The Q output is connected back to the input of the upper AND gate.
This cross-coupling from outputs to inputs changes the RS flip-flop into a JK flip-flop. The previous
S input is now labeled J, and the previous R input is labeled K.

JK Flip-Flop Operation:
 Consider J = K = 1. If Q = 1, the lower AND gate passes a RESET pulse on the next PT and Q
changes to 0 as illustrated in the figure below:

 Consider J = K = 1. If Q = 0, the upper AND gate passes a SET pulse on the next PT and Q
changes to 1 as illustrated in the figure below:

 Therefore, J=K=1 means the flip-flop will toggle (switch to the opposite state) on the next
positive clock edge.
 The truth table of the JK flip-flop is shown below:

19
Racing Problem:
When J=K=1, the output can continue to toggle as long as the clock is high. This condition is called
the race-around condition. Propagation delay prevents the JK flip-flop from racing. The JK flip-flop
output changes after the PT of the clock. The new Q and Q values are too late to coincide with the
PT’s driving the AND gate. If PT’s are narrower than the propagation delay of the flip-flop, the
returning Q and Q arrive too late to cause false triggering.

Avoiding Racing Problem:

A better method to avoid race condition is to use a master-slave circuit.

JK Flip-Flop Symbols
The different JK flip-flop symbols are as shown below:

20
JK MASTER-SLAVE FLIP-FLOPS:
The JK master-slave flip-flop configuration is as shown below:

The J and K data is processed by the flip-flop after a complete clock pulse. On the positive transition
of the clock, the data from the J and K inputs is transferred to the master. On the negative transition
of the clock, the data from the master is transferred to the slave. The flip-flop is referred to as pulse-
triggered.

JK Master-Slave Flip-Flop Operation:

The master is positive-level-triggered and the slave is negative-level-triggered. Therefore, the master
responds to its J and K inputs before the slave.
1. If J = 1 and K = 0, the master sets on the positive clock transition. The high Q output of the
master drives the J input of the slave, so on the negative clock transition, the slave sets,
copying the action of the master.
2. If J = 0 and K = I, the master resets on the PT of the clock. The high Q output of the master
goes to the K input of the slave. Therefore, the NT of the clock forces the slave to reset.
Again, the slave has copied the master.
3. If the master's J and K inputs are both high, it toggles on the PT of the clock and the slave
then toggles on the clock NT. Regardless of what the master does, therefore, the slave copies
it: if the master sets, the slave sets; if the master resets, the slave resets.
4. If J = K = 0, the flip-flop is disabled and Q remains unchanged.

JK Master-Slave Flip-Flop Symbols

The master is transparent while the clock is high, and thus J and K must be static during this time.
The truth table reveals this action by means of the pulse symbol
The different JK Master-Slave flip-flop symbols are as shown below:

21
IMPORTANT DEFINITIONS:
 Arithmetic logic unit: A device that can perform both arithmetic and logic function based on
select inputs.
 Full-adder: A logic circuit with three inputs and two outputs. The circuit adds 3 bits at a time,
giving a sum and a carry output.
 Half-adder: A logic circuit with two inputs and two outputs. It adds 2 bits at a time, producing a
sum and a carry output.
 Hardware: The electronic, magnetic, and mechanical devices used in a computer or digital
system.
 Look Ahead Carry: Carry that need not ripple from one stage to other and is obtained through a
look ahead logic after the binary numbers are placed in adder unit; useful in fast addition.
 Magnitude: The absolute or unsigned value of a number.
 Microprocessor: A digital IC that combines the arithmetic and control sections of a computer.
 Parallel addition: A method of binary addition where carry generation at a particular stage does
not depend on availability of carry from previous stage.
 Overflow: An unwanted carry that produces an answer outside the valid range of the numbers
being represented.
 Ripple carry: Carry that ripples from one stage to other in serial addition.
 Serial addition: A method of binary addition where carry sequentially propagates from one
stage to next stage.
 Software: A program or programs. The instructions that tells the computer, how to process the
data.
 2's complement: The binary number that results when 1 is added to the l's complement.
 Asynchronous: Independent of clocking. The output can change without having to wait fora
clock pulse.
 Bistable: Having two stable states.
 Buffer register: A group of memory elements, often flip-flops, that can store a binary word.
 Edge triggering: A circuit responds only when the clock is in transition between its two voltage
states.
 Finite state machine: functional description of sequential circuit.
22
 Flip-flop: An electronic circuit that has two stable states.
 Latch: Another term for an RS flip-flop.
 Propagation delay: The amount of time it takes for the output to change states after an input
trigger.
 Setup time: The minimum amount of time required for data inputs to be present before the clock
arrives.
 State: the set of memory values at any given time for a sequential logic circuit.
 Synchronous: When outputs change states in time with a clock. A clock signal must be present
in order for the outputs to change states.
 Transparent: The condition that exists when the flip-flop output changes immediately after its
inputs (R, S, J, K, D) change state.

23