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    The document contains questions asked by Google and Samsung during interviews. Google's questions focused on if/else statements, schematics, clock domain crossing from clock A to B, constraints and errors in CDC. Samsung's questions covered work experience, past projects, issues with signals going to different blocks, CDC flow, lint issues, constraints, errors in CDC, convergence and reconvergence. They also asked about integration work if an output pin is not used internally and protocol-based questions.

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    The document contains questions asked by Google and Samsung during interviews. Google's questions focused on if/else statements, schematics, clock domain crossing from clock A to B, constraints and errors in CDC. Samsung's questions covered work experience, past projects, issues with signals going to different blocks, CDC flow, lint issues, constraints, errors in CDC, convergence and reconvergence. They also asked about integration work if an output pin is not used internally and protocol-based questions.

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    6 views1 page

    Interview Question

    Uploaded by

    BEST OF BEST
    The document contains questions asked by Google and Samsung during interviews. Google's questions focused on if/else statements, schematics, clock domain crossing from clock A to B, constraints and errors in CDC. Samsung's questions covered work experience, past projects, issues with signals going to different blocks, CDC flow, lint issues, constraints, errors in CDC, convergence and reconvergence. They also asked about integration work if an output pin is not used internally and protocol-based questions.

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    © All Rights Reserved
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    of 1

    GOOGLE

    1.tel me about your self?

    2.regarding case statement ? 10min

    3.regarding if else statement? 10min

    4.schematic view for if else?

    5.basic CDC based crossing single bit from clk A to clk B

    6.4bit signal from clk b to clk a

    7.why constraints ?

    8.what kind of error you face in CDC?

    9. what is divergence in CDC?

    Samsung

    1.tel me about your self?

    2.what are the clint you have worked?

    3.what you did in last two project?

    4.we have two block block A and Block B signal is going to each what is the issue or no issue ?

    5.what is integration full flow?

    6.what is CDC full flow?

    7.Parameter Verilog code?

    8.what are the lint issue?

    9.what are the constraints?

    10. use of each constraints with diagram?

    11.what are the error in CDC?>

    12.what is convergence and reconvergence ?

    13.we have A and B Ais top module ypin is output of b but I didn’t used inside the b then as a
    integration work what you have to do?

    14 no port connection for ypin with A block then what you do?

    15.Protocal based question ?

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