Dedicated professional, having 2.

5 years of working experience in Handoff to BE

team(static validation /UPF Team) in Intel, Certified Post Graduation Advanced
PREETI SINGH
Diploma in ASIC Design and looking for career as Design Engineer in Semiconductor RTL Design Engineer

industry, which utilizes my all potential for organization as well as my personal growth.
Contact
Work History
Address
Beml Layout
2021-02 - RTL Design Engineer Bengaluru, KA, 560066
Current Intel Corporation (Tech Mahindra payroll) Phone
Role & Responsibilities-. 847-693-5337

• Low Power Architecture and Design. E-mail

preetisinghmu@gmail.com
• Low power SoC UPF modelling.
• Hands on in Upf coding and static checks like VCLP. LinkedIn
https://www.linkedin.com/in/preeti-
• H2B: Handoff to BE team (FE collateral generation,
singh-15b4bb1a4
Synthesis with constraints and UPF, VCLP).
• Functional verification of RTL.
• Logic Equivalence Check. Skills
• Basics of Linting and CDC.
UPF/VCLP
PROJECTS: -
Very Good
1. Elasti X3 (Client: Intel Technology India Pvt Ltd)
2. ACM plus (Client: Intel Technology India Pvt Ltd) Synopsys IC Compiler II
3. Rialto (Client: Intel Technology India Pvt Ltd)
Very Good
Key points: -
STA
1. Generate Low power Collaterals (UPF) for SOC.
2. Static validation for VCLP test and debugging logs and Very Good
reports.
DRC & LVS Debug
3. UPF file generation in our design is Hierarchical UPF and
Merge UPF.
Very Good
4. Collage UPF generation.
Verilog
5. UPF validation with vclp version and methodology change.
6. Checking Outputs generated from Collage upf, logs and Working knowledge
reports.
Perl/TCL scripting
7. Synthesis with UPF & Timing constraints.
8. Writing design constraints with architecture team. Good

9. Worked upon Cheetah and HDK workflow.

 Prime Time

10. Paranoia Checks - ISOSPEC checks, PST Consistency,

Good
Pin spec check, HIP PIN Connectivity change.
Teamwork / collaboration
Physical Design Training
2019-10 – Very Good
RV- VLSI Design Center, Bengaluru, Karnataka
2020-11
Designing of ASIC block in 40nm Technology: Quick learner
• Targeted concepts of Floor planning, metal layers, Power
planning, Budgeting, Placement-Optimization, Clock Tree Very Good
Planning & Analysis, Scan Re-ordering, Clock Tree
Synthesis, Routing, Parasitic Extraction, Static Timing
Languages
Analysis, ECO tasks (timing & functional), DRC, LVS, Low
Power Solution development & Implementation.
• EDA Tools - Synopsys IC compiler II, Prime time. HINDI
• Good knowledge in logic design, CMOS concepts.
Native
• Proficient in ASIC PD flow from Floorplan to GDS II with
various inputs at each stage. ENGLISH
Analysis of Timing Reports (STA):
• Flip-flop and latch-based timing paths working at different Superior
operating conditions, Timing Reports are analyzed
GERMAN (Deutsch)
considering OCV, uncertainty, CRPR, Clock skews and
certain exceptions like multicycle paths. B1
• Understanding cell delays, derate factors, skew, setup time
and hold time, MCMM (Multi-Corner Multi-Mode) scenarios. KANNADA
• Timing paths analysis in different path groups after every
Novice
session (floorplan, placement, CTS).
• Differentiating violations based on timing exceptions - false
paths, multicycle paths. Reporting same to change constraints
file.

2018-09 - GNOC Engineer

2019-10 Contract employee at Huawei Technologies India Pvt Ltd,
Bengaluru, Karnataka
• L1 level alarm troubleshooting of 3G, 4G & 5G sites for Gulf
country project. Above 95% success rate in generated reports.
Tools - U2020, Remedy, PRS, CMD, Huawei operation web
services (OWS), Net boss, RDP, Cell Tracker.

2018-04 - RAN Integration Engineer

2018-09 Contract employee at Samsung Electronics Pvt Ltd, Navi
Mumbai, Maharashtra
 • eNodeB Integration, Commissioning & Configuration of new
4G sites for Reliance JIO LTE project.
Tools - Citrix, Site Forge, HPSM Ticketing tool, LSMR, Tera
Term, Secure CRT, Jio coverage Platform.

2017-01 - Semester Internship (2017)

2017-05 JK Tyre & Industries, Mysore, Karnataka
Project: Commissioning of Hydraulic Mixer

Education

2013-08 - Bachelor of Technology: Electronics &

2017-07 Communication Engineering (7.7 CGPA)
Mangalayatan University - Aligarh Uttar Pradesh

Certifications

2019-10 DIPLOMA IN ASIC DESIGN (Basic) - PHYSICAL DESIGN (1

Month)

2020-11 Post-Graduation ADVANCED DIPLOMA IN ASIC DESIGN -

PHYSICAL DESIGN

2021-02 Deutsch (German) A1, A2 and B1

Interests

Singing, Traveling, Determination Activities (Swimming,

Running, Cycling)

Achievement

• "Best Capability Improvement Award" for successfully

delivering service on Time
with customer expectations consistently, upskilled resources
to deliver services with multi domain
skills set, in Huawei technologies India Pvt Ltd Bengaluru.
 Additional Information

• Passport Available - Yes

DOB

• 8 September 1993