PD Flow I - Floorplan

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PD Flow I – Floorplan
by Jedi (http://www.signo semi.com/author/somashekhar/) | May 19, 2017 |
Weekly-Training-Sessions (http://www.signo semi.com/category/weekly-training-
sessions/) | 34 comments (http://www.signo semi.com/ oorplan-placement-
2/#respond)
 Blog Views: 42,033

PHYSICAL DESIGN – I (Import Design, Floorplan, Placement)
Physical design is process of transforming netlist into layout which is manufacture-

able [GDS]. Physical design process is often referred as PnR (Place and Route) / APR
(Automatic Place & Route). Main steps in physical design are placement of all logical
cells, clock tree synthesis & routing. During this process of physical design timing,
power, design & technology constraints have to be met. Further design might
require being optimized w.r.t area, power and performance.
General Physical Design Flow is shown below,
www.signoffsemi.com/floorplan-placement-2/ 1/20
9/5/2019 PD Flow I - Floorplan - Physical design, STA & Synthesis, DFT, Automation & Flow Dev, Verification services. Turnkey Projects
1. IMPORT DESIGN / NETLISTIN
Import design is the rst step in Physical Design. In this stage all required inputs &
required references are read into the tool. And also basic checks are done (design,
technology consistency).
Inputs required
1. Gate level netlist

2. Logical (Timing) & Physical views of standard cells & all other IPs used in the
design
3. Timing constraints (SDC)
4. Power Intent (UPF / CPF)
5. FP DEF & Scan DEF
6. Technology le
7. RC Co-e cient les
How to qualify Import Design?
1. Check errors & warning while reading netlist. Understand all warnings
2. Check for uniqui cation & empty modules
3. Check errors & warning while reading timing constraints. Understand all warnings
4. Check errors & warning while reading UPF/CPF. Understand all warnings
5. Timing QoR (Minimal violations with xable WNS & TNS)
6. Check MV Design (Equivalent to LP checks). Fix all errors & understand all
warning
7. Check for assign & tri statements (Usually its checked & xed after Synthesis)
Timing analyses after Import Design
It is always a good practice to do quick timing analyses after import design. Even
though post synthesis timing analyses is done in timing tool (PT, Tempus/ETS), it’s
better to check post synthesis timing QoR in PnR tools also (ICC, Innovus, Olympus)
before actual implementation starts.
Why it is required?
ICC/Innovus optimizes critical timing paths (violating paths) which are seen by it.
There can be chances that PnR tool is showing a complete di erent timing QoR
(huge violations) compared to Post Syn QoR seen in PT/Tempus. It can be because
of correlation issue / constraints issue. We can avoid unnecessary optimization;
timing & design closure will be easy if we correlate Import Design timing QoR with
Post Syn timing QoR.
2. FLOORPLAN
Floorplan is one the critical & important step in Physical design. Quality of your
Chip / Design implementation depends on how good is the Floorplan. A good
oorplan can be make implementation process (place, cts, route & timing closure)
cake walk. On similar lines a bad oorplan can create all kind issues in the design
(congestion, timing, noise, ir, routing issues). A bad oorplan will blow up the area,
power & a ects reliability, life of the IC and also it can increase overall IC cost
(more e ort to closure, more LVTs/ULVTs)
Before staring of Floorplan, it is better to have basic design understanding, data

ow of the design, integration guidelines of any special analog hard IPs in the
design. And for block/partition level designs understanding the placement & IO
interactions of the block in Full chip will help in coming up with good oorplan.
What is required to come with a good oorplan?
1. Basic design understating

2. Data ow diagram (DFA / Analyze logic connectivity in Synopsys ICC)
3. Integration guidelines
4. IO / Pin placement requirements
5. Special requirements from Full Chip oorplan

6. MV / LP requirements. Understanding of PDs & Vas
Di erent types of partitions / blocks
1. Memory intensive digital cores, graphic cores

2. Partitions / Blocks with analog Hard IPs
3. DDR & other High Speed Interface partitions / blocks / sub-systems
4. Channel partitions
Partitions with di erent critical tasks
1. Timing critical
2. Routing critical / Congestion
3. Blocks with complex Clock structure
Types of oorplan techniques used in Full Chip plan
1. Abutted (All inter block pin connections are done through FTs)
2. Non abutted (Channel based. All inter block pin connections are routed in
channels)
3. Mix of both – partially abutted with some channels
FLOORPLAN STEPS
1. Size & shape of the block (Usually provided by FC oorplan)

2. Voltage area creation (Power domains)
3. IO placement
4. Creating standard cell rows
5. Macro-placement
6. Adding routing & placement blockages (as required)
7. Adding power switches (Daisy chain)
8. Creating Power Mesh

9. Adding physical cells (Well taps, End Caps etc)
10. Placing & qualifying pushdown cells
11. Creating bounds / plan groups / density screens
Detailed discussion
1. Shape & size of the block / partition
In most of the case, block size & shape is decided by FC oorplan. Rectangle/Square
shape is best in terms of oorplan & further design closure. But in many case,
oorplan can be of rectilinear shape with many notches. It is always good practice
to discuss with FC oorplan team for any scope to improve block/partition level
oorplan.
2. Voltage area creation
In multi-voltage & multi power domain designs, voltage areas are required to guide
the tool to understand di erent domains.
There are two methods to create voltage area;
1. Abutted voltage area (Cells are not allowed to place in default voltage area)
As is no default domain area, voltage area feed-through (VA-FT) are required
to cross over di erent voltage areas.
2. Non-abutted voltage area (Cells are allowed to place in default voltage area)
3. IO / Pin placement
IOs / Pins are placed at the boundary of the block. Usually pin placement
information is pushed down from FC oorplan. But these locations can be changed
based on block critical requirements. Any change in pin location has to be discussed
with FC oorplan team. Timing critical interfaces need special attention, like next 2-
3 levels of logic from IOs are pre-placed near the IOs). Source synchronous
interfaces requires delay balancing taking OCV into considerations (This will
require manual placement & scripting)
4. Row creation
Rows area created in the design using cell-site (unit / basic). Rows aid in systematic
placement of standard cells. And standard cell power routes done considering rows.
Rows can be cut, wherever cell placement is not allowed OR hard placement
blockage can also be used.
5. Macro placement
Step 1 – Understand Pins & Orientation requirements of Macros
Step 2 – Follow data ow / hierarchy to place the Macros. Make use of reference
oorplan if available
Step 3 – All the pins of the Macros should point towards the core logic
Step 4 – Channels b/w macros should be big enough to accommodate all routing
reqs & should get a minimum of one pair VDD & VSS power grids in the channel
Automatic Floorplan / Macro-placement
Most of the PnR tools provide automatic oorplan option. Automatic oorplan
option creates its own macro placement based on the e ort & other options. But
these options are not matured enough to give optimum oorplan for all kind of
designs. This option will be handy, when design has 100s of Macros, but generated
oorplan needs lot of modi cation for further optimizations.
How to qualify Macro – Placement
1. All macros should be placed at the boundary

2. Check the orientation & pin directions of all macros
3. Spacing b/w macros should be enough for routing & power grid
4. Macros should not block partition level pins
5. [Iterations] Less congestion & good timing QoR – These cannot be achieved in
one shot, but need few iterations [Thorough & deep analyses are the key things
while iterating]
6. Adding placement & routing blockages
Bu er only blockages are added in channels b/w macros. Partial placement

blockages can be added b/w the channels blocking sequential cells (whose
placement in channels can degrade CTS QoR). Partial blockages are added in
congestion prone areas/notches/corners
7. Adding power switches
Power switches are required to gate the power supply of gated domain when not
required. Power switches are MT-CMOS (multi-threshold) cells, which will have very
high threshold voltage when device is OFF & very low threshold voltage when
device is on.
Power switches are inserted in power mesh & supply to all gated domain cells will
be through power switches. Hence a single / few switches are not enough. A strong
network of power switches connected in daisy chain fashion will be inserted in the
design.
8. Adding special cells (Well Taps, EndCaps, Spare Cells, Metal ECO-able cells etc)
Well connection – Almost all standard cell libraries are tap-less (substrate
connections are not done @ cell level). So Well-taps cells are added in
partition/chip level to tie the wells to VDD/VSS. Tap-gate spacing has to be met
while adding well-tap array.
EndCap Cells – These cells are inserted to take care of boundary DRC of Wells &
Other layers. End Cap Cells ensure proper terminations of rows, so that no DRC are
created. This is a physical-only cell.
How to qualify Floorplan?

1. Check PG connections (For macros & pre-placed cells only)
2. LP / MV checks on oorplan database
3. Check the power connections to all Macros, specially analog/special macros if any
4. All the macros should be placed at the boundary
5. There should not be any notches / thin channels. If unavoidable, proper blockages
has to be added
6. Remove all unnecessary placement blockages & routing blockages (which might
be put during oor-plan & pre-placing)
7. Check power connection to power switches
8. Check power mesh in di erent voltage area voltage area
9. Check pin-layers & check layer directions (H-V-H)
34 Comments
Sidhant on July 16, 2017 at 10:54 AM
Very well written Som. Simple and informative.
Reply
Jedi
(http://www.signo semi.com/user/somashekhar/)
on October 3, 2017 at 4:50 PM
Thank you Sidhant
Reply
Chiraag on October 3, 2017 at 12:32 AM

Types of oorplan techniques used in Full Chip plan –
1. Abutted (All inter block pin connections are done through “FTs”)
Could you please tell me what QoR, FT stands for?
Reply
Jedi
on October 3, 2017 at 4:06 PM
QoR – Quality of results

FT – Feed-Through
Reply
() on October 4, 2017 at 3:30 PM
very useful information, very well written, Please upload

information about CTS.
Reply
Santosh S on November 5, 2017 at 12:22 AM

How did you derive oorplan dimensions/size from the synthesis
netlist ? The netlist has been synthesized for rst time.
Reply
Jedi
on November 6, 2017 at 10:54 AM
For the rst time, you do a normal synthesis & take the
netlist into PnR tool, create the oorplan (size, macro
placement & io pin placement). Then you can do physical-
aware synthesis, using the oorplan information.
FYI – Block size & IO pin placement is mostly driven by Full

Chip plan.
Reply
koteswararao8 on November 12, 2017 at 11:33 PM

good
Reply
Bhaskar on November 24, 2017 at 1:16 PM

What are push down cells?
How to place them & qualify them?
Reply
Jedi
on November 24, 2017 at 10:47 PM
Push down cells are pushed from Top level/Full chip

oorplan into the blocks. These cells can be process metric
cells / or any other logical cell/macro. Location & guidelines
are provided by Fullchip team.
Placement of these cells can be quali ed by manual checks /

script
Reply
AK on November 27, 2017 at 12:03 PM

what is upsizing and downsizing of cells?? apart from placing them
up and down ?
Reply
Jedi
Up-sizing & down-sizing doesn’t mean moving the cells up

/down. Its increasing the drive strength of the cells.
Standard cell library will have di erent drive strength cells
(like 1X,2X,3X,4X,8X,12X,16X… ). For example, up-sizing is
changing a cell from 1X -> 2X & down-sizing is changing a cell
from 4x -> 2X.
For more on standard cells, refer –

http://www.signo semi.com/standard-cell-library-2/
(http://www.signo semi.com/standard-cell-library-2/)
Reply
AK on November 29, 2017 at 11:36 AM

You are still seeing timing issues even after doing proper synthesis
and oorplanning, how do you resolve these timing issues ?
Reply
Jedi
There can be many reasons. You should analyse timing

violations & nd out the root cause.
It can be because of:
1. Bad placement (Irrelevant placement/routing blockage,
bounds)
2. Bad clock skew
3. Noise / Detouring of nets
4. Blocking of lower Vt cells
5. Many more reasons
Reply
narendra on November 29, 2017 at 9:15 PM

you have not discuss about halo.i have one doubt some websites
mention halo allows bu ers and inverters. but it is practically is
correct are not. if correct or not how?
one more thing you have mention (bad oorplan can create all kind
issues in the design (congestion, timing, noise, ir, routing issues). ) in
this how to e ect noise in oorplan stage.
can tell this things.
Reply
Jedi
– Halo is primarily added to prevent placement of any cell in

speci ed area. Halo is added to prevent the congestion @
the edges of Macros / Blocks.
– Bad oorplan can create congestion issue & chances of

noise issues in congested area is more.
Reply
Sohin on April 18, 2018 at 10:50 AM
Two type of halo is present if HALO is soft then bu er and

inverter can be place and if HALO is hard them it block all
the cell to place.
Reply
Balu Benny on December 6, 2017 at 1:14 AM

How can we decide the spacing between macros during the
oorplan so as to reduce congestion?
Reply
Jedi
on December 6, 2017 at 11:34 AM
Spacing is proportional to Number of Pins in Macro &

available routing resource in that direction.
Formula : Channel width = (Metal width + Metal spacing) x
number of pins / vertical routing layers) + extra spacing
You can reduce congestion by putting bu er only blockage

in channel & giving some extra space on calculated channel
space.
Reply
Sohin Borad on January 29, 2018 at 1:58 PM

In the point no. 6 there is routing blockage is created over the PLL in
the gure. so is it possible to create routing blockages because
there is need for the clock routing. If we create routing blockages so
how clock route may be done.
Reply
Jedi
on February 19, 2018 at 4:25 PM
Blockages can be cut in such areas
Reply
sreekanth reddy on February 3, 2018 at 1:33 PM

How to solve $ ground net ?
While creating power nets and vias $ is e ecting the nets and vias
creation of VSS
Reply
Jedi
Can you elaborate the query
Reply
Sohin on February 11, 2018 at 12:40 PM

In the point no. 6 there is routing blockage is created over the PLL in
the gure. so is it possible to create routing blockages because
there is need for the clock routing. If we create routing blockages so
how clock route may be done.
Reply
Jedi
Blockages can be cut in such areas
Reply
Sharanya Khamithkar on February 11, 2018 at 11:15 PM

Very well explained. It helped alot. Thanks.
Reply
sonu on April 3, 2018 at 7:15 PM

if we place marco in middle what problem will aries and how to solve
these problem
Reply
Jedi
on April 30, 2018 at 7:07 PM
Macro, generally a SRAM will use upto M4-M4 metals. So

routing is blocked till M5-M6 on SRAMs, if these macros are
placed @ center then routing resources will be blocked & it
can cause congestion
Reply
shashikumar on April 19, 2018 at 1:16 PM

How to decide number of power straps for power planning?
Reply
Jedi
on April 30, 2018 at 7:02 PM
It depends on power need of the chip/block. IR has to be

accounted while deciding PG plan
Reply
Akarsh on August 23, 2018 at 11:03 PM

Why macros should be placed at the core boundaries and why their
pins should be facing core area?
Reply
Jedi
on September 14, 2018 at 7:08 PM
Macros have routing blockage till M4 / M5, so placing them

in the core would create congestion & detour paths.
Most pins of the macros communicate to the core logic and

as they are placed @ boundary, it would be optimum to face
the pins towards the core.
Reply
Rakesh on September 13, 2018 at 10:48 AM

Why we are placing tap cells in oorplan stage because there are no
standard cells. Can we place the tap cells in placement so that it can
reduce latch up?
Reply
Jedi
on September 14, 2018 at 7:03 PM
There is a DRC rule (well-tap to gate spacing), it has to be

met. So Tap cells are systematically placed honoring this
requirement during place stage.
Idea of keeping tap connections outside the standard cell is

to reduce area. Minimum required tap cells are added during
oorplan stage. If you try it add after placement, we may
not get enough space to meet the Tap cell requirement.
Reply
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9/5/2019 PD Flow I - Floorplan - Physical design, STA & Synthesis, DFT, Automation & Flow Dev, Verification services.

n services. Turnkey Projects

 Blog Views: 42,033

Physical design is process of transforming netlist into layout which is manufacture-

General Physical Design Flow is shown below,

1. IMPORT DESIGN / NETLISTIN

1. Gate level netlist

How to qualify Import Design?

Timing analyses after Import Design

Before staring of Floorplan, it is better to have basic design understanding, data

What is required to come with a good oorplan?

1. Basic design understating

5. Special requirements from Full Chip oorplan

Di erent types of partitions / blocks

1. Memory intensive digital cores, graphic cores

Partitions with di erent critical tasks

Types of oorplan techniques used in Full Chip plan

1. Size & shape of the block (Usually provided by FC oorplan)

8. Creating Power Mesh

1. Shape & size of the block / partition

2. Voltage area creation

There are two methods to create voltage area;

Step 1 – Understand Pins & Orientation requirements of Macros

Automatic Floorplan / Macro-placement

How to qualify Macro – Placement

1. All macros should be placed at the boundary

6. Adding placement & routing blockages

Bu er only blockages are added in channels b/w macros. Partial placement

7. Adding power switches

How to qualify Floorplan?

Thank you Sidhant

Chiraag on October 3, 2017 at 12:32 AM

Could you please tell me what QoR, FT stands for?

QoR – Quality of results

() on October 4, 2017 at 3:30 PM

very useful information, very well written, Please upload

Santosh S on November 5, 2017 at 12:22 AM

FYI – Block size & IO pin placement is mostly driven by Full

koteswararao8 on November 12, 2017 at 11:33 PM

Bhaskar on November 24, 2017 at 1:16 PM

Push down cells are pushed from Top level/Full chip

Placement of these cells can be quali ed by manual checks /

AK on November 27, 2017 at 12:03 PM

Up-sizing & down-sizing doesn’t mean moving the cells up

For more on standard cells, refer –

AK on November 29, 2017 at 11:36 AM

There can be many reasons. You should analyse timing

narendra on November 29, 2017 at 9:15 PM

– Halo is primarily added to prevent placement of any cell in

– Bad oorplan can create congestion issue & chances of

Sohin on April 18, 2018 at 10:50 AM

Two type of halo is present if HALO is soft then bu er and

Balu Benny on December 6, 2017 at 1:14 AM

Spacing is proportional to Number of Pins in Macro &

You can reduce congestion by putting bu er only blockage

Sohin Borad on January 29, 2018 at 1:58 PM

Blockages can be cut in such areas

sreekanth reddy on February 3, 2018 at 1:33 PM

Can you elaborate the query

Sohin on February 11, 2018 at 12:40 PM

Blockages can be cut in such areas

Sharanya Khamithkar on February 11, 2018 at 11:15 PM

sonu on April 3, 2018 at 7:15 PM