ABHISHIKTH_BEJJAM_DF01016 [2.

5]
MOBILE :918074377453
MAILID :abhishikthbejjam01@gmail.com
DOB :01/07/1997
PIN CODE :522004

Career Objective

Seeking for challenges in the field of Design for testability (DFT), which will make best
use of my skills and further polish my personality and career with an esteemed progressive
organization.

Professional Summary

 Currently having 2.5 years of experience in DFT.

 Good understandings of DFT scan insertion, Compression.
 Have good exposure to the ATPG pattern generation, stuck-at and Transition faults on block
level.
 Test coverage analysis and debugging DRC violations.
 Have exposure on Wrapper chains, OCC & EDT.
 Simulation Debug in timing and Notiming.
 Have good exposure to Mentor EDA tools :-TessentScan(DFT Advisor), TestKompress,
QuestaSim.
 Have good exposure to Synopsys EDA tools :- DFT Compiler, VCS.

Project Details

Project 1 DFT
Client Quick Logic
Preiod July 2022 to Till Date
Tools Used DFT Compiler, TestKompress, QuestaSim
My Responsibilities My Responsibilities were the following:-
 Worked on scan chain insertion.
 Worked on pre-scan DRC violation checking, developing
the scan specifications, insertion of scan chain to the
Logic and post-scan DRC violation checking.
 Debugging the DRC violation and fixing the violations.
 ATPG pattern generation and simulating the ATPG
patterns and debugging the pattern mismatches.
Project Description Flop count ~50k - ~80K

Project 2 DFT
Client Quick Logic
Period Oct 2021 to June 2022
Tools Used DFTCompiler, TestKompress, QuestaSim
My Responsibilities My Responsibilities were the following:-
 Involved in the scan insertion.
 Worked on the pre-scan DRC violation checking,
developing the scan specification, insertion of scan
chain into the logic and post-scan DRC violation
checking and fixing the violations.
 ATPG pattern generation and simulating the ATPG
patterns and debugging the pattern mismatches.
Project Description Flop count ~40k - ~70K

Project 3 DFT
Client Rockwell
Period Dec 2020 to Sept 2021
Tools Used DFT compiler, TestKompress, VCS
My Responsibilities My Responsibilities were the following:-
 Involved in the scan insertion for 4 partitions.
 Worked on the pre-scan DRC violation checking,
developing the scan specification, insertion of scan
chain into the logic and post-scan DRC violation
checking and fixing the violations.
 ATPG pattern generation and simulating the ATPG
patterns and debugging the pattern mismatches.
 Test coverage improvement analysis.
Project Description Flop count ~50k - ~90K

Educational Qualification

B.Tech (Electronics and communication Engineering)

University/Board : JNTU Kakinada.
Institute : Andhra Loyola Institute of Engineering and Technology
Year of passing : 2018
Pass Percentage : 60%
Intermediate (MPC)
University/Board : Board of intermediate.
Institute : Sri Chaitnaya Junior College
Year of passing : 2014
Pass Percentage : 69%
SSC
University/Board : Board of Secondary Education
Institute : St.Joseph`s High School
Year of passing : 2018
Pass Percentage : 7.8 (CGPA)