DILEEP_KUMAR_NARLA_DF01146 [2.

6]
Mail id : dileepnarla1997@gmail.com
Phone : 9949741968
DOB : 23/06/1997
Pin Code : 532212
_______________________________________________________________________________

Career Objective:

Aspiring for challenging assignments, one which will make best use of existing skills and further
my personal and career development with a progressive and forward thinking organization.

Experience Summary:

 Done Block Level Scan-Insertion, ATPG and Simulation.

 Generated patterns for stuck-at, at-speed fault models.
 Done Test coverage Improvement analysis and debugging DRC violations.
 Done debugging of No-Timing and Timing Simulation.
 Have exposure on Wrapper chains, OCC & EDT.
 Have a basic theoretical knowledge on MBIST and Boundary Scan.
 Hands on Industry Tools: Mentor Graphics (DFT Advisor, TestKompress, QuestaSim)
and Synopsys (DFT compiler, VCS).

Project Details :

Project 1 DFT
Client Alif Semiconductor
Period May 2022-till date
Tools Used DFT Compiler, TestKompress, QuestaSim
My Responsibilities My Responsibilities were the following:-
 Worked on scan chain insertion for 5 partitions.
 Fixed D1, D2, D3 DRC’s and inserted scan chains.
 Debugging the ATPG DRC’s violation and fixing the
violations.
 Done Test coverage analysis for all of partitions and reached
targeted coverage numbers.
 Started ATPG and simulating the ATPG patterns and
debugging the pattern mismatches.
 Flop Count was 35K – 80K.
Project Description ~1.2 million gate count

Project 2 DFT
Client Alif semiconductor
Period July 2021- Apr 2022
 Tools Used DFT Compiler, TestKompress, QuestaSim
My Responsibilities My Responsibilities were the following:-
 Involved in the scan insertion for 4 partitions.
 Efficiently resolved Pre-scan DRC’s & achieved good scan-
flop coverage.
 Resolved T3/T5 violations for few partitions and completed
ATPG.
 Patterns were simulated with Zero-delay mode & Timing
mode using QuestaSim.
 Resolved setup/hold violations with the help of STA team.
 Flop Count was 25K - 65k.
Project Description ~ 1 million gate count

Project 3 DFT
Client Quick logic
Period Oct 2020 - June 2021
Tools Used DFT Advisor, TestKompress, VCS
My Responsibilities My Responsibilities were the following:-
 Involved in the scan insertion for 4 partitions.
 Build the scan chains by balancing them.
 Resolved S1, S2 violations and able to write out scan insertion
netlist.
 Completed ATPG by using scan inserted netlist.
 Achieved target coverage numbers for Stuck-at & At-speed.
 Debugged simulation mismatches & made them PASSED.
 Flop count was 30k – 70k
Project Description ~1 million gate count

Academic Qualifications

Year of
Course Institution Percentage
passing
B.TECH (ECE) Aditya Institute of Technology and Management 2018 6.52 (CGPA)

Intermediate Narayana Jr college 2014 83%

S.S.C Aruna vidyalayam 2012 78%