Introduction

➢ Name – Gaurav Srivastava

➢ Experience – 7.5 Years
➢ B.Tech . - JSS Academy of Technical Education Noida (2015)
➢ Current Company Name with City - arm, Bengaluru
➢ Nature of Work – Memory Design
➢ Previous Work Experience -

Company Designation Duration

ST Microelectronics Consultant(Through Zia Semiconductors) Oct 2015 - Nov 2016

arm Consultant(Through Exiger) Nov 2016 - July 2018

arm Design Engineer Aug 2018 - March 2021

arm Senior Design Engineer March 2021 – till date

Good evening respected members of the Admission Committee,

I am Gaurav Srivastava .
I have a total of 7.5 Years of experience in the VLSI domain.
I have done my Bachelors in 2015 from JSS Academy of Technical Education Noida. . I
am currently employed with arm located in Bengaluru.
Most of my Experience comes from the Memory Design itself.
Below is the brief summary of my work experience .
I started my career by working as a consultant in ST Microelectronics from Oct 2015-
Nov 2016, then I worked
as a consultant in arm from Nov 2016 – July 2018 . I got the permanent position in
arm as a Design Engineer in Aug 2018 and got promoted to Senior Design Engineer in
March 2021 and at Present is working there .

1
 Highlights of the previous work

➢ Memory Compilers Experience – SRAM, Register Files(6T Bitcell)

Experience of the following activities throughout the compiler development timeline –
➢ SRAM Bitcell analysis which has following subsections –
✓ Write margin Analysis
✓ Write Assist analysis (negative bitline assist scheme)
✓ Access Disturb Margin (ADM)
✓ READ Assist analysis (Wordline lowering assist scheme)
➢ Sense Amplifier Analysis
➢ Margin Verification - Different types of margin verification in the memory which includes –
✓ Read ,Write & ADM(Access disturb Margins)
✓ Functional Margin (Races, Internal holds margins, Pulse width Check Margins)
✓ Race Ratio Calculations

Below is the Highlights of the activities that I have been a part of throughout my
Memory Compiler Design Experience .
I have worked on different nodes like TSMC 22nm, 5nm and 3nm and Samsung
18FDSOI nodes. I have mostly worked on 6T based bitcells and been a part of
SRAMs and Register Files Development.
I have been a part of Bitcell Analysis activity and in which I have done the following
activity .
I have done the Write margin analysis and calculated the offsets to be employed in
the bitcell for instance level verification.
I have worked on applying and tuning of negative bitline based write assist scheme to
improve Vmin and yield of the bitcell at instance level .
I have verified the access disturb margin and calculated the offsets for ADM to be
applied on the bitcell at the instance level simulation.
I have worked on Wordline lowering based read assist scheme , assist level
calculation and assist implementation in the Design .
As a part of the Read margin Tuning I have done Sense Amplifier analysis which
included both systematic and random offset calculation and optimization .
Apart from the analysis at the bitcell level , I have also done margin verifications
at the instance level also which included the read, write and adm verification and STP

2
tuning at the exhaustive PVT corners list .
I have done Functional margin verifications which included Races check ,Internal hold
margins or Sneak through Margins ,Critical Pulse widths check so that the Pulses of
critical signals do not evaporate at the high temperature and fast corners .
I have done Race Ratio Calculations which involves how different stages delays will be
varying statistically on a corner, this ratio is then used for the verification of Races
and internal hold margins .

2
 Highlights of the previous work (contd.)

➢ Characterisation -
✓ Setup, Hold & Cycle time
✓ Power & Leakage
✓ Data Accuracy
✓ Data validation (Tight Stimuli)
✓ Trend Analysis

Additional Work -
✓ Silicon Debug of RA1UHD Compiler in TSMC 22nm Technology .
✓ Reverse write fix in RF1HD (TSMC 22nm) when VDDPE (Peri Power) < VDDCE (Core Voltage)
✓ Worked as a Design Lead in two Memory Compilers(TSMC 22ULL RF1HD and RA1UHD)
✓ Feature Implementations like BIST,SCAN and Bypass modes
✓ Capacity based Read assist circuitry design and Self Time Path(STP) tuning
✓ Design of Decoding Logic for write assist trigger at different voltage domains

Apart from the Design activities, I have also been a part of characterization also .
In this I have done setup , hold and cycle time characterisation as a part of Timing
characterisation
I have also done power and Leakage characterisations.
Data accuracy check is basically in the compiler we only characterise corner instances
and interpolate the remaining instances . So this check is basically checking that how
well the interpolated instances are close to the actual simulation values by picking
some middle random instances .
Data validation Check is basically after the characterisation is done and we have
liberties available , then we give that actual setup and hold in to the instances and
check whether there are no missing paths or the memory is working fine and there is
no margin degradations and all the critical pulses are forming or not.
Then there is this trend check in which we check how the characterised data in the
liberties like setup hold cycle time leakage etc is following a proper trend or not . For
example Leakage should increase when the instances size increases because more
number of devices will be leaking now .Likewise we check for no abnormalities in the
trend in the liberties .

Then there are some additional works that I have been a part of e.g I have been a

3
part of Silicon Debug of RA1UHD compiler in TS22ULL technology . Basically in this
the testchip results showed that instances were failing for SF –40 and 125c corners .
After debug we found that in the silicon bitcell degraded much more compared to the
models that we used in the simulations. Workaround was to use the assist and final
fix included the PDK refresh from the foundary.
I had fixed the reverse write issue in the RF1HD compiler which was coming
basiccally in the domain where periphery supply was at 0.6v and core array supply
was at 0.8v , due to which there was dummy read happening because peri was slow
and bitcells started reading when Wordline became available . This was fixed by
tweaking the circuit in the periphery .
Then I had a chance to work as a Design Lead for two Compilers RF1HD and RA1UHD .
I also had a chance to be a part of implementing the test features like BIST , SCAN and
Bypass modes .
I implemented the usage capacity based self time path tuning . In this we provided
the customer that if his usage of the memory is more than 8MB ,then he should use
the read assist which is implemented through an external pin RAWL . In this case the
STP will be different and a little slower compared to when read assist is not being
used in usage less than 8MB. For this an extra STP tuning had to be done .
I implemented the decoding logic which successively enables the write assist levels
when used in different domains . Basically there were three domains to be supported
in the compiler 0.9v,0.8v,0.7v and each domain requires more level of write assist
compared to its previous domain so instead of using different cap for different
domains we took advantage of the cap previously applied in the higher domain and
added extra cap needed to generate extra write assist level. Using this we saved some
area also.

3
 Highlights of the present work till date
➢ Presently I am working on TSMC n3e node RF1HD compiler .
➢ The scope of this project is PPA optimization and Power gating Feature Implementation .
➢ Frequency Target is 4.5GHz .
➢ Responsible for implementing power gating scheme using headers and footers design
➢ Power down modes supported are -
✓ Chipenable – Active mode (mission mode, VDDPE and VDDCE are line and header footers are on)
✓ Chipdisable – WL Headers are turned off only and WL is clamped to VSSE
✓ Selective Precharge – BL Precharge circuits is turned off reducing BL leakage
✓ Retention1 mode – VDDPE footers are turned off along with BL Pchg and WL Headers and all the outputs are clamped to VDDPE
✓ Retention2 mode – Core Array supply is brought down to retention voltage of bitcell using diode based design alongwith vddpe footers,
BL PCHG and WL Headers turned off .(Retention2 diode sizing analysis)
✓ Complete Power down mode – Headers and Footers of VDDPE and VDDCE both turned off memory goes into Deep Sleep mode and Time
Required to come out of this mode is significantly higher than other modes

➢ Inrush Current reduction is done using daisy chaining the power up sequence through the memory to reduce
the surge current at the time of wake up

Currently I am working in TSMC n3e RF1HD compiler .

In this we have the scope of the project is ppa optimization and power gating feature
implementation
We have a timing target of 4.5GHz of frequency. At present we are at 4Ghz . For this
we need to see how can we reduce that . We are checking in clk2wl,wl2sae and
sae2q paths for optimization .
Then I will be implementing the power gates and have to come up with appropriate
size for the headers and footers .
In power gating feature implementation we will support following 6 power down
modes .
Chipenable This is actually the active or mission mode. All the supplies will be live in
this mode .
Then Chipdisable mode – This mode is when memory is not selected . In this the WL
headers will be turned off . This will reduce the core leakage .
Then there is Selective Precharge mode – In this we will turn off the BL precharge
circuit also along with WL Header this will save peri leakage .
Then Retention 1 mode is there in which VDDPE footers are turned off along with
BL Pchg and WL Headers and all the outputs are clamped to VDDPE
Then Retention 2 mode is there in which Core Array supply is also brought down to

4
retention voltage of bitcell using diode based
design alongwith vddpe footers, BL PCHG and WL Headers turned off . I have done
the Retention2 diode sizing analysis also in this .
Then there is Complete Power down mode in this Headers and Footers of VDDPE and
VDDCE both turned off and memory goes into Deep Sleep mode and Time Required
to come out of this mode is significantly higher than other modes
Another scope of this project is to keep the inrush current as low as possible . This we
are doing by daisy chaining the power up sequence through the memory to
reduce the surge current at the time of wake up

4
 What is the motivation behind pursuing M.Tech in VLSI?

➢ A deep-rooted fascination with the advancements in electronics and a desire to be a part of the ever -evolving
field. This course will provide me with a strong foundation and exposure to cutting-edge research in VLSI.
➢ Acquiring a comprehensive understanding of Digital integrated circuits Design , Analog Circuits Design ,Mixed
Signal Design, microprocessors and verification techniques. This specialization aligns perfectly with my career
goals, as I have a keen interest in designing and implementing complex integrated circuits
➢ M.Tech in VLSI provides a platform for exploring research areas such as low-power design, nanotechnology,
Design Automation, Statistically aware Design etc.
➢ Enhancing problem-solving, analytical, and critical thinking skills while developing a strong foundation in
electronics and integrated circuit design.
➢ I believe that the part-time format of the program at IIT Roorkee will enable me to continue working while
pursuing my academic goals. This flexibility is crucial for me to maintain my professional commitments while
gaining the necessary theoretical knowledge and practical skills in VLSI.

There are multiple reasons behind pursuing M.Tech in VLSI e.g. I have always been
fascinated by the advancements in electronics . I feel like This course will provide me
with a strong foundation and exposure to cutting-edge research in VLSI.
I feel that through this course I would be able to acquire necessary skills through
courses like Digital circuits Design , Analog Circuits Design ,Mixed Signal Design
etc which will be helpful in designing and implementing complex integrated circuits
I feel that pursuing M.Tech. will provide me a platform for exploring areas such
as low-power design, nanotechnology, Statistically aware Design etc .
Also I feel that through this course I would be able to enhance my problem-solving,
analytical, and critical thinking skills in circuit design .
And above all I believe that part time format will enable me to keep my professional
commitments while gaining the necessary theoretical knowledge and practical skills
in VLSI.

I feel that the program's curriculum, coupled with the guidance of esteemed faculty
members, will provide me with the necessary theoretical foundation and practical
expertise to excel in this field.

5
6