RAMAKANTH GOLADARI
E-mail: goladari1990@gmail.com
Mobile: +91-9966522605(India)
Professional Experience
● Extensive experience of 7+ years in AMS Layout Design on AI-Neural networks, SerDes, Automotive, PMIC,
DRAM and Ethernet product lines.
● Excellent knowledge on TSMC 5nm and 7nm nodes.
● Worked on 5nm, 7nm, 10nm, 14nm, 16nm, 28nm 40nm, 90nm, 130nm, 180nm and 350nm.
● Worked with processes from various foundries like TSMC, GF, Micron, and Tower Jazz.
● The work involves in module’s layout, chip/IP layout and Release checks of Analog and Mixed signal IP’s
Error checking (DRC, LVS, Density, DFM, LUP, EM).
● Good experience in coordinating team members and mentoring juniors to complete schedules on time.
● Exceptionally good at handling the high frequency layouts.
● Has knowledge about isolation/coupling and takes care of them during IP placement.
● Has basic knowledge about packaging and can floorplan chip top level that is package compliant.
● Good knowledge on IP release flow and handled multiple IP releases with all QA checks.
● Good at understanding layout multi-stack methodology and working on multi-stack supporting layouts.
Technical Tools used
• Layout Tools : Cadence Virtuoso Layout/XL/GXL, Virtuoso -ICADVM 18.1
• Verification Tools : Calibre, PVS (Cadence-Physical verification system), Assura
• Schematic Tools : Cadence Virtuoso Schematic
• EM : Voltus-fi
• RC Extraction : QRC
Organizational Experience in IC Mask/Layout Design
➢ Total years of Experience : 7 years and 8 months
➢ Present working company:
• Company name : Redpine signals India Pvt Ltd, Hyderabad, India
• Designation : Senior Layout Engineer
• Duration : August 2020 to till date
➢ Second company:
• Company name : Micron Technology, Hyderabad, India
• Designation : DEG, Layout Engineer
• Duration : April 2019 to July 2020
➢ First company:
• Company name : First Pass Semiconductors, Hyderabad, India
• Designation : Layout Engineer, Senior Layout Engineer (Promoted)
• Duration : September 2013 to March 2019
Education
● Bachelor’s Degree in Electronics and Communication Engineering from Acharya Nagarjuna University-2013.
● Diploma in Electronics from NTTF-2009.
1. AI-Neural networks Product line
Title : QS1, TSMC 5nm
Team size :6
Role-played:
● Working as a senior layout engineer and managing a small team of junior engineers.
● Worked on RC and Crystal oscillator.
● Worked on PLL, OTA, HBI, TX, SERIALISER, TX-DRIVER, and DRIVER SIGMENTS layouts.
● Worked on SAR ADC top level from scratch.
● Set few in-house methods to work on the latest TSMC 5nm node.
2. DRAM Product line
Title : Z42M, MICRON foundry, 10nm
Title : RA3MR, MICRON foundry, 10nm
Title : Y32A, MICRON foundry, 10nm
Role-played
● Designed layouts for sub-blocks of BCENTP, OSCILLATORS, CHARGE PUMPS, DDL-TOP from scratch to top
level.
● Made layouts with zero QA issues.
● Worked on Matched routing, shield DRC and Yield enhancement check.
3. SerDes IP Product line:
IP Title : X320-SERDES, TSMC7nm – FinFET Process
IP Title : X321-SERDES, TSMC16nm – FinFET Process
IP Title : X082-SERDES, TSMC16nm – FinFET Process
IP Title : X083-SERDES, GF14nm – FinFET Process
IP Title : X050-SERDES, TSMC16nm – FinFET Process
IP Title : X046-SERDES, TSMC28nm – CMOS Process
Blocks handled.
● SUP ANA, PRESCALER, SERIALIZER, RTUNE TOP, POR TOP, VCO, REGULATOR BLOCKS
● TX TOP, TX_VDRIVER, TX_SERIALIZER,
● RX AFE, RX_AFE_EQ_R, RX_LOS_TOP, V2I
Challenges
● Prescaler is the heart of sup_ana, it provides reference clocks to PLL’s. Taken care of the placement and
clock signals.
● Self-heating effect, it is really challenging while fixing EM/IR in lower nodes.
● Routing lengths are reduced with good floorplan in serializer.
● Modified Inductor to meet required inductance for VCO block.
● Planned excellent power distribution for Regulators and V2I blocks.
● Clock routings are planned on IP level.
● Handled PLL abutting issues with other top levels.
● Power planning is taken care in TSMC7FF.
● Solved density fixes manually.
● Worked on Sanity checks like missing via, floating metals and DFM checks.
4. Ethernet Product line:
Title : ONEG, ETHERENET IP, TSMC foundry, 90nm
Title : NEO, GF foundry, FinFET process, 14nm
Role-played
● Worked on layouts from scratch for RX_bias, DAC with LVS, DRC, DFM and Density checks.
● Worked on RXAFE-TOP which includes PGA, CMFB, TWO STAGE LPF with LVS and DRC.
● Also worked on PLL REGULATOR, CB_TOP with LVS and DRC.
● Executed parasitic extraction with calibre for the all above mentioned blocks.
5. Automotive and Image Processing Product line:
Title : CMTOPS00, TSMC foundry, 40nm
Title : DADCCORE, TSMC foundry, 40nm
Role-played
● Worked on layouts from scratch for CMTOP, CMDRVR, CMDRVL, CMCLM array with LVS & DRC checks.
● Worked on layout from scratch for OP-AMP, OUTBUFF, MONOUT with LVS & DRC checks.
● Worked on top level signal and power routing.
6. Power Management Product line:
Title : SC60518, Tower Jazz foundry, 180nm
Title : SC40000, Tower Jazz foundry, 180nm
Title : SC60512, Tower Jazz foundry, 180nm
Title : TC91404, Tower Jazz foundry, 180nm
Title : TC91406, Tower Jazz foundry, 180nm
Title : SC35130, Tower Jazz foundry, 350nm
Role-played
● Designed layout for Ldoamp, Startldo, ldoamp,ATOP_ldo, LED_ADC_DAC, LEDSINK,
LEDBLK,LED_PGMFLT,LDO_uvlo, LDO_uvlo, DC control, COMP_RAMP, VLOOP_EA blocks with LVS and DRC
checks.
● Designed layout for Startldo, ldoamp, ldoreg, halflatchBstsw , power42vLox_Drivers,references_OT blocks
with LVS and DRC checks.
● Worked on top level signal routing for major sections like LED, BB_loop and BB_top.
● Designed layout for BCK_SS, BCK_PASVE, BCK_ACP_CLMP,rampClockGen_logic,
ATOP_VMON_logic,DtimeLogic,BCK_loop, and ILIMIT blocks with LVS and DRC checks.
● Worked on top level routing for ATOP (Analog top) having five major sub- blocks.
● Designed layout for ATOP_references, ATOP_trim_test and ATOP_itrim_mirrblocks with LVS and DRC
checks.
● Worked on PADs and ESDs placement.
● Worked on chip level power and signal routing with verification (DRC & LVS).
