TANMAY KABRA

Sr. Technical Lead, Qualcomm, Bengaluru, Karnataka.

Mob:(+91)7022120493, Email: Tanmay290@gmail.com
LinkedIn: https://in.linkedin.com/in/Tanmay-kabra

WORK SUMMARY
➢ Having 7 years’ experience in DFT implementations and effectuated DFT architecture via
ECOs, timing constraints development, scan insertion for a SSN based architecture, DFT
pattern generation, Silicon debug and characterization on ATE.
➢ Served as peer mentor to several junior members in the team. Good team player with an
attitude to learn and adapt, enabling individual and program success.

WORK EXPERIENCE
Sr. Technical Lead, Qualcomm, Bengaluru, India (Feb 2019 - present) – Worked on multiple
SOC’s for DFT activities primarily focusing on scan insertion for an SSN based architecture and
SOC test constraints handoff to STA & PD team and ensuring smooth timing closure.
➢ Responsible for scan insertion for an SSN based architecture involving DC-DRC cleanup,
ATPG, hierarchical coverage analysis and attaining high quality metrics for multiple blocks.
➢ Responsible for SOC test timing constraints development covering all ATPG scenarios,
assessing timing reports and exceptions from netlist release till tape out of the project.
➢ Providing timing feedbacks on DFT implementation changes on scan partitioning, defining
pipeline architecture to achieve high shift frequency.
➢ Providing pre-placement guidelines and end to end discussion with PD & STA team including
retiming flops/Lockup addition and clock ECO generation for test mode setup & hold timing
closure.
➢ Provide capture mask list and pipeline enablement information to ATPG with quality to avoid
silicon fail and responsible for silicon debug for stuck-at and at-speed vectors at timing
perspective.
➢ Developed methodology/flow for merge mode and cross-corner constraints.

ASIC engineer, Einfochips (AVAGO client) Bengaluru, India (March 2018 – Feb-2019) – Worked on
multiple networking chips and responsible for the in-time delivery of DFT production pattern
according to our quality metrics.

➢ Responsible for ATPG pattern generation - DRC cleanup and coverage analysis.
➢ Performed vector simulation on test patterns and ensured quality test patterns to ATE.
 ➢ Vector conversions for different ATE production testers like Teradyne, Verigy93K and failure
Diagnosis using tetramax.

Test engineer, Tessolve semiconductors ( FPC client) Bengaluru, India (March 2016 – March -2018) –
Worked on test program creation and validation DFT and functional vectors
➢ Test program development and debug of structural and functional patterns on V93K ATE.
➢ Analyzed shmoo plots, evaluate product margin.
➢ Production support for at Wafer and Package level.
➢ Characterization of IC for different voltages and Temperatures.

TECHNICAL SKILLS
➢ Strong understanding of DFT methodologies and tooling
➢ Scan insertion, DRC debug, STA Constraints development, timing analysis
➢ ATPG Pattern generation, coverage analysis, Gate level simulation debug, Post silicon
debug and support on failing pattern.
➢ Test flow and test program creation for Production testing. Direct experience in
silicon bring-up, debug, and validation of DFT features on ATE.
➢ VLSI programming Languages: Verilog HDL.
➢ Scripting Languages: Perl, Tcl, shell
➢ Tools Used: DC compiler, Tessent – Mentor Graphics, Tessent -TestKompress,
complier, Prime-time, Tempus.

EDUCATION
➢ May 2015 - B.Tech. in Electronics & Communication, Punjabi University, Patiala.
➢ April 2011 - Intermediate Central Board of Secondary Education.
➢ April 2009 - High School Central Board of Secondary Education.

Awards and Achievements

➢ Video paper selection in QBUZZ for Test constraints Challenges and improvements
➢ Awarded for successful Tape-out of multiple Networking chip for Avago by
Einochips.
➢ Awarded for quality test program development for FPC projects by Tessolve semiconductors.