Venugopal N

Flat S2, Deccan Fields

Marathalli, Bangalore

cell: 8050476656
iitgopal@gmail.com

Summary
3 years of experience in IO circuit design along with experience in setup and execution of flows such as
Timing Liberty model generation and EMIR.

Professional Summary

Presently (1.8 year) working at Synopsys Bangalore, as Design Engineer from 17-Sep-2014
Currently working on DDR block CMPANA and
Timing characterization for entire LPDDR4 using Nano-time and Silicon-Smart
Worked on DDR blocks Vrefglobal and POR
Successfully delivered GPIO1.8 in TSMC16ff
Timing characterization using Silicon-Smart for GPIO1.8
Equivalence Checks formality & ESP-cv
EMIR analysis
1.2 years at AMD Bangalore as Design Engineer from 8-July-2013
Worked in GPIO1.8 in GF20
Written Verilog (Behavior model) for GPIO1.8/3.3, PWRGOOD1.8/3.3
Design of RX &TX for GPIO
Design of PWRGOOD1.8 blocks
Design of DFTIO blocks
Performed simulations on GPIO3.3 & SDIO
Developed ATPG models
Worked on LEC & totem flows

Education
M.Tech in Electrical Engineering with a CGPA of 7.64
B.Tech in ECE with a percentage of 60.00

IIT Roorkee 2010-12

JNTU 2005-09

Technical Skills
Technologies: GF-28nm, GF-20nm, TSMC-16nm (Finfets), GF-14nm (Finfets)
Schematic &Layout editors: Cadence Virtuoso schematic editor, Synopsys Custom Designer
Simulator: hspice, Spectre, ADE-L/XL, SAE
Timing characterization: Silicon-Smart and Nano-time
HDL: Verilog, VCS Verilog Logic Simulation Tool
Logic equivalence Tools: LEC, formality & ESP-cv
EMIR flow: XARA flow
Languages: Shell scripting and basic perl.

Employment History
Synopsys India Pvt Ltd

June 2016- till present

Senior Analog Design Engineer, IO Design Group, Bangalore.

Synopsys India Pvt Ltd

September 2014- May 2016

Analog Design Engineer, IO Design Group, Bangalore.

AMD India Pvt Ltd

July 2013- September 2014

Design Engineer-2, IO Design Team, Bangalore.

Awards
PCT Excellence award in AMD
Spot Recognition award in AMD
Project award for Silicon success of TSMC16ff GPIO library

References
References will be provided on request. I hereby declare that the information given above is true
& correct to the best of my knowledge.
Venugopal N
Bangalore