RISHIKESH SURESH TAMBULKAR

PROFESSIONAL EXPERIENCE
 6+ year experience in semiconductor industry.
 Currently working with Intel client in HPG group in analog team with 3nm Intel Custom
foundry (ICF) in full custom layout design and mixed signal blocks.
 Worked at Qualcomm client in DDR group in Macro and IO team with 3nm 4lpe Samsung
and 4nm 4N TSMC Tech node with experience in Full custom Layout Design including
analog and Mixed Signal Blocks.
 Worked at Synopsys in SerDes Team with 65nm STM and 40nm TSMC tech node with
experience in Full custom analog and mixed signal Blocks.
 Worked in Intel in 5nm TSMC project of test chip, GPIO team with tech node 22nm ICF
majorly involves metal modifications and verification check, thermal Sensor team with
10nm ICF tech node.
 Handled layout design of BGR in 40nm SMIC at in-House project at Altran.
 Worked on full custom layouts, analog and mixed signal layouts, IO Layouts.
 Experience in solving DRC, LVS & ERC, IR, Latch-up, EM, IR drop.
 Detailed exposure to critical matching, floorplan, placement,routing, shielding in layouts.

TECHNICAL SKILLS
Layout Tools Cadence Virtuoso Layout Editor, Synopsys custom compiler
LVS/DRC Tools Calibre, ICV
VLSI Simulation Tools Cadence Virtuoso Spectre

AREA OF EXPERTISE
Matching Techniquesimplementation for analogblocks
Good understanding of Layout Dependent Effect (WPE, LOD and STI etc)
Preventing Latch up by proper addition of taps and Guard rings
IR, EM,shielding the critical nets

PROJECTS
1. AIB Test chip (ICF 3nm FinFET Technology)
Environment : Cadence Virtuoso Layout Editor EXL, ICV LVS/DRC, Totem tool for EM/IR.
Blocks : Analog and Mixed signal Blocks
Description :
 A test chip consists of different IP’s called CBB, out of which RXCLK CBB has been handled
as a team lead.
 Project consists of various analog and mixed signal blocks in ana top and in digital top.
  Layout has to be made from scratch from given schematic till top level.
My Role :
 Fully handled top block RXCLK from scratch layout development to top layout
development including placement of devices, floorplan of sub-blocks on top, routing in
sub-blocks till top and layout verification.
 Lead the team of colleague to get the work done in sub-block wrt floorplan, routing and
verification.
 Fixed the EM/IR by using Totem tool to get the RV and IR drop clean.
 Worked and synced with other TL and client in various CBBs to meet time constraints and
develop high efficient layout
 Develop layout from schematic, critical matching, floor plan, placement, routing .
 Done pin placement, LEF generation of RXCLK CBB.
 Clean DRC, LVS, ERC, EM and IR drop.

2. DDRIO (4lpe Samsung 3nm FinFET Technology)

Environment : Cadence Virtuoso Layout Editor XL, Calibre LVS/DRC.
Blocks : Analog and Mixed signal Blocks
Description :
 Project consists of different analog and mixed signal blocks .
 Layout has to be made from scratch from given schematic and their next 3-4 hierarchy.
My Role :
 Closely worked with TL in different analog and mixed signal blocks to meet time
constraints and develop high efficient layout
 Develop layout from schematic, critical matching, floor plan, placement, routing
 Clean DRC, LVS and ERC

2. DDRIO (4N TSMC 4nm FinFET Technology)

Environment : Cadence Virtuoso Layout Editor XL, Calibre LVS/DRC.
Blocks : Analog and Mixed signal Blocks
Description :
 Project consists of different analog and mixed signal blocks from scratch to top
 Layout has to be made from scratch from given schematic and their next 3-4 hierarchy.

My Role :
 Closely worked with TL in different analog and mixed signal blocks to meet time
constraints and develop high efficient layout
 Develop layout from schematic, critical matching, floor plan, placement, routing
 Clean DRC, LVS and ERC

3. DDR-macro (4N TSMC 4nm and 4lpe Samsung 3nm FinFET Technology)
Environment : Cadence Virtuoso Layout Editor XL, Calibre LVS/DRC.
Blocks : Analog and Mixed signal Blocks
Description :
 Various top level block has to be made from scratch
My Role :
  Develop layout from schematic, critical matching, floor plan, placement, routing
 Clean DRC, LVS and ERC

4. Test Chip (TSMC 5 nmFinFET Technology)

Environment : Cadence Virtuoso Layout Editor XL, Calibre LVS/DRC.
Blocks : Array of Different Device Flavours
Description :
 Different flavours contain SVT, LVT, ULVT, ELVT, XLVT, LVTLL,ULVTLL of P-FinFET and N-
FinFET devices.
 It has an array of N-FinFET and P-FinFET cells with different fins and different widths
arranged in column and row fashion.
My Role :
 Worked on making the array with different flavours of devices in circuit.
 Modification in array layout wrt device layers and parameters.
 Changes in device parameters in circuit wherever required.
 Layout verifications like LVS/DRC were performed.

5. SerDes (TSMC 40 nm Technology)

Environment : Synopsys Custom Compiler, ICV LVS/DRC, Calibre LVS.

Block : RX_LOSD
Description :
 It has PREAMP, COMPARATOR, and level shifter sub blocks.
 The main challenge was to meet the current requirements and parasitic reduction in
PREAMP. Also, shielding the diff. pair output nets.
My Role :
 Completely owned block and sub blocks (PREAMP, CPMPARATOR) from scratch.
 Matching of current mirror, diff. Pair, input pair,and resistive ladder. Floorplanning,
 Layout of top level block, sub block, and custom digital blocks. Routing.
 Layout Verifications like LVS/DRC were performed. Worked on integration on all blocks.

Block : CONSTANT GM BIAS

Description :
 It has a start-up circuit, current mirror.
 The main challenge is to take out different current values from different diode connected
device in current mirror.
My Role :
 Worked on constant gm bias block(sub-block of VCO) and worked on digital custom cells of
adcfrom scratch.
 Matching and Layout of current mirror chain.
 Floorplanning and routing of above blocks.
 Layout verifications like LVS/DRC were performed.

6. SerDes (STM 65 nm Technology)

Environment : Synopsys Custom Compiler, ICV LVS/DRC, Calibre LVS.

Block : MPLL_DIG
Description :
 It is a digital part of PLL. It has digital custom blocks.
 Main challenge is the area constraint with respect to top level floorplan and use of
minimum number of metal layers.
My Role :
 Worked on digital custom blocks from scratch.
 Floorplan and placement of sub blocks according to pin placement. Routing.
 Layout verifications like LVS/DRC were performed.

Block : DIFFERENT SUB-BLOCKS of VARIOUS IP’S

 It has various current mirrors, diff. pairs, input pairs from different IP of SerDes.
 The main challenge is to implement within less time with assurance of quality of layout.
My Role :
 Worked on preparing layout of current mirrors, diff. pairs, input pairs from scratch.
 Matching and Layout of current mirrors, diff. pair and input pair.
 Floorplaning, Placement of devices, Routing.
 Extractions were performed on different sub-blocks.

7. Thermal Sensor(ICF 10 nm Technology)

Environment : Cadence Virtuoso Layout Editor XL, ICV LVS/DRC.
Blocks : Digital Custom Cells
Description :
 It has different CMFB (common mode feedback circuit), mux.
 Main challenge was to do routing according to track pattern in minimum no. of metal
layers.
My Role :
 Worked on layout of digital blocks from scratch.
 Floorplan by coordinating with design, routing according to track pattern.
 LVS and DRC checks.

8. GPIO (ICF 22 nm Technology)

Environment : Cadence Virtuoso Layout Editor XL, ICV LVS/DRC.
Blocks : IO CELLS
Description : It has filler, corner, terminator, esdclamp cell.
My Role :
 Reshaped or modified the original IO cells to the given coordinates according to main pads
(n-vertical, e-horizontal).
 Modification has been done with respect to changes is metal lengths and unwanted cells.
 LVS and DRC checks
 LEF generation

9. OPAMP and BGR (SMIC 40nm Technology)

Environment : Cadence Virtuoso Layout Editor XL, Calibre LVS/DRC.
Description : Main challenge is the BJT matching and resistor matching.
My Role :
  Worked on layout of OPAMP, BJT and resistor from scratch.
 Matching of Current mirror, diff pair, BJT and resistors.
 Floorplan by coordinating with design, routing.
 LVS and DRC checks

ACADEMIC PERFORMANCE
M.Tech. in VLSI Design from VIT University, Vellore, TN secured 8.0 CGPA in 2014.
B.E. in Electronics & tele. from RTM Nagpur University secured First Class in 2011.

PERSONAL PROFILE
Date of Birth : 05th September 1989.
Nationality : Indian.
Languages : English, Marathi, Hindi.