MAHESH_KUMAR_YADAV_LAKUMAGARI _DF01243 [1.

5]
MOBILE : 9100870318
MAILID : maheshlakumagari@gmail.com
DOB : 10/09/1999
PIN CODE : 518385

Career Objective

Seeking for challenges in the field of Design for testability (DFT), which will make best use of
my skills and further polish my personality and career with an esteemed progressive
organization.

Professional Summary

▪ Performed Block Level Scan-Insertion and ATPG.

▪ Debugged SCAN & ATPG DRC violations.
▪ Generated patterns for stuck-at, at-speed fault models.
▪ Done Test coverage analysis and achieved the targeted coverage.
▪ Familiar with debugging of No-Timing and Timing (Min & Max) Simulation.
▪ Have theoretical knowledge on EDT, OCC, Wrapper Insertion and Test Point
Insertion.
▪ Hands on Industry Tools: Mentor Graphics (DFT Advisor, TestKompress, Questasim) and
Synopsys (DFT compiler, VCS).

Project Details

Project 1 DFT
Client K2 Media Inc
Period July 2022 to till date
Tools Used DFT Compiler, TestKompress, QuestaSim
My Responsibilities  Done Scan Insertion for 4 partitions.
 Synthesized the RTL of the design using dc_shell.
 Generated the ATPG test patterns for Stuck at and Transition
faults.
 Performed no timing simulation by using QuestaSim.

Project Description Flop count : ~25k to ~80k

Project 2 DFT

Client K2 Media Inc

Period Oct 2021 to June 2022
Tools Used DFT Compiler, TestKompress & VCS
My Responsibilities  Resolved Scan DRCs and fixing the violations and
implemented scan methodology for 4 partitions.
 Generated test patterns stuck-at & at speed modes.
 Done with test coverage improvement.
 Validated chain and stuck-at simulations for all patterns.
 Performed no-timing simulations and validate the patterns.
Project Description Flop count ~25k to ~60k

Academic Qualifications

Year of
Course Institution Percentage
passing
Rajeev Gandhi memorial college of
B. Tech (EEE) 2021 6.47 CGPA
Engineering & Technology
Diploma (EEE) Intell Engineering college 2018 63.9%
Excellent English medium High
SSC 2015 7.3 GPA
School