Jawaharlal Nehru Technological University, the Drivers & Power Systems, Telecom, Mechanical repeaters, operational amplifiers and
tional amplifiers and delivers deep
First Technological University of India, was and Civil sector. We do offer R & D consulting insights on characterization. established on 2nd October 1972 in Andhra Pradesh across technologies. Our niche services include – IC The program also caters to the needs of research with head quarterslocated in a historical city fabrication alliance, Post silicon validation and scholars pursuing their research in custom IC Hyderabad. The University is one of the premier more. We cater to wide range of customers in Design/ Analog circuit and Layout. This program Universities in India accredited by NAACwith „A‟ semiconductor, manufacturing, defense & aerospace also benefits practicing engineers to fine tune their Grade. After successful and proven levels of and academia. skill and work on analog circuit and layout design appreciated existence and stature spanning over 36 more effectively in their deliverables. years, JNTU has been divided into four different About the FDP/ Short Term Course: VLSI technology has gone through rapid strides in Key Learning Outcomes: universities by Govt. of Andhra Pradesh, through last few decades. Despite digital processing of At the end of the program you will be able to: Act No.30, Dt. 24th September, 2008. One of the signals, advent of digital architecture and rapid Analyze the performance specification requirements constituent colleges of the University “JNTUH growth of IC design technology, the basic and identify the suitable circuit topologies College of Engineering, Hyderabad” is regarded Characterize the PDK for device analog model abstraction layer for complex chipsets continuous to as a pioneer in shaping the excellence of some of the parameters be Analog components. Analog circuit & layout leading organizations of the industry, by churning Synthesize basic and OP-AMP amplifier circuit design continuous to get more and more complex out the finest professionals with a resolve to scale topologies due to ever increasing demand for power, area and greater heights in the technological scenario, every Design CMOS Amplifier circuits for given DC and AC cost effective solutions in digital and analog IC year. Other constituent college of JNTUH is located performance parameters design. Industry efforts are focused towards at Jagityal and 11 other academic units at Develop programmed spread sheets for amplifier design optimizing designs for better performance, area & automation Hyderabad campus. energy and other key factors. Industry is looking at Design and characterize a seven – pack CMOS competent manpower to address these challenges on Compensated OP-AMP at the schematic design entry The Department of Electronics & Communication an ongoing basis. Academia is the main source of level Engineering established in 1973, is instrumental in molding the careers of students and helping them to manpower to industry. Quality manpower from Derive layout constraints for the physical design of the campuses is one of the key expectations of industry. OP-AMP and carry out DRC and LVS become world-class professionals. The department Entuple believes in a philosophy of empowering Carry out the physical verification and parasitic is offering UG, PG, Research and Collaborative faculty champions to groom competent future extraction. Programmes with well experienced faculty and as Back Annotate and carry out Post Layout Simulation/ engineers of industry. The various learning activities well as established laboratories. Besides highly Characterization driven by Entuple are focused towards this qualified and experienced staff and well-equipped objective. Who should attend? laboratories, the Department has been awarded 8.1 points out of 10 by the State Board of Technical Practicing engineers in Analog circuit and layout design This Faculty Development Program (FDP) or Short Faculty involved in teaching Analog CMOS IC Design Education. Term Course (STC) program is designed to provide and Analog Mixed Signal design courses Entuple Technologies Pvt., Ltd.: deeper aspects of Analog Circuit Design layout Research scholars pursuing research in Analog circuit Entuple is a next generation solutions enabler in concepts. The program provides the industry ways and Layout, devicecharacterization and more. cutting edge technologies. Head Quartered at of working environment for participants. It UG/PG students aspiring to get started with concepts of Bangalore, India, Entuple delivers world class progressively builds the concepts with a kick start Analog circuit and layout foundation and planning for a products & solutions in Applied Electromagnetics, on functional blocks such as current mirrors, career in semiconductor industry. Semiconductor and System Design & Reliability, 1 Course Outline and Structure Small Signal AC Performance of CS and Differential Pair Lab 7: Design and Characterization of the CS Day 1: Fundamentals of Analog Signal Processing – amplifier for Small Signal DC and AC Performance Lab 8: Design and Characterization of Differential Pair for A Faculty Development Program/Short CMOS Amplifier Topologies and Performance Small Signal DC and AC Performance Review of the generic amplifier performance Day 5: Design and Performance Characterization of a 7 – Term Course on parameters – Gain, Power Dissipation, Frequency Response, (Noise – optional, time permitting) Pack OPAMP A Hands-on Tutorial for Schematic and Layout Design of a “Analog IC Design (AICD) - Circuit Synthesis of Basic Amplifier Circuit Topologies CMOS OP-AMP for the given Specifications and and Layout Design Large and Small Signal DC Performance Analysis and Characterization Methodologiesusing Cadence Design Design of Basic Amplifiers Single and Differential Ended Signaling – Concept Registration Fee: Flow” Illustration - What really is a commonmode signal? Faculty/Research Scholars: Rs. 10,000/- The Basic Ideal OP-AMP and its properties PG/UG students: Rs.7,500/- 03rd-07th July, 2017 Lab1: PDK Device Characterization for Analog Model Parameters Note: 1. DD/cash in favour of The Coordinator, AICD, Lab 2: Hands – on Tutorial on Design and Simulation JNTUH CEH, Hyderabad payable at Hyderabad. In collaboration with 2. Participants are advised to bring their personnel of a CS Amplifier for Large and Small Signal DC Laptops, if any. Future R&D guidance will be provided. performance Lab 3: Design and Simulation of the Bias Circuit for the Limited seats: Registration is on first come first CS amplifier: Hands – on Tutorial Day 2: Small Signal DC Design and Simulation of the serve basis. Selected participants will be informed Basic Differential Pair/ Analog Layout Design by mail by 1st July, 2017. Seats will be blocked based Bangalore Concepts on receipt of payment in advance. Interpreting the Design Specifications Design Methodology and Flow - Large Signal and Last date for registration: 30th June, 2017. Coordinator Small Signal DC Design Analog Layout Design Concepts – Importance of Travel/Accommodation Dr. M. Madhavi Latha Device Matching in Layouts; LDEs Participants are required to make their own Professor in ECE &Coordinator- Lab 4: Design and Performance Characterization of arrangements for travel, local conveyance and Center for Excellence in VLSI & Embedded CMOS Current Mirror (Schematic Design and accommodation. Systems Design Simulation) Lab 5: Layout Design of a CMOS Current Mirror Address for Correspondence Lab 6: DC Performance Characterization of the Basic CMOS Dr. M. Madhavi Latha Differential Amplifier (5 – Pack OP-AMP) Professor & Coordinator - CVED Day 3 – 4: Frequency Response and Compensation of Department of ECE, JNTUH CEH Amplifiers – Performance Analysis Cell: 9848506611, Email: mlmakkena@yahoo.com Effect of the Amplifier BW limitations on Analog Signal Processing – Illustration Review of Transfer Functions and Frequency Response Plots; Venue: CVED, 2nd Floor, ECE Department, JNTUH Department of FB concepts and Effect of FB on Frequency Response, Stability CEH, Time:10:00 AM to 5:00 PM Electronics & Communication Engineering and Compensation Registration form: Down Load from jntuhceh.ac.in JNTUH College of Engineering Gain – BW Enhancement Techniques – The CASCODE Stage or jntuh.ac.in website. Hyderabad-500 085, Telangana. 2 A Short Term Course on
“Analog IC Design- Circuit and Layout Design Methodologies
Using Cadence Tools” 3-7 July, 2017
Registration Form
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