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  • FB - PLC Program

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    itsaveryverymadworldd
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    This document provides a function block diagram with 3 sentences or less: The diagram shows the control logic for a system using Boolean logic gates including AND, OR, and NOT gates connected to sensors and solenoids controlling cylinders A, B, and C. Gates BAND_01 through BAND_07 and BOR_01 through BOR_02 are connected as inputs and outputs to control the extension and retraction of the cylinders based on the sensor signals and start and stop inputs. The diagram is part of a main program for a function block called TEST_FB on page 1 of 1.

    Original Description:

    Plc program

    Original Title

    FB - PLC program

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    This document provides a function block diagram with 3 sentences or less: The diagram shows the control logic for a system using Boolean logic gates including AND, OR, and NOT gates connected to sensors and solenoids controlling cylinders A, B, and C. Gates BAND_01 through BAND_07 and BOR_01 through BOR_02 are connected as inputs and outputs to control the extension and retraction of the cylinders based on the sensor signals and start and stop inputs. The diagram is part of a main program for a function block called TEST_FB on page 1 of 1.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    11 views1 page

    FB - PLC Program

    Uploaded by

    itsaveryverymadworldd
    This document provides a function block diagram with 3 sentences or less: The diagram shows the control logic for a system using Boolean logic gates including AND, OR, and NOT gates connected to sensors and solenoids controlling cylinders A, B, and C. Gates BAND_01 through BAND_07 and BOR_01 through BOR_02 are connected as inputs and outputs to control the extension and retraction of the cylinders based on the sensor signals and start and stop inputs. The diagram is part of a main program for a function block called TEST_FB on page 1 of 1.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 1

    FB - Function Block Diagram Page 1

    TEST_FB:MainTask:MainProgram
    1 of 1 total sheets in routine C:\Users\Jbaluswamy\OneDrive - Conestoga College\FBfinaldemowithmotor.ACD

    A B C D E F G H I
    BAND_01 BOR_02
    BAND ... BAND_02 0 BOR ...
    Cylinder_C_Ext_Sensor
    Boolean And BAND ... Boolean Or
    0 0 Boolean And 0 0 BAND_05
    StopPB In1 Out R2 In1 Out R2
    0 0 BAND ...
    1 In2 R1 R1 In1 Out Cylinder_A_Ext_Solenoid In2 1
    In3 In2 Boolean And
    0 BNOT_02 0
    Cylinder_C_Ret_Sensor In3 In1 Out Cylinder_C_Ret_Solenoid
    0 BOR_01 0 BNOT ...
    StartPB R3 In2
    BOR ... BNOT_01 Boolean Not
    0 Boolean Or BNOT ... 0
    R1 In Out
    0 Boolean Not
    In1 Out
    0 0
    In2 R2 In Out
    BAND_06
    BAND ...
    BAND_03 Boolean And
    2 2
    BAND ... 0
    In1 Out Cylinder_B_Ret_Solenoid
    Boolean And 0
    Cylinder_C_Ret_Sensor In2
    0
    In1 Out Cylinder_B_Ext_Solenoid
    0
    Cylinder_A_Ext_Sensor In2
    BAND_07
    BAND_04 BAND ...
    BAND ... Boolean And
    Boolean And 0
    In1 Out Cylinder_A_Ret_Solenoid
    0 0
    In1 Out Cylinder_C_Ext_Solenoid Cylinder_B_Ret_Sensor In2
    0
    3 Cylinder_B_Ext_Sensor In2 3

    BAND_08
    BAND ...

    Boolean And
    BNOT_03 0
    In1 Out R3
    BNOT ... 0
    Cylinder_A_Ret_Sensor In2
    Boolean Not CTUD_01
    0 CTUD ... BNOT_04
    In Out
    Count Up/Down BNOT ... TOFR_01 EQU_01
    0 Boolean Not TOFR ... EQU ...
    4 CUEnable ACC 4
    0 0 Tim er Off Delay with Reset Equal
    CDEnable DN In Out
    5 0 0
    5 PRE Tim erEnable ACC SourceA Dest MotorVFD:O.Stop
    0 15000
    Reset PRE TT MotorVFD:O.Start 15000 SourceB
    15000 0
    15000 Reset DN MotorVFD:O.Forward

    EQU_02
    EQU ... 6000
    6000 MotorVFD:O.FreqCommand
    Equal
    5 0
    5 5 SourceA Dest 5
    SourceB

    BNOT_05
    BNOT ...

    Boolean Not
    0
    In Out

    6 6
    A B C D E F G H I

    Logix Designer

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