Structure of Computer Systems – Using the StateCAD State Machine Editor 1

USING THE STATECAD STATE MACHINE EDITOR

This tutorial presents the main aspects of using the StateCAD state machine editor provided
with the Xilinx ISE design environment. StateCAD allows to specify state machines in graphical form,
as state diagrams. The tutorial also presents the use of the StateBench tool, which allows to verify the
behavior of state machines designed with the StateCAD editor. An example design is described using
the StateCAD and StateBench tools.

1. Overview
StateCAD is a module integrated into the Xilinx ISE design system, which allows to create
and edit finite state machines in graphical form. This module permits to define the states, the output
signals that should be asserted in each state (state actions), and the state transitions. The state actions
and state transitions can be specified by equations with a simple syntax. StateCAD also allows to add
common logic circuits to the state machines created, such as gates, multiplexers, adders, comparators,
flip-flops, shift registers, and counters.
StateCAD allows to validate the state diagrams before their behavioral simulation. Therefore,
the designer can discover indeterminate conditions, syntax errors and incomplete portions of state
diagrams early in the design cycle. After validating a diagram, it can be compiled into the equivalent
code written in a hardware description language (VHDL, Verilog, or ABEL). The generated code can
be used to simulate the state machine, to synthesize and implement the state machine, or to create a
symbol (macro) from the state machine, which can be placed into a schematic.
After creating and validating a state machine, its behavior can be verified with the StateBench
tool. This tool allows to create a testbench for the state machine under test, by specifying the input
signals of the state machine and the output signals that should be generated in each state. StateBench
uses the testbench that was created to simulate the behavior of the state machine, and signals the
differences between the results generated during the simulation and the expected results. After the
simulation, a testbench which contains timing constraints can be created. This testbench can be used to
verify the timing constraints of the design after synthesizing the state machine.

2. Design Example
The following sections describe the steps required to design a multiplier for two 4-bit
unsigned numbers using the shift-and-add multiplication method. Both the control unit of the
multiplier and the data processing part will be designed using the StateCAD editor.

2.1. Design Description

The block diagram of the multiplier is illustrated in Figure 1. The B register stores the multi-
plicand RX during the operation (bit 4 of this register is set to 0). At the beginning of the operation, the
multiplier RY is loaded into the Q register, and this register will contain the least significant bits
(LSBs) of the product at the end of the operation. The A register is an accumulator, which is initialized
to 0 at the beginning of the operation. This register stores the partial product during the operation and
will contain the most significant bits (MSBs) of the product at the end of the operation. The 5-bit ad-
der is used to repeatedly add the multiplicand in the B register to the partial product in the A register.
A 5-bit adder is used since a carry may be generated when adding the 4-bit multiplicand to the partial
product. The control unit contains a counter N, which is initialized to 4 at the beginning of the opera-
2 Structure of Computer Systems – Using the StateCAD State Machine Editor

tion and is decremented by 1 in each step of the multiplication. When the counter N reaches 0, the
multiply operation is completed. The START signal should be asserted to initiate the multiply opera-
tion. The TERM signal is asserted by the multiplier to indicate the end of the operation.

Figure 1. Block diagram of the multiplier using the shift-and-add multiplication method.

Before starting the multiply operation, the values of the multiplicand RX and the multiplier RY
are set. To start the operation, the START signal is asserted. By asserting this signal, the multiplier
performs the following initialization operations: loads the multiplicand RX into the B register, loads
the multiplier RY into the Q register, initializes the A register to 0, and initializes the counter N to 4. In
each step of the operation, the LSB of the multiplier (Q0) is tested, and if this bit is 1, the multiplicand
(stored in register B) is added to the partial product (stored in register A). Next, the A and Q registers
are shifted right by one position, and the LSB of the A register is transferred into the MSB of the Q
register. The counter N is decremented, and if it is not 0, the operation continues by testing the LSB of
the multiplier. At the end of the operation, the TERM signal is asserted, which indicates that the A and
Q registers contain the final product.

Figure 2. State diagram of the multiplier using the shift-and-add multiplication method.

The multiplier can be considered as a state machine, so that its operation may be described by
a state diagram. The state diagram of the multiplier is illustrated in Figure 2. This diagram contains 6
distinct states. State S0 is an idle state, in which the circuit waits for the assertion of the START signal
to begin the multiply operation. If the START signal becomes 1, the circuit transitions into state S1, in
which the initialization operations are performed. These operations can be described symbolically as
follows:
B ← RX; Q ← RY; A ← 0; N ← 4;
In state S2 the counter N is decremented. The decrement operation is performed before each
step of the multiply operation, and not after each step, as was described previously, in order to
simplify the state diagram. If bit Q0 is 1, the circuit transitions into state S3, in which the multiplicand
is added to the partial product:
A ← A + B;
 Structure of Computer Systems – Using the StateCAD State Machine Editor 3

From state S3 the circuit transitions unconditionally into state S4, in which the A and Q
registers are shifted right by one bit position. The circuit also transitions into state S4 from state S2, if
bit Q0 is 0. From state S4 the circuit transitions into state S2 if the counter N is not 0, or into state S5 if
the counter N is 0. In state S5 the TERM signal is asserted, which indicates the end of the operation,
after which the circuit transitions into the idle state S0.

2.2. Creating the Project

To create a new project, launch the Xilinx ISE 8.1 program, and then perform the following
steps:
1. In the Project Navigator window, select File → New Project. The New Project Wizard –
Create New Project dialog box will open.
2. In the Project Location field, select the folder in which the project will be created (this should
be a subdirectory of the D:\Student\ directory).
3. In the Project Name field, enter the name of the project, for instance, lab_stcad.
4. Select the Next button. The New Project Wizard – Device Properties dialog box will open.
5. Verify the correct settings in the Family, Device, and Package fields. For the Pegasus board,
these settings should be Spartan2, XC2S50, and PQ208, respectively. For the Spartan-3
board, the settings should be Spartan3, XC3S200 (or XC3S400), and FT256, respectively.
6. Select the Next button. The New Project Wizard – Create New Source dialog box will open.
7. Select the Next button. The New Project Wizard – Add Existing Sources dialog box will open.
8. Select again the Next button, and in the New Project Wizard – Project Summary window
select the Finish button to create the project.

2.3. Opening StateCAD

To open the StateCAD editor and to create a file for the state diagram, perform the following
steps:
1. In the Project Navigator window, select Project → New Source.
2. In the New Source Wizard – Select Source Type dialog box, select the State Diagram option.
3. In the File name field, enter the name of the file for the state diagram, for instance, mul_add.
4. Select the Next button.
5. In the New Source Wizard – Summary window, click the Finish button.
StateCAD will open in a new window.

2.4. Creating the State Machine

To create the state machine, the State Machine Wizard will be used.

1. Select the Draw State Machines button . The State Machine Wizard will open (Figure
3).
2. In the Shape of state machine field, select the Row option to place the state symbols in a row.
3. In the Number of states field, keep the default setting (5) for the number of states of the
machine. Later on, an additional state will be added.
4. Click the Next button. The Reset The State Machine dialog box will open.
4 Structure of Computer Systems – Using the StateCAD State Machine Editor

5. In the Reset Mode field, select the Asynchronous option to generate an asynchronous reset
logic for the state machine.

Figure 3. State Machine Wizard dialog box.

6. Click the Next button. The Setup Transitions dialog box will open (Figure 4).

Figure 4. Setup Transitions dialog box.

7. In the Add Transitions field, select the types of transitions that will be present in the state
machine diagram. By default, only the Next option will be selected. In this way, the diagram
will contain only transitions from a state to its next state. Retain this setting.
8. Click the Finish button. In the StateCAD window a green rectangle will display, which shows
the borders of the diagram.
9. Move the rectangle in the center part of the window, then click the left mouse button. The
state machine diagram with the form illustrated in Figure 5 will display.

Figure 5. The initial form of the state diagram created with the State Machine Wizard.
 Structure of Computer Systems – Using the StateCAD State Machine Editor 5

2.5. Adding a New State

To add a new state to the state diagram created, perform the following steps:

1. Select the Add State button , located on the left part of the screen.
2. Position the mouse pointer above the STATE2 symbol, and then click the left mouse button.
The symbol of the new state will be placed on the diagram. StateCAD will assign the name
STATE5 to the new state.
3. Click the Pointer button .

2.6. Editing the States

Next, the names of the states will be modified, so that the names will suggest the state
functions, and the output signals which should be asserted in each state will be specified.
1. Double-click on the STATE0 symbol. The Edit State dialog box displays (Figure 6).

Figure 6. Edit State dialog box.

2. In the State Name field, enter the new name of the state, idle, and then click the OK button.
3. Double-click on the STATE1 symbol. In the State Name field, type the name init. In the
Outputs field, enter the following equations to initialize the registers and the TERM signal:
B=0:RX;Q=RY;
A=0;N=4;
TERM='0';
Click the OK button.
4. Double-click on the STATE2 symbol. In the State Name field, type the name decrem_N and
then click the OK button.
5. Double-click on the STATE3 symbol. In the State Name field, type the name shift_AQ and
then click the OK button.
6. Double-click on the STATE4 symbol. In the State Name field, enter the name termin. In the
Outputs field, enter the value of the TERM signal:
TERM='1';
Click the OK button.
7. Double-click on the STATE5 symbol (the state that has been added separately). In the State
Name field, type the name add_B and then click the OK button.
6 Structure of Computer Systems – Using the StateCAD State Machine Editor

2.7. Adding Additional Transitions

To complete the diagram with the transitions that have not been generated automatically,
perform the following operations:

1. Select the Add Transition button , located on the left part of the screen.
2. Select the decrem_N state by clicking the state symbol, and then click again inside the state
symbol, near the upper edge. A red square appears on the edge of the state symbol, and
another red square follows the cursor movement.
3. Move the cursor above the add_B state. A red square appears on the edge of the state symbol
and a line between the decrem_N and add_B states. Click the left mouse button to fix the
position of the endpoint. If a transition line is not added correctly, it can be deleted with the
Delete key, and then can be added again.
4. In the same way, add a transition from the add_B state to the shift_AQ state.
5. Proceed similarly to add a transition from the shift_AQ state to the decrem_N state. To
transform the transition line to a curved line, click on one of the two control points inside the
line (the points shown by squares with red edges), then reposition the point by moving the
cursor downward, maintaining the mouse button pressed. Proceed similarly with the second
control point.
6. To add a loop-back transition for the idle state, double-click inside the symbol of this state,
near the upper edge. StateCAD adds the loop-back transition line (which starts and ends in the
idle state), and adds the @ELSE condition to this transition.
7. Click the Pointer button to finish the transition mode.

2.8. Adding Transition Conditions

A transition condition determines the execution of the corresponding transition when the
condition becomes true. To add conditions for transitions, perform the following operations:
1. Double-click on the transition line from the idle state to the init state. The Edit Condition
dialog box displays (Figure 7). In the Condition field, type the condition START, and then
click the OK button. Place the red rectangle above the transition line.

Figure 7. Edit Condition dialog box.

2. Double-click on the transition line from the decrem_N state to the add_B state. In the
Condition field, type the condition Q0=1, and then click the OK button. Place the red
rectangle to the left of the transition line.
 Structure of Computer Systems – Using the StateCAD State Machine Editor 7

3. Double-click on the transition line from the decrem_N state to the shift_AQ state. In the
Condition field, type the condition Q0=0, and then click the OK button. Place the red
rectangle above the transition line.
4. Double-click on the transition line from the shift_AQ state to the decrem_N state. In the
Condition field, type the condition N/=0 and then click the OK button. Place the red rectangle
below the transition line.
5. Double-click on the transition line from the shift_AQ state to the termin state. In the
Condition field, type the condition N=0 and then click the OK button. Place the red rectangle
above the transition line.
After executing these operations, the state diagram will look like in Figure 8. Save the state
diagram file by clicking the Save File button.

Figure 8. The form of the state diagram after adding the transition conditions.

2.9. Adding Logic Circuits

To execute the basic operations from which the multiply operation consists of, the appropriate
logic circuits have to be added. These circuits will be added automatically by the StateCAD editor if
the user specifies the equations of the output signals that should be generated in the corresponding
states. For the designed multiplier, the following logic circuits will be added: a counter N, which is
decremented in each step of the operation; a 5-bit adder, used for adding the multiplicand in the B
register to the partial product stored in the A register; the A and Q registers, which are shifted right
with one position in each step of the operation.
To add the counter N, perform the following operations:
1. Double-click the symbol of the decrem_N state. The Edit State dialog box will open.
2. Click the Output Wizard button. The Logic Wizard window will open (Figure 9).

Figure 9. Logic Wizard window.

8 Structure of Computer Systems – Using the StateCAD State Machine Editor

3. From the list displayed in the upper left corner of the window, select the Count Down
component.
4. In the COUNT field, enter N as the name for the output signal of the counter.
5. In the Data path width field, select 2 as the size of the vector which represents the output
signal of the counter.
6. Verify that the Registered option is checked, so that the output signal will be sequential.
7. Click the OK button. The Logic Wizard generates the logic equation of the counter and defines
the vector which represents its output signal. In the Outputs field of the Edit State window the
equation of the counter will appear: N = N-1;.
8. Click the OK button. The equation of the counter will appear below the name of the
decrem_N state. In the state diagram window, the symbol of the vector N[1:0] will appear,
indicating that this vector has been defined.

To add the adder circuit, perform the following steps:

1. Double-click the symbol of the add_B state. The Edit State dialog box will open.
2. Click the Output Wizard button. The Logic Wizard window will open.
3. From the list displayed, select the Adder component.
4. Enter A in the A field, and B in the B field. These are the two operands that will be added.
5. Enter A in the DEST field as destination of the addition operation.
6. In the Data path width field, select the value 5 as the size of the vectors to be added.
7. Click the OK button. The Logic Wizard generates the logic equation of the adder and defines
the vectors that will be added. In the Outputs field of the Edit State window the equation of the
adder will appear: A = (A+B);.
8. Click the OK button. The equation of the adder will appear below the name of the add_B
state. In the state diagram window, the symbols of the vectors A[4:0] and B[4:0] will appear,
indicating that these vectors have been defined.

To add the A and Q shift registers, perform the following steps:

1. Double-click the symbol of the shift_AQ state. The Edit State dialog box will open.
2. Click the Output Wizard button. The Logic Wizard window will open.
3. From the list displayed, select the Shift Right component.
4. Enter A4 in the DIN field, and A in the DOUT field.
5. In the Data path width field, keep 5 as the size of the shift register.
6. Click the OK button. In the Outputs field of the Edit State window the equation of the shift
register appears: A = A4:A4..A1;.
7. Click the Output Wizard button. The Logic Wizard window will open again.
8. Select the Shift Right component.
9. Enter A0 in the DIN field, and Q in the DOUT field.
10. In the Data path width field, select 4 as the size of the shift register.
11. Click the OK button. In the Outputs field of the Edit State window, below the equation of the
A shift register, the equation of the Q shift register appears: Q = A0:Q3..Q1;.
 Structure of Computer Systems – Using the StateCAD State Machine Editor 9

12. Click the OK button. The equations of the shift register will appear below the name of state
shift_AQ. In the state diagram window, the symbol of the vector Q[3:0] will appear, indicat-
ing that this vector has been defined.

Save the state diagram file by clicking the Save File button.

2.10. Adding New Vectors

StateCAD automatically defines the vectors that have been used in the equations of logic
circuits added to generate the output signals. The size of these vectors is known by selecting the value
of the Data path width field in the Logic Wizard window. The vector variables which do not appear in
the equations of the logic circuits added have to be defined explicitly by the designer, specifying their
size. Otherwise, these variables will be considered bit variables.
For the multiplier circuit, the vector variables for which the size has not been specified are RX
and RY. To define these variables as vectors, perform the following operations:
1. Click the Add Vector button , located on the left part of the screen.
2. Move the cursor above a free area below the state diagram and click the left mouse button.
The symbol of a vector VAR0[7:0] will appear, with the size 8 (Figure 10).

Figure 10. The symbol of a vector with the default name and size.

3. Place a second vector to the right of the first. The symbol of a vector VAR1[7:0] will appear.
4. Click the Pointer button to finish the vector mode.
5. To change the name and size of the vector VAR0, double-click its symbol. The Edit Vector
dialog window displays (Figure 11).

Figure 11. Edit Vector dialog window.

6. In the Name field, change the name of the vector to RX, and in the Range field, change the
range of bits to 3:0. Then click the OK button. A window may display indicating that the RX
variable is already used. In that case, click the Yes button to delete the existing variable RX
and to rename the vector to RX.
7. Proceed similarly to change the name of the VAR1 vector to RY and the range of bits to 3:0.

2.11. Viewing the Configuration Options

Next, the default configuration options that will be used when compiling the state machine
will be displayed, and one of these options will be changed.
1. Select Options → Configuration to open the Configuration dialog window.
10 Structure of Computer Systems – Using the StateCAD State Machine Editor

2. In the Options section of this window, enable the Retain Output Values option, by which the
output signals that are not specified explicitly in a state will retain their values from the pre-
ceding assignment.
3. The State Assignment section shows the state assignment method that will be used. The option
selected by default is One Hot. You may keep this option, or you may select the Enumerated
option.
4. Close the window by clicking the OK button.

2.12. Compiling the State Diagram and Correcting the Errors

To compile the state diagram, click the Generate HDL button . The View Error window
will open, displaying an error message. The message displayed indicates that the value 4 assigned to
vector N is greater than the range of the vector values. On the state diagram, the state in which the
assignment is made will be highlighted; this state is init. Close the View Error window by clicking the
Close button.
To correct this error and recompile the state diagram, perform the following steps:
1. Double-click the symbol of vector N. The Edit Vector dialog window will open.
2. In the Range field, change the range of the vector from 1:0 to 2:0. Consequently, the counter
N will have a size of 3 bits.
3. Click the OK button. The symbol of vector N will show the new range.
4. Compile the state diagram by clicking the Generate HDL button. A new error will be
displayed in the View Error window, indicating an illegal comparison Q0 = 1 or Q0 = 0. The
value used in a comparison expression should be a Boolean constant or variable. The
condition in which the illegal comparison appears and the corresponding transition are
highlighted in red on the state diagram. Close the View Error window.
5. Double-click the condition Q0 = 1. The Edit Condition dialog window will open.
6. In the Condition field, correct the existing condition Q0 = 1 to Q0 = '1', and then click the OK
button.
7. Proceed similarly to change the condition Q0 = 0 to Q0 = '0'.
8. Save the state diagram by clicking the Save File button.
9. Compile again the state diagram by clicking the Generate HDL button.
10. If the Delete Unused Variables displays, click the Delete button to delete the unused variables.
11. The Optimize Port I/O dialog window displays. In this window, the user may select the signals
that will become nodes (internal signals) and those that will become I/O ports. Internal signals
allow to perform some optimizations. Click on the name of the A, Q, and TERM signals to
delete the X marker before their names (Figure 12). Therefore, the signals A, Q, and TERM
will become I/O ports, while the signals B and N will become nodes.
12. Click the Optimize button. The Results window displays, indicating a compilations with no
errors. Several statistics are also displayed about the state machine that was generated and the
operations performed during the compilation.
13. Close the Results window. The StateCAD HDL Browser window will display, showing the
VHDL file generated by the compilation of the state machine. Browse through the generated
code, then close this window.
 Structure of Computer Systems – Using the StateCAD State Machine Editor 11

Figure 12. Optimize Port I/O dialog window for selecting signals that will become nodes.

2.13. Behavioral Verification with StateBench

To verify the operation of the multiplier, the StateBench program will be used. After
launching this program, the Verify Behavior command will be used first, and then the Cycle command.
For the behavioral verification, perform the following steps:

1. Launch the StateBench program by selecting the StateBench button . In the bottom half
of the screen the StateBench window will be displayed (Figure 13), while the state diagram is
displayed in the upper half of the screen.

Figure 13. StateBench window.

2. In the StateBench window click the Verify Behavior button . The Verify Behavior dialog
window will open.
3. In the Set initial conditions section set the initial values of the signals. First, set the value of
the multiplicand in register RX by double-clicking the name of the RX signal. The Assign
Value dialog box will open. Enter the value 6 in this box, and then click the OK button.
Proceed similarly to set the value of the multiplier in the RY register to 5. Then double-click
the name of the START signal to set this signal to logical 1.
12 Structure of Computer Systems – Using the StateCAD State Machine Editor

4. In the Choose the target state section select the decrem_N state. The simulation will be
performed until the state machine enters this state.
5. Click the Go button. The StateBench program will perform the simulation with the initial
values specified for the signals until the decrem_N state will be reached. The states through
which the state machine passes are shown on the state diagram in green, and the target state is
shown in yellow. In the StateBench window the signal waveforms are traced in clock cycles 0,
1, and 2. Then the Reached Target State dialog window displays. This window shows that the
specified state has been reached, and allows to select another target state or to stop the
simulation. Click the No button to close the window and to stop the simulation with the Verify
Behavior command.

6. Click the Signal Editor button to open the Signal Editor dialog window. In the List in
simulation section select the Q signal, and then click the Up button twice so that the Q signal
will be displayed below the A signal in the waveform window. In this way, the result of the
multiplication, formed in the A and Q registers, is visible in the waveform window. Click the
OK button, and in the Signal Editor window click the No button.

7. Continue the simulation with the Cycle command, activated by clicking the Cycle
button. With this command, the execution will be simulated for a clock cycle. Continue the
simulation with this command until the state machine reaches the termin state.
8. Verify the values of the A and Q signals (registers) in the termin state. The A register contains
the value 1, and the Q register contains the value 14 (in decimal). Since the A register contains
the most significant part of the product, and the Q register contains the least significant part,
the value of the product is 1×16 + 14 = 30. This result is correct (6×5 = 30).
9. Next, modify the initial values of the RX and RY registers in order to verify the operation of
the multiplier for other values of the multiplicand and the multiplier. To do this, double-click
the value 06 of the RX signal on the timing diagram, and in the Assign Value dialog box enter
the value 15 and then click the OK button. A dialog window displays; select the No button in
this window to modify the value of the signal in all clock cycles. Proceed similarly to modify
the value of the RY signal from 05 to 07.
10. Enter the expected values (the values considered correct) of the A and Q signals at the end of
the operation (in the termin state), in order to compare these values to the values obtained
during the simulation. The expected product is 15×7 = 105, which can be written as 6×16 + 9.
Therefore, the expected value of the A signal is 6, and the expected value of the Q signal is 9.
To set these values, double-click the waveform of the A signal in the termin state. The
Assertions dialog window will open. Select the Add option to add the value on the diagram,
and then click the OK button. The Assign Value dialog box will open; enter the value 6 in this
box, and then click the OK button. The value entered will be highlighted in red on the timing
diagram. Proceed similarly to enter the expected value of the Q signal (the value 9).
11. Next, rerun the simulation with the new values of the signals. For this operation, click the Run

Test Bench button . A dialog window displays; select the Yes button in this window to
rerun the current simulation with the modified values of the signals. StateBench will rerun the
simulation until the termin state, checking the values of the A and Q signals. A warning
message will be displayed, indicating that differences have been detected between the values
of the signals (“Warning: Failing assertions found...”). Close the window of the warning
message. The area in which differences have been detected between the values of the signals is
highlighted on the timing diagram (Figure 14). Click on the timing diagram in the highlighted
area and notice that the incorrect value (indicated in red) is the value of the A signal.
 Structure of Computer Systems – Using the StateCAD State Machine Editor 13

Figure 14. Timing diagram showing differences between the expected values of the signals and the values
obtained during simulation.

2.14. Detecting and Correcting the Error

To detect the error, the Find Event command will be used. When this command is executed,
the StateBench program steps through the timing diagram and allows to stop in a given state, at a
given simulation time, when differences are detected between the expected values of the signals and
the values obtained at simulation, or when an expression becomes true. When a specified condition is
detected, StateBench allows to identify the driving source of the signal and to edit it directly on the
state diagram.
To detect the error, perform the following operations:

1. Execute the Find Event command by clicking the Find Event button . The Find Event
dialog window will open.
2. In this window, select the Find driver for output option. In the adjacent box select the A signal
for which the difference has been detected (this signal may be selected automatically). Click
the Find Next button. The Find dialog window displays, which shows that the A signal is set in
the shift_AQ state. Select the Yes button to edit this state on the state diagram.
3. In the Edit State window verify the equation of the A shift register: A = A4:A4..A1. This
equation shows that, when the register is shifted to the right, the most significant bit is not
changed. Normally, when an unsigned number is shifted to the right, a bit of 0 should be en-
tered into the most significant position.
4. Correct the equation of the shift register to: A = 0:A4..A1. Click the OK button.
5. The StateBench program will rerun the current simulation automatically, verifying the signal
values. A message will be displayed indicating that the tests have been passed successfully
(“All assertions pass.”). Close the window of this message. Notice that the expected values of
signals are displayed in green.
6. Delete the expected values of the signals with the Options → Clear Assertions command. En-
ter other values for the RX and RY registers, set the expected values of signals A and Q, and re-
run the simulation.

7. Save the testbench by clicking the Save Test Bench button . The Save Test Bench/ Re-
gression dialog window will open. In this window, retain the default file names and select the
Save button. The testbench generated in VHDL will be displayed in the StateCAD HDL
Browser window. Browse through the generated code and then close this window.
8. Close the window of the StateBench program. In the window of the StateCAD program, save
the file of the state diagram. Recompile the state diagram, and then close the Results window
and the window of the StateCAD program.

3. Applications
3.1. Perform the steps described in Section 2 to design and simulate the multiplier using the
shift-and-add method.
14 Structure of Computer Systems – Using the StateCAD State Machine Editor

3.2. Implement the multiplier on the Pegasus or Spartan-3 board. Perform the following opera-
tions:
1. Add to the project created for Application 3.1 the VHDL file generated by the StateCAD pro-
gram from the state diagram of the multiplier.
2. Add to the project the file display.vhd, containing the display module that controls the
multiplexed seven-segment displays. This file is available on the laboratory web page, in the
stcad.zip archive.
3. Create a VHDL file for a decoder of the seven-segment display. You may use the decoder cre-
ated for the implementation of the FIFO memory. The decoder’s module, hex2sseg, has as in-
put the code of a hexadecimal digit (hex) and as output the vector to drive the 7 segments of
the display (sseg). The display is a common anode display, so that in order to turn on a seg-
ment a logical 0 signal should be applied to that segment.
4. Create a VHDL file for the main module. This module has the same inputs as the multiplier
module created with the StateCAD program: CLK, RESET, START, RX, and RY. The outputs
of the main module are the TERM signal and the signals that drive the four seven-segment dis-
plays, sseg and an. In this module, define as components the multiplier and the display module
that controls the seven-segment displays. Then, instantiate these components, connecting to
the data inputs of the display module the following signals:
• Bits 15..12: RX;
• Bits 11..8: RY;
• Bits 7..4: the output of register A (bits 3..0);
• Bits 3..0: the output of register Q.
5. Add to the project the constraints file to specify the assignment of signals to the pins of FPGA
chip. The constraints files for the Pegasus and Spartan-3 boards are available on the laboratory
web page, in the stcad.zip archive. For the Pegasus board, use the file stcad_pegasus.ucf,
while for the Spartan-3 board use the file stcad_spartan3.ucf. These constraints files specify
the use of the following resources on the development boards for the input and output signals:
• RESET: button BTN1;
• START: button BTN0;
• RX: switches SW7..SW4;
• RY: switches SW3..SW0;
• TERM: LED LD0.
6. Compile each module and correct the possible syntactic errors.
7. Specify the use of the JTAG clock for programming the device. To perform this, in the proc-
esses window right click on the Generate Programming File line, and then select the Proper-
ties option. In the Process Properties window select Startup Options, and for the FPGA Start-
Up Clock choose the JTAG Clock option.
8. Perform the synthesis and implementation of the design.
9. Generate the configuration file (.bit) for the FPGA device.
10. Connect the development board to the computer through either a parallel or an USB pro-
gramming cable, and then power the Pegasus board with a voltage of 3.3 V or the Spartan-3
board with a voltage of 5 V.
11. If you are using a parallel programming cable, configure the FPGA device with the iMPACT
tool from the Xilinx ISE design environment. If you are using an USB programming cable,
configure the device with the Digilent ExPort program (Start → All Programs → Digilent →
Adept → ExPort).
 Structure of Computer Systems – Using the StateCAD State Machine Editor 15

12. Verify the operation of the multiplier by checking the results generated by the circuit for sev-
eral numbers applied to its inputs.

3.3. Perform the steps described in Section 2 to design a multiplier for two signed numbers
using Booth’s technique. The numbers are represented in 2’s complement on four bits each, including
the sign bit. First, draw the state diagram of the circuit, and then perform the same steps as in the de-
sign example described in the tutorial.