8085 Microprocessor and Its Applications 22h 2.7 DATA TRANSFER INSTRUCTIONS 4. MOVRd, Rs (Rd) — (Rs) The content of source register (Rs) is copied to the destination register (Ra). The registers Rd and Rs can be any one ofthe ‘gonerel purpose registers A, B, C, D, E, H or L. No flags are affected. Example: MOV B,C (8) (0) The content of C-register is moved to the B-register Before execution ‘After execution B c B c c2 E4 E4 E4 One byte instruction One machine cyclo : Opcode fetch - 4T Register addressing Total number of instructions = 49 MOV A, A MOV B, A MOV D, A MOV H, A MOV A, B MOV B, B MOV D, B MOV H, B MOV A, C Mov B,C MOV DC MOV H, MOV A, D MOV B, D MOV D, D MOV H, D MOV A, E MOV B, E MOV D, E MOV H, E MOV A, H MOV B, H MOV D, H MOV H, H MOV A, L MOV B, L MOV D, L MOV H, L MOV C, A MOVE, A MOV L, A MOV C, B MOVE, B MOV L, B MOV Cc, C MOV E, C MOV L, C MOV C, D MOV E, D Mov L, D MOV C, E MOVE, E MOV L, E MOV C,H MOVE, H MOV L, H MOV C, L MOVE, L MOV L, L 2 MOV Rd, M (Rd) < (M) or (Rd) <~ ((HL)) The content of memory (M) addressed by the HL pair is moved to the destination register (Rd). The register Rd can be any one of the general purpose registers A, 8, C, D, E, H or L, No flags are affected. Example: MOV A, M (A) << (M) or (A) < (CHL) The content of memory addressed by HL pair is moved to the A-register. Before execution After execution A H L Memory A L Memory co 5A | 54] [co] [A Tlcosa | C2 I 12 |cosa 35 |cosB Li | Fas Joos Two machine cycles: Opcode fetch - 4T Memory read - 3T 17 One byte instruction Register indirect addressing ‘Total number of instructions = 7 Mova,M —MovB,M MOVG.M MOVD,M MOVE,M MOVH,M MOVL, MChapter 2 Instruction Set oy, ((HL)) = (Rs) 2.22 by HL pat. Tho register Rs can bo on, ng (mye (Rs) OF the memory location addressed Fl MOV M, Rs i eee ffocted. The contont of source register (Rs) ys aro al oth grt pase egies BCD LNT ae @) Trample: MOV, B wee ot tho HL pai sxample > J iddrossed by the to is moved to memory localion a fant of B-rogistr smo ‘Attor oxecutlon The cont Before oxecutlon [2] [ee |c0s0 15 |c251 Two machine cycles: Opcode fetch - 4T ‘One byte instruction ° Register indirect addressing Memory write = Total number of instructions = 7 MOVMA MOVMB MOVM,C MOVM,D MOVM,E — MOVM,H, | MOVM,L (Rd) <— dB 4. MVIRG, dB The B-bit date (d8) given in the instruction is moved to the destination register (Rd). The register Rd can be any one othe general purpose registers A, B, C, D, E, H or L. No flags are affected. ‘Example : MVID,09H (0) <- 08, ‘The 6-bit data 09, given in the instruction is moved to the D-register Before execution After execution D D C2 09 Two byte instruction Two machine cycles: Opcode fetch - 4T Immediate addressing Memory road - 3T 77 Total number of instructions = 7 MVIA,d8 MVIB, dB MVIC,d8—MVID,d8 MIE, dB MVI H, d8 MVLL, d8 os (Med or (HL) a Example: MVIM, ETH (W) <7, or (HL = la )) <- E7, 8-bit data E7,, given in the instruction is moved to the memory location 2 Before execution Ai a ter execution Memory Memor H ee fea if H L [=] ea] [22] axe [2] E7 | 2050 3A | 205D se 3A | 205D Cee8085 Microprocessor and Its Applications 2.23 Two byte instruction Register indirect addressing or Immediate addressing Three machine cycles : Opcode fetch - 4T Memory read - 3T Memory write -_3T 107. Total number of instructions = 1 6. LDA addrié (Aye (M) or (A) (addrt6) The content of the memory location whose address is given inthe instruction, is moved toaccumulator. No flags are affected. ne ne ee Example LDA 205DH (A) < (2080,) The content of the memory location 2050, is moved to the A-ragister. Before execution After execution ‘e rd A Memory ce 15 _|205D 15 15 |205D TF |2056 7F [205 Three byte instruction Four machine cycles : Opcode fetch - 4T Direct addressing Memory read - 3T Memory read. - 3T Memory read - aT 13 Total numberof instructions = 1 7 LHLD addrté y<() (L) < (addrt6) (H)<— (M) OF (HW) & (addri6 + 01) The content of the memory location whose address is given in the instruction, is moved to the L-register. The content of the ‘next memory location is moved to the H-register No flags are affected. [Example : LHLD 1050H (<(10650,) (H) < (1051,) The content of the memory location 1050, is moved to the L-register The content of the memory location 1051, is moved to the H-register Before execution After execution | 1 Memory Ho xAL: Memory [os] [2 6A {1050 GA _|1050 3D |1051 09 |1052 3D |1051 09 fios2 Three byte instruction Fiye machine cycles: Opcade fetch - 4 Direct addressing Memory read - 3T Memory read - ST Memory read - ST Memory read ~ ST TT Total number of instructions = 4Chapter 2_ Instruction Set OF gy. | 2,24 Lx rp, d16 (op) at en . is i ister pair can be BC, DE, Hi Te tebit data given inthe instruction i moved to theregister pair (p)_ The register P Lor sp : i, 1050H (L) = 50, Example: LXIH, Oa rhe 16-bit date 1050, given inthe instruction is moved to the HL register pat. Before execution After execution H= le H L ew fio] [Be (some arbitrary value) Three byte instruction Three machine cycles : Opcode fetch - 47 Immediate addressing Memory read - ST Memory read -_3T in Total number of instructions = 4 LXL_B, d16 LXL_D, 416 Lx H,dt6 LX SP, d16 9, LDAX rp (A) << (M) or — (A) (1) ‘The content of the memory addressed by theregister pair (pis moved tothe accumulator. (The ccontent ofthe register par is the memory address). The register par can be either BC or DE. ‘Example: LDAX B (A) << (M) or (A) < ((8C)) ‘The content of the memory localion addressed by the BC pair is moved to the A-register Bofore execution ‘After execution Memory Memo fe aBr 3G A B C * 2] [20] [5A] [1 }205a GE] [20] DA} {1£ J205a 3C |205B fe [| 3c | 2058 One byte instruction Two machine cycles: Opcode fetch - 4T Register indirect addressing Memory read - ST ia Total number of instructions = 2 LDAX B LDAX D 0, 10, STA adarié ( (H) The conlent of the HL pair is exchanged withthe DE pait No flags are affected. Example :XCHG Eo) and (0) (H) ‘The content of the E-register is exchanged with the L-register and the content of the D-register is exchanged with the Hep Before execution After execution | | D £ H L D E H L =) [7] Gs] fs) Ps] fo] Ba _ One byte instruction ‘One machine cycle: Opcode fetch - 4T Implied addressing Total numberof instructions = 4 15 XTHL (HL) <> (M)— or (HL) <> ((SP)) ‘ The content ofthe top of stack is exchanged withthe HLpait. Stack i iemory ee pair. Stack is a portion of m (RAM memory). tho Stack Pointer (SP) isthe ediess ofthe top of the stack. No flags arafeted, f | ae . XTHL (L) <> ((SP)) and (H) <> ((SP) + 01) otter lent of memory addressed by the stack pointers exchanged with the L-reister and the cote ‘memory location is exchanged with the H-register " pl Before execution ‘After execution Stack SP_ HL Memory =e pele) SP_H_ L__ Memory io 15 |2000<~Top of Stack 18 | _sFo4 200010" 67 [2001 AD |2002 ee ‘AD |2002 [02 |2003 D2 |20033085 Microprocessor and Its Applications a One byte instruction Five machine cycles: 0; ‘ Implied addressing y6 )pcode fetch - AT Memory read - 37 Memory read - 3T Memory write - 3T Memory write - 3T ‘6T Total number of instructions = 1 — fee (SP) <(8P)-1 (BP) | B xx | 2052) >| = 2052 a ra" 2 43 | 2053 a Top of stack >| 43 | ane 7 Pot eac ode 3 Jas oe fChapter 2_ fnstruction S¢ et OF tay, | i 2.28 (SP) (sP)+4 (SP) (sp) < (SP) +1 moved to the register pail. ‘After execution ofthis instruction the content o The register pais can be BC, DE. HHLand PSW. Notas ae aft tg a * 47. POP rp (p< (SP) ‘Te content of op of stack memory iS Pointer (SP) willbe 02 arate than the ear valu fprgram Selus Word): AccurutorandFe0 register ere 10 register isa low order register) The pop instruction is executed as folOWS: (9 The content ofthe memory addressed by te SPis moved fo the low order. register {iy Te content of th SP is inrerentd by one. {i The content of the memory earessed by the SPis moved tothe high order register {yy The content ofthe SPs incremented by one- One byte instruction Three machine cycles: Opcode fetch - 4T Register indirect addressing Memory read - ST Memory read -_3T 107 ether called PSW. The accumulator is a high order register ang. Total number of instructions = 4 POPPSW poPB = POPD.-—SsPOPH Example: POPD €) <(P) (SP) < (SP) +01 0) (SP) (SP) < (SP) +01 () The content ofthe memory addressed by the SPis moved tothe E-regster (The content ofthe SP i incremented by one. (ii) The content of the memory addressed bj y the SPs moved to the D-register (v)_The content ofthe SP is incremented by one. . Before execution After executi xecution ‘Stack Memory ‘Stack Memory D E SP OFF D E 2] Ga) Cony foclemtEe| Ce] Ge] Gee) fine OFFF 1000 OFFF. Top of stack 1000 5E 1001 E2 | 1001 1002 FE 1008 Top of stack} CO | 1002 1F | 1003. (A)e (addr) The content of the port is moved to the Aegis Th tit pr cess wegen nheinstucton, No fe 28 stack 3[8] #3] Occupied stack 18, IN addr ‘Two byte instruction Wks elreitg Three machine cycles: Opcode fetch - 47 Memory read - ST lOread +a. 107 Total number of instructions = 1{8085 Microprocessor and Its Applications 2.29 49, OUT addrB {addr8) <— (A) The content of theA-registeris moved tothe port. The 8-bt port address willbe given in the instruction, No flags are affected. Two bye instruction Three machine cycles: Opcode fetch - 4T Direct addressing Memory read - 3T lOwite — -_oT 107 Total number of instructions = 4 ‘Note: In an 8085 procesorbased system when the 10 devices are mappedly 10 mapping han la Protaaar can communicate with these IO devices only by using IN and OUT instructions, ‘The processor uses an 8-bit address to select JO-mapped 10 devices With &-it address the processor can generate 2° 256,10 adahcse, 2.8 ARITHMETIC INSTRUCTIONS 1. ADD reg (A) (A) + (reg) The content ofthe register is added tothe content of the accumulator (Aregistey. Afler edition the result i stored in tha ‘accumulator All flags are affected. The register can be any one ofthe general purpose register A,B, C.D, E, Hor Example : ADD E (A)<— (A) + &) The content of the E-register is added to the content of the,A-register The result will be in the A-register. All flags are affected, Before execution Addition After execution A C2, = 1100 0010 E c2] 7A BB = BB, = 1011 1000 fl PF 0 AF Sum = 0111 1010= is ZF Cany=1 a Mie (Addition is performed in ALU) One byte instruction One machine cycle: Opcode fetch - 4T Register addressing Total number of instructions = 7 ADDA ADDB ADDC ADDD ADDE _—ADDH ADDL 2 ADIs (A) (A) + dB The 8-bit data given in the instruction is added othe content of the A-reister (Accumulator). After adtion, the result is stored ‘in the accumulator, All flags are affected. Two byte instruction Two machine cycles: Opcode fetch - 4T Immediate addressing Memory read - z Total number of instructions = 1 3% ADD M (Ac (A)+(M) or (A) (A) + (HL)) The content of memory addressed by HL.pai is edded (othe content of theAegiser. After addition, the result is stored inthe A-register, All flags are affected.= Ne +H) Example: ADD M aye (aye) sxample Abe 4, mn a " a snaroy Iocation oa oe tte canentof here The result Pu ech ay, re cab fter execution focation Ct 7 The content of the memory eam ; —_ secution al ‘44, = 0100 0100 a] a A_ _HL_ Memory "i 04) lo, 4] [ooo] frafcooa) 7a, = o11t 00tt CF = Sone CF = 0 [ra}coB oI O11 Bp ee aor loge Pr = 0 [2140000 | on = B7 AF = 0 ee ZF = 0 ree (Addition is performed in ALU) SFI DH SF = 0 Opcode fetch - 4T (ne byte instruction Two machine cycles ove a Register indirect addressing 7 x Total number of instructions = 1 4 acids (A) < (A) + d8 + CF The bt date given in the instruction and the cary lag (the value of carry flag before executing this instruction) are ads {othe content ofthe A-regster (Accumulator). After addition, the result is stored in the accumulator All flags are affected. Two byte instruction Two machine cycles : Opcode fetch - 4T Immediate addressing Memory read - 3T Total number of instructions = 1 = H3085 Microprocessor and Its Applications 9557 One byte instruction Register addressing Total number of instructions = 7 ADCA ADCB ADCG ~— Adc One machine cycle : Opcode fetch -4T ADCE ADCH ADCL 6 | ADC M (A) CUA)+ (M+ CF or (A) — (A)+ (HL) + CF The content ofthe memory adaressed by the HL. pir and th oe auded tothe content of register. fer adaton theres eto teh 9 batons oxeutg this instructonare ‘on, the result is stored in the A-register. All fags are affected, ‘One byte instruction ‘Two machine cycles: Opcodefetch - 47 Register inditect addressing Memory read - 37 7 Total number of instructions = Fos en SUB 00 (A) < (A) ~ (reg) The content ofthe register is subtracted from the content of the accumulator(A-register). After subtraction the result is stored in the A-register. All flags are affected. The register can be any one of the general purpose registerA, B, C, D, E, Hor L. Result =38,, CF =0 Examp) SUB C () © (A)- (0) The content of the C-register is subtracted fromA-register. The result will be in the A-register Casei Before execution Subtraction C4, = 11000100 89,,= 1000 1001 1's complementof 89,, 2's complement of 89, sort o111=77, C4, =1100 0100 c 477, =0111 O11 £2, [a ]0011 1011 ° convene’ 3B o a o o o -— ON an oa Case li Subtraction Before execution 89,,= 1000 1001 64,,= 11000100 41's complement of C4,,= 0011 1011 2's complementof C4, =0011 1011 +1 =0011 1100=36,,Chapter 2_ Instruction Set Of yy, Case Ii continued . ‘Subtraction | | | | | ‘After exeeulon 89, = 1000 1001 A cs] |= (ee +90,5:0011 1100 OF 1 [o]1100 0101 PE = 1 conpiemont TCS cy ‘cary a) SF = 1 Result=C5,, cF_st foie: 2’s complement of C5, ~ 3By i fon. But after subtraction, it will complement Tote: The 8085 microprocessor performs 2's complement subtraction. But after subh he carp alone. In 2s complement subtraction, if CF =1, then the result is positive and if CF =O, then the result ements the carry after subtraction, here if CF = 0, then the results positive and tive. Since, the 8085 processor compl raction, here if ver 4; then te result is negative. Ifthe result i negative, then it will be in 2 complement form, ‘One machine cycle: Opcode fetch - 4T One byte instruction Register addressing Total number of instructions = 7 suBA SUBB SUBC SUBD SUBE SUBH SUB L a SUldé (A) © (A)- a8 ‘The B-bit date given in the instruction is subtracted from the A-register (accumulator). After subtraction, the result is sed in the A-register. All flags are affected. Two byte instruction Two machine cycles : Opcode fetch - 4T Immediate addressing Memory read ~_3T 7 Total number of instructions = 4 9 SUBM (A) <(A)-(M) or (A) (A) - ((HL)) The content ofthe memory addressed by the HL pair is subtracted f regi soe Lis eens from the A-register. After subtraction, the resutt ss One byte instruction Two machine cycles : Opcode fetch - 4T Register indirect addressing Memory read - 3 7 Total number of instructions = 4 10. SBB reg (A) (A) - (reg) - CF The content of the register and the value of carry accumulator (A-register) After subtraction, the result is sto any one of the general purpose register A, B, C, D, E, Hor, (before executing this instruct a ion) are subtracted fo! red nth accumultoc Al gear fected, The retro (One byte instruction One machine cycl lo: : Register addressing oo Total number of instructions = 7 SBBA__SBBB_ SBBC SBBD _SBBE SBBH SBBL8085 Microprocessor and Its Applications 2.33 a SBM, (A) < (A) = dB - CF The 8-bit dete given in the instruction and the value of cary (before executing this instruction) are subtracted from (reg) then the cany fag is reset or cleared (i.e, CF = 0) fi) (A) = (eg) then the zero flag is set (ie, 2F = 1). Example: CMP B (A) = (B) = Modify flags. Tho content ofthe B-registeris compared withthe accumulator. The comparison is perfomed by subtracting the conte, ofthe Bregter fom th content of he accumultoc The subtraction is performed in the ALU and the result is used ‘modify the flags end then discarded. The content of the accumulator and the B-register are not altered, Before Comparison After execution execution AB C2,=1100 0010 AB 15] [Ca] 1'scomplement of C2,=0011 1101 15] [ca CF 0 2's complement of C2,,= 0011 110141 oF . PF = 0 =0 7 ind re 011 1110 = 3, PEo= 4 ZF 0 15,,=0001 0101 AF = 1 SF = 0 43E,,= 0011 1110 ZF = 0 Dor01 oo11 SE eu Cemyd 5 3 One byte instruction Reiter adtessng One machine cycle: Opcode fetch - 4T Tal numberof instructions = 7 CMPA CPB cupc CMP D cl i cnn MP E CMP H CMP L (A) - a8 if Tho 6-bidate given int = Mealy fags. Two byte instruction Immediate addressing TWo machine cyctes ; Opcode fetch Ich - 47 Memory read . Total numberof instructions = 4 OY read ~ aTMicroprocessor and Its Applications 2.41 085. The status of carry and zero fag after comparison are given below: ‘) (A) < (M) then the cany Nag is set (Le, CF= 1) ff) IF(A) > (M) then the carry fag is reset or cleared (1, CF = 0) = (M) then the zero flag is set (ie, ZF = 1) Example: CMP M Letthe content ofthe Hl. pair be CO5Q, Let the content of the memory loca ° ny location C05Q, be 7A, The content of the memory Iocetion C050, is compared with the content of theaccumulator. Only lags are altered. The content ofthe accumulator and the memory remains the same, Before A HL 25, = 00100101 AHL [25] [e050] TA,=0111 1010 [25] [C050] Memory 4'complement of 7A,= 10000101 Memory 7A] C050 2'complement of 7A,= 10000101 +1 7A] C050 10 = 1000 0110 =86,, 10 cr 25,,= 0010 0101 CF Pr ++86,,= 1000 0110 RE AF rE AF ZF (010 1011 ZF SF comey |) AB ae o One byte instruction Two machine cycles: Opcode ten : : i Register indirect addressing Manono - Total number of instructions = 1 8 oww a® (CMA - Complement Accumulator) tod. The conten ofthe accumulator is complemented. Noflags aro ae e ‘one machine cycle: Opcode fetch - One byte Instruction Implied addressing ste ene! (STC - Set Carry) The camy fag is set to 4. One byte instruction is this instruction. flag is affected by’ ed ine cycle: opcode fetch - 4T (Ono machiChapter 2_ Instruction Set oy yy, is We 15, CMC (cr) < (CF) (MC - Complement Carry) renee ms ence ny te cany fg is flected by 1S instruction ja struction ‘one machine cycle: opcode fetch «AT One byte ins Implied addressing i id (CF) addr16 Wf is TRUE then, (PC) < addris It1s conditional jump instruction. The conditional ump instruction wil check @ flag conlton the lag condition is tuo, then the eaaress given Inthe Intrcton Is moved fo the program counter Thus the program contol fs branched to tha jump ‘address. Ifthe flag condition is false, then the next insruction Is executed,2.44 Taree pt costononpinstisi ons ormemriet cirt6 MPN y= dup i 200 9 seats dump on ot Z2 se Bp abot Bon i ca fod = m0 nits pump on NO Cay iv) JNC a ump on Minus * slump it sig bales par ump on Positive ~ snp it ” pe addrts Jump on Paniy Even - raroeds a vii) 3PO addrt6. slump on Peri Odd - Three byte instruction Immediate addressing Two or three machine cycles: Condition False | Chapter 2_Instruction Sey, Oy | i Condition True Opcode fetch - 47 — Opcode fetch . Memory read - 3T = Memory read « 3¢ Memory read - 37 = 3. CALL addrt6 (SP) (SP)-1 5 (SP) <(SP)-1 (PC) < addrté itis uncondtional CALL used fo call @ subroutine program. When this instruction is executed, the address of the ret instruction inthe program counters pushed tothe stack. The 16-bit address (which isthe address of the subroutine program) get inthe instructions loaded in the program counter Now, the processor will start executing the instructions stored in this clades (SP) < (PO), (sP)) < (PC), Thee bye intueton Five machine cycles: Opcode fetch - 6T Inmediate stressing Memory read - 37 Memory read - 3T Memory write - 37 Memory write - 37 187. 4 Cécondition> —addrt6 4 is TRUE then, (SP) (9P) -4 (SP) < (SP) =4 (r+ ay (PC) « addrte (SP) — (Pc), itis conditional suboutn conditions on het el ecto, The cond instuton is lade inthe pees 8 "9H isiucton is poet =e tution wil check fora tag condone fog condone, then tao oo NOW ho processor ait, 2 S8CK and tho cal edérone sone given i Thora ian i et stun exec Ml 8 xceung the nace eae (ales ate wetadpcnntca ann tions stored in this ade 0 cz addrtg Meso ag : ae Calli zer0 tag 8 scar al, §) CNC addrie 5 cota in ¥) CW addts Cali eary Vi) CP addrig Calli: eh Wi) CPE adarts atta 8 vill) CPO addrig all if a flag Caparosssor and Its Applicati nf Microproce \pplications nat Three byte instruction Two or five machine cycies: Condition Fals Immediate addressing Sondiifon False Condition True Opcode fetch - 6T — Opcode fetch - 6T Memoryread - 3T — Memory read - ST “ Momoryread- <3 Memory write Memory write - las at (PC) (SP) 5 (SP) (SP)+4 (PC), (SP); (SP) (SP) +4 {RET - Return to the main program) tis an unconditional retum instruction. This instruction is placed atthe end of the subroutine program, in order to return to the main program. When this instruction is executed, the top of the stack is poped fo (loaded in) the program counter. Note: While calling the subroutine using CALL instruction, the return address ofthe main program is pushed tothe stack. The return instruction, (RET) pops that to the program counter. Thus the processor resumes the execution of| main program. One byte instruction Three machine cycles: Opcode fetch - 4T Register indirect addressing Memory read - 37 Memory read -_3T. ior, & ——_Recondition> If is TRUE then, (PC), — (SP); (SP) <-(SP)+1 (PC), <— (SP) 5 (SP) <—(SP)+1 Itis conditional return instruction. Ina conditional return instruction a flag condition is tested. Ifthe flag condition is true, then the program control retum to ‘main program by poping the top of the stack fo the program counter. Ifthe flag condition is false, then the next instruction is executed, There are eight conditional return instructions: ) RZ jReturn on Zero + Return if zero flag = 1. jl) RNZ Return on Not Zero - ‘Returnif zero flag = 0. ii) RC ;Retum on Cany = Return if camy flag = 1. iv) RNC ;Refum on No Cany —- Return if carry flag = 0. v) RM = Return ifsign flag = 1 vi) RP ;Retum on Positive ~ ‘Retumif sign flag = 0. vil) RPE Return on Parity Even - Return if pany fag = 1 vii) RPO ;Retun on Parity Odd - Return if party flag = ‘ ance iy One byte instruction ‘One or three machine cycles: Condition Fase Seton Ie Register indirect addressing Opcode fetch fi eh e Memory read - aT is [Chapter 2 Instruction Set Of gy oe software interrupts. Each restart instructic NAS a veg, ty 1 RSTn . ed itis reste instruction. The restart instructions rt et atress. Te vecoraaaress fixed by Re ‘manufacturer | Mr open conte stl te sock dt tr st, fon is executed, the content of the, yrocessor. The vecte Wen a restr istucion sr dress i intel generated camped presse The etre i loaded in tho Sr ye Ts th program onl branched toa subroutine prog} orate, mise és Three machine cycles: Opcode fetch - 2 ‘One byte instruc pear ee Register indirect addressing mais oT 120 There are eight restart ‘instructions. Rests RST6—RST7 psto. RST1.«—«RST2.—«—CRST3_—ORSTA tresses for he restart instructions are listed inthe table given below: The vector ad Restart Vector Computation of instruction address vector address RSTO 0000, Ox8= 0, = 0, RST1 0008, tx8= 8, = 6, sieke 0010, 2x8= 16, = 10, balk 0018, 3xB= 24, = 18, ey 0020, 4x8= 32, = 20, bald 0028, 5x8= 40, = 28, ~ a 6x8= 48, = 30, 7x8= 56, = 38, 8. PCHL PS The content of the HLregistr pairs prog "pair is moved to the in counter, the program control is transferrec ieee The ees ‘ ri mei is instruct ae a at artaredo aren ads. This insucton fs used by ta eaten ceeenet inser . One byte instruction ‘Implied addressing One machine cycle: Opcode fetch - ér 2.11 MACHINE Ci ONTROL INST) a RUCTIONS (Ol - Disable interrupts) ‘Processor wil not accept or tocessor i do recognize the intr TRAP a ois doing an emergency work, it can eee ‘mado by the ada abled. (When the interrupts are disabled ite One byte instruction instruction to prevent tho Caos Hugh the interrupt pins. Whe? interrupts from interrupting the process) 01 me machine cycle: Opcode fetch aT{085 Microprocessor and Its Applications 247 2 @ (El Enable Interrupts) This instruction is used (or executed) to allow th processor reset or afer execution of DI instruction. Wh One byte instruction 1 interrupts after disabling. (The interrupts except TRAP are disabled after ven We want fo allow the interrupts, we have to execute EI instructions.) One machine cycle: Opcode fetch - 47 3 OSIM (SIM - Set Interrupt Mask) The SIM instruction is used to mask the hardware interupts RST 7.5, RST 6.6 and RST 5.5. It is also used to send data through the SOD line. (SOD: Serial Output Data bin of the 8085 processor) The execution of SIM instruction uses the content of the ‘ccumulator to perform the following functions: ) Program the interrupt mask for the hardware interrupts RST 5.5, RST 6.5 and RST 7.5. ji) Reset the edge-triggered RST 7.5 input latch, ji) Load the SOD output latch The bis in the accumulator before execution ofthe SIM instruction are defined as shown inthe Fig. 2.12. D, | >, | DB, D {>| DB. | DB Serial Output paws) lien Mask for RST 5.5 Serial Output Enable: Interrupt Mask for RST 6.5 ‘Undefined Interrupt Mask for RST 7.5 Reset RST 7. eee Mask Set Enable Fig. 2.12 : Accumulator content before execution of SIM instruction. lithe mask set enable bit is sett 1" then tho interupt mask bits for RST 7.5, RST 6.5 and RST 5.5(D,, D, and 0,) are {Roanized and if itis *0° then these bits are not recognized by the processor. The infenupt mask bits D,, D, and D, can be ‘independently set to "1" fo mask the particular interrupt and reset to "0" to unmask the particular interrupt. "the bt Dis set to "1", then an intemal flip-flop is reset to "0" in order to alsable the RST 7.5 interupt. Ifthe serial output enable is “1, the serial output data is sent to the SODpin. One byte Instruction ‘One machine cycle: Opcode fetch - 47 4 RM (RIM - Read Interrupt Mask) The RIM instruction is used to check whether an interrupt Is masked or not. It is aso used to read data from the SID lina, vil Input Data pin of 8085 processor). When @ RIM instruction is executed, the accumulators loaded with 8-bit data, The 8-bi data inthe accumulator (content ‘f eccumulator) can be interpreted as shown in Fig. 2.13. Bits D, D, and D, provide the mask status ofthe RST 6, RST 65 and RST'7.6interupts respectively. tho mask bt ponding fo a particular RST fs "1", thon tho inerupt is masked and if th mask biti 0" thon the interrupt i : is unmasked, tbo interrpt enable it (0, is ‘0, the 8085's maskebointorupls ra csabled. Tho interrupts ae enabled i this biti 42, ‘4°1" in apariculariterupt pending bit indicates that an interupis being requested on th identified RST ine, When "N90. intorapt is waiting to belsorviced. Tho serial input data (bt D) indicat th valu ofthe signal at the SID pin, a One byte instruction ‘One machine cycle: Opcode fetch - 4T a (SID: Se bisChapter 2_ Instruction Set OF snr, 2.48 p,|v.] v.| >| D |B] r Interrupt Mask ee forRSTS.S is Interrupt Mask Interrupt Pending : Flag for RST 7.5 for RST 6.5 i Interrupt Mask Interrupt Pending Flag for RST 6.5 for RST 7.5, Interrupt Pending Interrupt Enable Flag Fisg fo BST 3 Fig. 2.13 : Accumulator. 5. (HLT - Halt program Execution) This instruction is placed at the end of the program. When this instruction is executed, the processor suspends progran execution and bus will be in idle state. (One byte instruction Two machine cycle: Opcode fetch - 3T Buside - 2 ar (NOP - No operation) The NOP/s a dummy instruction, it neither achieves any result nor affects any CPU registers. This is an useful instruction for producing software delay and reserve memory spaces for future software modifications. (One byte instruction ‘One machine cycle : Opcode fetch - 4T