Low-Cost 24-Bit Stereo Codec with

110 dB Signal-to-Noise Ratio

V4220

Description
V4220M is a high performance audio codec IC using delta-sigma ADC and DAC techniques, its applications include
digital effects processors, DAT, and multitrack recorders.
Its features are:
• 100 dB dynamic range A/D converters
• 100 dB dynamic range D/A converters
• 105 dB DAC signal-to-noise ratio
• Analog Volume Control
• Differential inputs / outputs
• On-chip Anti-aliasing and Output Smoothing Filters
• Selectable De-emphasis Filters for 32 k, 44.1 k and 48 kHz sample rates
• Package: SSOP28

Block Diagram and Pin Description

DIF1 DIF0 DEM1 DEM0

digital analog
PLA REG volume volume
control control

LOUT+
de- interpolation low pass
DIN data emphasis filter 4th ΣΔ filter
input LOUT-
interface de- interpolation low pass ROUT+
DTEST emphasis 4th ΣΔ
filter filter
ROUT-
ATEST1 test
logic
LIN+
decimator 4th ΣΔ
DOUT data filter LIN-
output
interface decimator 4th ΣΔ RIN+
filter
RIN-

On-chip
Timing Control bandgap
reference

XT1 SCLK LRCK RSTN

Function Description
V4220M is a high performance, 24-bit, stereo, audio codec IC that includes two channel ADC and two channel DAC.
The fourth-order delta-sigma A/D converters the analog input to the 24-bit serial outputs; the delta-sigma DAC
includes the interpolation filter, noise shaping modulator and low-pass smoothing filter.
The V4220M also includes a digital selectable de-emphasis filter for 32 k, 44.1 k and 48 k Hz sample rates;
an analog volume control architecture can make an 113.5 dB attenuation in 0.5 dB steps, which preserves dynamic
range during attenuation. The V4220M provides a serial interface to read/write the internal registers.

1
 V4220
Pin Configuration

NC 1 28 NC

XTO 2 27 RSTN

XTI 3 26 LOUT-

LRCK 4 25 LOUT+

SCLK 5 24 ROUT+

VD 6 23 ROUT-

DGND 7 22 AGND

DOUT 8 21 VA

DIN 9 20 LIN+

DIF1 10 19 LIN-

DIF0 11 18 DEM1

DEM0 12 17 RIN+

VL 13 16 RIN-

NC 14 15 NC

2
 V4220
Pin Description and Structure Scheme

Pin Symbol Function Attribute Structure Scheme

1 NC / /

2 XTO I/O

OSC Input/output

3 XTI I/O

4 LRCK Left/right clock I/O

5 SCLK Serial data clock I/O

6 VD Digital power
7 DGND Digital ground
8 DOUT Serial data output I/O
9 DIN Serial data input I/O

10 DIF1 (scl/cclk) Digital interface format I

11 DIF0 (sda/cdin) I/O

12 DEM0(ad0/cs)
De-emphasis select I
18 DEM1(I2C/SPI)

13 VL Digital logic power

14, 15 NC / /
16 RIN-
Differential right channel analog input I
17 RIN+
19 LIN-
Differential left channel analog input I
20 LIN+
21 VA Analog power
22 AGND Analog ground
23 ROUT-
Differential right channel analog output I/O
24 ROUT+
25 LOUT+
Differential left channel analog output I/O
26 LOUT-

27 RSTN Reset I

28 NC / /

3
 V4220
Electrical Characteristics
• Absolute Maximum Ratings
Unless otherwise specified, Tamb = 25 °C

Parameter Symbol Value Unit

Power Supplies VA,VD,VL -0.3~6 V
Power Supply Current Iall 90 mA
Power Dissipation PD 450 mW
Operating Temperature Tamb -40~85 °C
Storage Temperature Tstg -65~+150 °C

• Recommended Operating Conditions

Limit
Parameter Symbol Unit
Min Typ Max
Digital power VD 4.75 5.0 5.25 V
Analog power VA 4.75 5.0 5.25 V
Digital power VL 2.7 5.0 5.25 V

4
 V4220
• Electrical Characteristics
Unless otherwise specified, Tamb= 25°C, VA =VD =5 V

Test Conditions Specifications

Parameter Symbol Unit
/Comments Min Typ Max
DC Parameter
Power supply Current
VA Iva VL=5 V 46 60 mA
VD Ivd VL=5 V 9 20 mA
VL Ivl VL=5 V 3 5 mA
Analog input characteristics
Total harmonic distortion THD 0.003 %
ADC dynamic range 92 100 - dB
Total harmonic
THD+N Note 1 -92 -87 dB
distortion+noise
Full scale input voltage Differential 2.0 2.1 Vrms
Analog output characteristics
Total harmonic distortion THD 0.003 %
DAC dynamic range 92 100 - dB
DAC SNR SNR 97 105 dB
Attenuation step size 0.35 0.5 0.65 dB
Common mode output
2.4 V
voltage
Digital characteristics
Vih VL=5V 2.8 VL+0.3 V
High-level input voltage
Vil VL=3V 2.0 VL+0.3 V
Low-level input voltage Vil -0.3 0.8 V
High-level output voltage Vl-1 V
Low-level out voltage 0.5 V
Input leakage current Logic Inputs 10 μA
High Impedance
Output leakage current 10 μA
Logic Outputs

Note 1: referenced to typical full-scale differential input voltage(2 Vrms)

5
 V4220
Test Circuit
Test Circuit
DC Test Circuit
Test Circuit DC Test Circuit
• DC Test Circuit
0.1 uF + 1 uF
0.1 uF + 1 uF
VA VD
VA VD +2.7-5 V
150 MΩ VL +2.7-5 V
150 MΩ LIN+ VL 0.1 uF + 1 uF
2.2 nF LIN+ LOUT- 0.1 uF + 1 uF
2.2 nF LOUT-
15 MΩ
15 MΩ LIN- LOUT+

signal input
LIN- LOUT+

signal input
ROUT+
150 Ω ROUT+
150 Ω RIN+
2.2 nF RIN+ ROUT-
2.2 nF ROUT-
15 MΩ
15 MΩ RIN- DEM1 De-emphasis
RIN- DEM1 De-emphasis
DEM0 select
DEM0 select
Digital
Digital DIF1 V 4V24 22 02 M0 M
interface DIF1
interface
format DIF0 XTI external clock
format DIF0 XTI external clock
XTO
XTO
Reset RSTN
Reset RSTN SCLK
LRCKSCLK
NC LRCK
NC DIN
NC
NC DIN
NC DOUT
NC DOUT 47 kΩ
NC 47 kΩ
NC
AGND DGND
AGND
22
DGND
7
22 7

AC Test Circuit
AC Test Circuit
• AC Test Circuit +5 V
+5 V
Supply + 1 uF
Supply 2Ω 0.1 uF + 1 uF
2Ω 0.1 uF
VA VD
150 Ω VA VD +2.7-5 V
150 Ω
+

Input LIN+ VL +2.7-5 V

+

Input LIN+ VL 0.1 uF

10uF 2.2 nF + 1 uF
10uF 2.2 nF 0.1 uF + 1 uF
+ LIN-
+ LIN- LOUT-
4.7uF 0.1uF LOUT- analog
4.7uF 0.1uF LOUT+ analog
filter
150 Ω LOUT+ filter
150 Ω ROUT+ analog
+

Input RIN+ ROUT+ analog

+

Input RIN+ filter

10uF 2.2 nF ROUT- filter
10uF 2.2 nF ROUT-
+ RIN- DEM1 De-emphasis
+ RIN- DEM1 De-emphasis
4.7uF 0.1uF DEM0 select
4.7uF 0.1uF DEM0 select
Digital
Digital
DIF1 V 4V 24 22 02 M0M
interface DIF1
interface
format DIF0 XTI external clock
format DIF0 XTI external clock
XTO
XTO
Reset RSTN
Reset RSTN Rs
SCLK Rs
SCLK Rs Audio
NC LRCK Rs Audio
LRCK Rs
NCNC DIN Rs DSP
NC DIN Rs DSP
NC DOUT Rs
NC DOUT
NC
NC
AGND DGND 47 kΩ
AGND DGND 47 kΩ
22 7
22 7

6
 V4220
Characteristics Curve Characteristics Curve
0
-10
-20
-30
-40
-50
-60
dB
-70
-80
-90
-100
-110
-120
-130
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Normalized Frequency (Fs)
ADC Filter Response

0
-10
-20
-30
-40
-50
-60
dB -70
-80
-90
-100
-110
-120
-130
-140
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Normalized Frequency (Fs)
DAC Filter Response

7
 V4220
Timing Sequence and Port Operating Description
• Digital Interface Format

DIF1 DIF0 Digital Interface Format (Input)

00(default) Format 1: I2S, up to 24-bit data
01 Format 2: Left justified, up to 24-bit data
10 Format 3: Right justified, 24-bit Data
11 Format 4: Right justified, 20-bit Data

Serial data format 00:

Serial data format 00:
Left
Left Channel
Channel Right
Right Channel
Channel
LRCK
LRCK

SCLK
SCLK

SDATA
SDATA MSB
MSB -1
-1 -2
-2 -3
-3 -4
-4 -5
-5 +5
+5 +4
+4 +3
+3 +2
+2 +1
+1 LSB
LSB MSB
MSB -1
-1 -2
-2 -3
-3 -4
-4 +5
+5 +4
+4 +3
+3 +2
+2 +1
+1 LSB
LSB

Master Slave
I2S, up to 24-bit data I2S, up to 24-bit data
XTI=256, 384, 512 Fs XTI=256, 384, 512 Fs
LRCK=4 to 50 kHz LRCK=4 to 50 kHz
SCLK=64 Fs SCLK=48,64,128 Fs

Serial data format

Serial 01: 01:
data format

Left
Left Channel
Channel Right
Right Channel
Channel
LRCK
LRCK

SCLK
SCLK

SDATA
SDATA MSB
MSB -1
-1 -2
-2 -3
-3 -4
-4 -5
-5 +5
+5 +4
+4 +3
+3 +2
+2 +1
+1 LSB
LSB MSB
MSB -1
-1 -2
-2 -3
-3 -4
-4 +5
+5 +4
+4 +3
+3 +2
+2 +1
+1 LSB
LSB

Master Slave
Left-justified, up to 24-bit data Left-justified, up to 24-bit data
XTI=256,384,512 Fs XTI=256,384,512 Fs
LRCK=4 to 50 kHz LRCK=4 to 50 kHz
SCLK=64 Fs SCLK=48,64,128 Fs

Serial data format 10:

LRCK
LRCK Left Right
Right Channel
Channel
Left Channel
Channel

SCLK
SCLK

SDATA
SDATA 0
0 23 22
23 22 21 20
21 20 19 18
19 18 7
7 6
6 5
5 4
4 3
3 2
2 1
1 0
0 23 22
23 22 21 20
21 20 19 18
19 18 7
7 6
6 5
5 4
4 3
3 2
2 1
1 0
0

Serial data format 11:

8
LRCK
LRCK Left Right
Right Channel
Channel
Left Channel
Channel
 V4220
Serial data
Serialformat 10: 10:
data format
Serial data format 10:
LRCK Left Channel Right Channel

LRCK Left Channel Right Channel

SCLK
SCLK
SDATA 0 23 22 21 20 19 18 7 6 5 4 3 2 1 0 23 22 21 20 19 18 7 6 5 4 3 2 1 0

SDATA 0 23 22 21 20 19 18 7 6 5 4 3 2 1 0 23 22 21 20 19 18 7 6 5 4 3 2 1 0

Master Slave
Right-justified, 24-bit data Right-justified, 24-bit data
XTI=256,384,512 Fs XTI=256,384,512 Fs
LRCK=4 to 50 kHz LRCK=4 to 50 Hz
SCLK=64 Fs SCLK=64 Fs

Serial data format 11:

Serial data format 11:
Serial data format 11:
LRCK Left Channel Right Channel

LRCK Right Channel

SCLK Left Channel

SCLK
SDATA 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SDATA 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Master Slave
Right-justified, 20-bit data Right-justified, 20-bit data
XTI=256,384,512 Fs XTI=256,384,512 Fs
LRCK=4 to 50 kHz LRCK=4 to 50 Hz
SCLK=64 Fs SCLK=64 Fs

• Control port timing

• SPI mode
In SPI mode, CS is the V4220M chip select signal, CCLK is the control port bit clock, CDIN is the input data line from
the micro controller and the chip address is 0010000, all the signal are input and data is clocked in on the rising edge
of CCLK.
Figure behind shows the operation of the control port in SPI mode. To write to a register, bring CS low. The first 7 bits
on CDIN form the chip address, and must be 001000. The eighth bit is a read/write indicator, which must be low to
write. Register reading from the V4220M is not supported in SPI model The next 8 bits form the Memory address
Pointer(MAP), which is set to the address of the register that is to be updated. The next 8 bits are the data which will
be placed into a register designated by the MAP.
The V4220M has a MAP auto increment capability, enabled by he INCR bit in the MAP register. If INCR is a zero, then
MAP will stay constant for successive writes. If INCR is set to a 1, then MAP will auto increment after each byte is
written, allowing block writes of successive registers. Register reading from V4220M is not supported in the SPI
mode.

CS

CCLK
CHIP
ADDRESS MAP DATA
CDIN 0010000 R/W MSB LSB
byte 1 byte n
MAP = Memory Address Pointer

9
 byte 1 byte n
MAP = Memory Address Pointer

V4220
• I2C mode
In I2C mode, SDA is a bi-directional data line. Data is clocked into and out of the part by the clock, SCL, with the clock
to data relationship as shown in the following figure. There is no CS pin. Pin ad0 form s the partial chip address and
should be tied to VDD or DGND as desired. The upper 6 bits of the 7 bit address field must be 001000. In order to
communicate with the V4220M, the LSB of the chip address field(first byte sent to the V4220M)should match the
setting of the ad0 pin. The eighth bit of the address byte is the read/write bit(high for a read, low for a write). If the
operation is a write, the next byte is the memory address pointer which selects the register to be read/write. If the
operation is a read, the contents of the register pointed to by the memory address pointer will be output. Setting the
auto increment bit in MAP, allows successive reads or writes of consecutive registers. Each byte is separated by an
acknowledge bit.

SDA 001000 ADDR R/W ACK DATA 1-8 ACK DATA 1-8 ACK
AD0

SCL
Start Stop

Typical Circuit
Typical Application Application Circuit and Information
and Information

ferrite bead
+5V
Supply + 1uF 0.1uF 2Ω 0.1uF + 1uF
216
VA VD
150 Ω 20 LIN+ VL 13 +2.7-5V
2.2nF 0.1 uF + 1 uF
150 Ω 19
LIN-
signal input

LOUT- 25
analog
LOUT+ 26
150 Ω filter
17 24
RIN+ ROUT+ analog
2.2nF 23 filter
ROUT-
150 Ω 16 18
RIN- DEM1 De-emphasis
DEM0 12 select
V4 2 2 0 M
10 3
Digital DIF1 XTI external clock
interface 2 40 pF Eliminate the crystal
11 DIF0
format XTO and capacitors when
using an external
40 pF clock input
27
Reset RSTN 5 Rs
SCLK
4 Rs Audio Rs=500 Ω
1 NC LRCK
9 Rs Required for
14 NC DIN DSP Master mode
8 Rs
15
NC DOUT only
28 NC 47 kΩ
AGND DGND
227

10
 V4220
• Input buffer Input buffer
Input buffer LIN-
10 k 10 k
LIN-
LEFT 10 uF 20 k 10 k 10 k 10 k
ANALOG
+ uF
LEFT 10
INPUT 20 k LIN+
ANALOG 10 k
INPUT +
LIN+
RIN-
10 k 10 k
RIN-
RIGHT 10 uF 20 k 10 k 10 k 10 k
ANALOG
+ uF
RIGHT 10
INPUT 20 k RIN+
ANALOG 10 k
INPUT +
10 k RIN+
VA
+
8.25 k 10 k
47 uF + 0.1 uF VA
8.25 k
47 uF 0.1 uF
Optional Input Buffer
Output buffer Optional Input Buffer
• Output buffer
Output buffer 14 kΩ
14 kΩ 220 pF
14 kΩ 3.24 kΩ 220 pF
OUT-
14 kΩ 3.24 kΩ
OUT- 1000 pF
14 kΩ 1000 pF 3.24 kΩ
OUT+
14 kΩ 3.24 kΩ
OUT+ 1000 pF 14 kΩ 220 pF
1000 pF 14 kΩ 220 pF
2-Pole Butterworth Filter
2-Pole Butterworth Filter

• Applications Information
Master mode and slave mode:
The V4220M may be operated in either master mode or slave mode. In master mode, SCLK and LRCK are outputs
which generated by inner circuit. The V4220M will operate in master mode when a 47kΩ pulldown resistor is present
on DOUT at startup or after reset, see application circuit. LRCK and SCLK are inputs to the V4220M when operating in
slave mode, see the available clocking modes.

11