Ain Shams University

Faculty of Engineering
Computer & Systems Eng. Dept.

CSE 311s – Computer Architecture 2023-2024

Memories Sheet
1. A set-associative cache consists of 64 lines, or slots, divided into four-line sets. Main
memory contains 4K blocks of 128 words each. Show the format of main memory
addresses.

2. A two-way set-associative cache has lines of 16 bytes and a total size of 8 KB. The 64-
Mbyte main memory is byte addressable. Show the format of main memory addresses.

3.

4. For given problem,

a. Which references exhibit temporal locality?

b. Which references exhibit spatial locality?
Ain Shams University
Faculty of Engineering
Computer & Systems Eng. Dept.

5.

6. For a direct-mapped cache design with a 32-bit address and byte-addressable memory,
the following bits of the address are used to access the cache:

a. What is the cache line size (in words)?

b. How many entries (cache lines) does the cache have? Cache lines are also called
blocks.

7. Recall that we have two write policies and write allocation policies, and their
combinations can be implemented either in L1 or L2 cache. Assume the following
choices for L1 and L2 caches:

a. Buffers are employed between different levels of memory hierarchy to reduce

access latency. For this given configuration, list the possible buffers needed
between L1 and L2 caches, as well as L2 cache and memory.
b. Describe the procedure of handling an L2 write-miss, considering the
component involved and the possibility of replacing a dirty block.

8. A Virtual memory system has a 32-bit virtual address, 4 KB pages, and 4 bytes per page
table entry. Compute the total page table size.