CPIT210 : Computer Organization and Architecture Chapter 4: Cache Memory Tutorial

T.A. Khalid Alharbi

Department of Information Technology Faculty of Computing and Information Technology King Abdulaziz University

Problems: 4.8 Consider a machine with a byte addressable main memory of 216 bytes and block size of 8 bytes. Assume that a direct mapped cache consisting of 32 lines is used with this machine. A. How is a 16-bit memory address divided into tag, line number, and byte number? Block size = 8 bytes ) 3 bits are used for byte offset. 32 cache lines ) 5 bits are used as index bits. Remaining 16-(5+3) = 8 bits are used as tag bits. Tag 8 Line 5 Bytes 3

B. Into what line would bytes with each of the following addresses be stored? 0001 0001 0001 1011 1100 0011 0011 0100 1101 0000 0001 1101 1010 1010 1010 1010 Index bits (3-7) specify the cache line. The above addresses are stored in line 3, line 6, line 3, and line 21 respectively. C. Suppose the byte with address 0001 1010 0001 1010 is stored in the cache. What are addresses of the other bytes stored along with it? The tag and index bits of other addresses should match. Other addresses include: 0001 1010 0001 1xyz where x, y, and z can be 0 or 1. D. How many total bytes of memory can be stored in the cache? 32 lines 8 bytes/line = 256 bytes. E. Why is the tag also stored in the cache? Several addresses map to the same cache line. Tags help in identifying addresses in a line uniquely.( The tags are used to distinguish between possible entries in a cache line ).

4.4 List the following values: a) For the direct cache example of Figure 4.8: address length, number of addressable units, block size, number of blocks in main memory, number of lines in cache, size of tag. Address length: 24 bits Addressable units: 224 Block size: 4 words Blocks in main memory: 222 Lines in cache: 214 Size of tag: 8 b) For the associative cache example of Figure 4.10: address length, number of addressable units, block size, number of blocks in main memory, number of lines in cache, size of tag. Address length: 24 bits Addressable units: 224 Block size: 4 words Blocks in main memory: 222 Lines in cache: 214 Size of tag: 22 c) For the two-way set associative cache example of Figure 4.12: address length, number of addressable units, block size, number of blocks in main memory, number of lines in set, number of sets, number of lines in cache, size of tag. Address length: 24 bits Addressable units: 224 Block size: 4 words Blocks in main memory: 222 Lines in set: 2 Number of sets: 213 Lines in cache: 214 Size of tag: 9

4.3) For the hexadecimal main memory addresses 111111, 666666, BBBBBB, show the following information in hexadecimal format: a) Tag, Line, and Word values for a direct-mapped cache, using the format of Figure 4.8. b) Tag and Word values for an associative cache, using the format of Figure 4.10. c) Tag, Set and Word values for a two-way set associative cache, using the format of Figure 4.12.

Hex Address Binary Address a. T, L, W in Binary a. T, L, W in Hex b. T and W in Binary b. T and W in Hex c. T, S, W in Binary c. T, S, W in Hex

111111

666666

BBBBBB

0001 0001 0001 0001 0001 0001

0110 0110 0110 0110 0110 0110

1011 1011 1011 1011 1011 1011

00010001 00010001000100 01

01100110 01100110011001 10

10111011 10111011101110 11

11 0444 1

66 1999 2

BB 2EEE 3

0001000100010001000100 01

0110011001100110011001 10

1011101110111011101110 11

44444 1

199999 2

2EEEEE 3

000100010 0010001000100 01

011001100 1100110011001 10

101110111 0111011101110 11

22 444 1

CC 1999 2

177 1EEE 3

4.1) A set associative cache consists of 64 lines divided into four-line sets. Main memory contains 4K blocks of 128 words each. Show the format of memory addresses. The cache is divided into 16 sets of 4 lines each. Therefore, 4 bits are needed to identify the set number. Main memory consists of 4K = 212 blocks. Therefore, the set plus tag lengths must be 12 bits and therefore the tag length is 8 bits. Each block contains 128 words. Therefore, 7 bits are needed to specify the word. So, main memory address:

TAG 8

SET 4

WORD 7

4.2 ) A two-way set associative cache has lines of 16 bytes and a total size of 8 Kbytes. The 64-Mbyte main memory is byte-addressable. Show the format of main memory addresses. The cache size is 8 Kbytes and the line size is 16 Bytes and each set contains two lines ("two-way" means each set contains two cache lines). Therefore, Number of sets =((8 Kbytes / 16 Bytes) / 2 lines/set) =((213/24)/21)=28 = 256 Therefore 8 bits are needed to specify the set number. Each block contains 16 bytes. Therefore, 4 bits are needed to specify the Byte. Main memory size 64MB = 226 addressable units. Therefore, the address length must be 26 bits and the tag length is (26-(8+4))=14 bits. So, main memory address:

TAG 14

SET 8

Byte 4