Course Name & Code: Computer Architecture and Organization & CSE2001

Programme Name & Branch: B.Tech – CSE

Faculty: T Gopalakrishnan

Notes on Cache Memory solved problems

 Question : 3

A block-set associative cache memory consists of 128 blocks divided into four block sets
The main memory consists of 16,384 blocks and each block contains 256 eight bit
words.
a. How many bits are required for addressing the main memory?
b. How many bits are needed to represent the TAG, SET and WORD fields?
Solution-

Given-
 Number of blocks in cache memory = 128
 Number of blocks in each set of cache = 4
 Main memory size = 16384 blocks
 Block size = 256 bytes
 1 word = 8 bits = 1 byte
Main Memory Size-
We have-
Size of main memory
= 16384 blocks
= 16384 x 256 bytes
= 222 bytes
Thus, Number of bits required to address main memory = 22 bits

Number of Bits in Block Offset-

We have-
Block size
= 256 bytes
= 28 bytes
Thus, Number of bits in block offset or word = 8 bits

Number of Bits in Set Number-

Number of sets in cache

= Number of lines in cache / Set size
= 128 blocks / 4 blocks
= 32 sets
= 25 sets
Thus, Number of bits in set number = 5 bits

Number of Bits in Tag Number-

Number of bits in tag

= Number of bits in physical address – (Number of bits in set number + Number of bits in
word)
= 22 bits – (5 bits + 8 bits)
= 22 bits – 13 bits
= 9 bits
Thus, Number of bits in tag = 9 bits

Thus, physical address is-

Question :No : 4

A computer has a 256 KB, 4-way set associative, write back data cache with block size
of 32 bytes. The processor sends 32 bit addresses to the cache controller. Each cache
tag directory entry contains in addition to address tag, 2 valid bits, 1 modified bit and 1
replacement bit.

a) Select he number of bits in the tag field of an address is-

a. 11
b. 14
c. 16
d. 27
b) Select The size of the cache tag directory is-

a. 160 Kbits
b. 136 Kbits
c. 40 Kbits
d. 32 Kbits

Solution-
 Given-
 Cache memory size = 256 KB
 Set size = 4 blocks
 Block size = 32 bytes
 Number of bits in physical address = 32 bits

Number of Bits in Block Offset-

We have-
Block size
= 32 bytes
= 25 bytes
Thus, Number of bits in block offset = 5 bits

Number of Lines in Cache-

Number of lines in cache

= Cache size / Line size
= 256 KB / 32 bytes
= 218 bytes / 25 bytes
= 213 lines
Thus, Number of lines in cache = 213 lines

Number of Sets in Cache-

Number of sets in cache

= Number of lines in cache / Set size
= 213 lines / 22 lines
= 211 sets
Thus, Number of bits in set number = 11 bits

Number of Bits in Tag-

 Number of bits in tag
= Number of bits in physical address – (Number of bits in set number + Number of bits in
block offset)
= 32 bits – (11 bits + 5 bits)
= 32 bits – 16 bits
= 16 bits
Thus, Number of bits in tag = 16 bits

Tag Directory Size-

Size of tag directory

= Number of lines in cache x Size of tag
= 213 x (16 bits + 2 valid bits + 1 modified bit + 1 replacement bit)
= 213 x 20 bits
= 163840 bits
= 20 KB or 160 Kbits

Thus,
 For part-01, Option (C) is correct.
 For part-02, Option (A) is correct.

Question No 5:
Consider a fully associative mapped cache of size 16 KB with block size 256 bytes. The
size of main memory is 128 KB. Find-
a. Number of bits in tag
b. Tag directory size

Solution-
Given-
 Cache memory size = 16 KB
 Block size = Frame size = Line size = 256 bytes
 Main memory size = 128 KB
We consider that the memory is byte addressable.
Number of Bits in Physical Address-

We have,
Size of main memory
= 128 KB
= 217 bytes
Thus, Number of bits in physical address = 17 bits

Number of Bits in Block Offset-

We have,
Block size
= 256 bytes
= 28 bytes
Thus, Number of bits in block offset = 8 bits

Number of Bits in Block Offset-

We have,
Block size
= 256 bytes
= 28 bytes
Thus, Number of bits in block offset = 8 bits
Number of Bits in Tag-

Number of bits in tag

= Number of bits in physical address – Number of bits in block offset
= 17 bits – 8 bits
= 9 bits
Thus, Number of bits in tag = 9 bits

Number of Lines in Cache-

Total number of lines in cache

= Cache size / Line size
= 16 KB / 256 bytes
= 214 bytes / 28 bytes
= 26 lines

Tag Directory Size-

Tag directory size

= Number of tags x Tag size
= Number of lines in cache x Number of bits in tag
= 26 x 9 bits
= 576 bits
= 72 bytes
Thus, size of tag directory = 72 bytes

Question No :6
 Consider a 2-way set associative mapped cache of size 16 KB with block size 256 bytes.
The size of main memory is 128 KB. Find-
1. Number of bits in tag
2. Tag directory size

Solution-

Given-
 Set size = 2
 Cache memory size = 16 KB
 Block size = Frame size = Line size = 256 bytes
 Main memory size = 128 KB

We consider that the memory is byte addressable.

Number of Bits in Physical Address-

We have,
Size of main memory
= 128 KB
= 217 bytes
Thus, Number of bits in physical address = 17 bits

Number of Bits in Block Offset-

We have,
Block size
= 256 bytes
= 28 bytes
Thus, Number of bits in block offset = 8 bits
Number of Lines in Cache-

Total number of lines in cache

= Cache size / Line size
= 16 KB / 256 bytes
= 214 bytes / 28 bytes
= 64 lines
Thus, Number of lines in cache = 64 lines

Number of Sets in Cache-

Total number of sets in cache

= Total number of lines in cache / Set size
= 64 / 2
= 32 sets
= 25 sets
Thus, Number of bits in set number = 5 bits
 Number of Bits in Tag-

Number of bits in tag

= Number of bits in physical address – (Number of bits in set number + Number of bits in
block offset)
= 17 bits – (5 bits + 8 bits)
= 17 bits – 13 bits
= 4 bits
Thus, Number of bits in tag = 4 bits

Tag Directory Size-

Tag directory size

= Number of tags x Tag size
= Number of lines in cache x Number of bits in tag
= 64 x 4 bits
= 256 bits
= 32 bytes
Thus, size of tag directory = 32 bytes

Question No :7
Consider a 4-way set associative mapped cache with block size 4 KB. The size of main
memory is 16 GB and there are 10 bits in the tag. Find-
1. Size of cache memory
2. Tag directory size

Solution-
 Given-
 Set size = 4
 Block size = Frame size = Line size = 4 KB
 Main memory size = 16 GB
 Number of bits in tag = 10 bits

We consider that the memory is byte addressable.

Number of Bits in Physical Address-

We have,
Size of main memory
= 16 GB
= 234 bytes
Thus, Number of bits in physical address = 34 bits

Number of Bits in Block Offset-

We have,
Block size
= 4 KB
= 212 bytes
Thus, Number of bits in block offset = 12 bits

Number of Bits in Set Number-

Number of bits in set number
= Number of bits in physical address – (Number of bits in tag + Number of bits in block
offset)
= 34 bits – (10 bits + 12 bits)
= 34 bits – 22 bits
= 12 bits
Thus, Number of bits in set number = 12 bits

Number of Sets in Cache-

We have-
Number of bits in set number = 12 bits
Thus, Total number of sets in cache = 212 sets

Number of Lines in Cache-

We have-
Total number of sets in cache = 212 sets
Each set contains 4 lines

Thus,
Total number of lines in cache
= Total number of sets in cache x Number of lines in each set
= 212 x 4 lines
= 214 lines

Size of Cache Memory-

Size of cache memory

= Total number of lines in cache x Line size
= 214 x 4 KB
= 216 KB
= 64 MB
Thus, Size of cache memory = 64 MB
Tag Directory Size-

Tag directory size

= Number of tags x Tag size
= Number of lines in cache x Number of bits in tag
= 214 x 10 bits
= 163840 bits
= 20480 bytes
= 20 KB
Thus, size of tag directory = 20 KB

Question No :8
Assume a byte-addressable main memory consists of 2^14 bytes, cache has 16 blocks, and each
block has 8 bytes.

Question No:9:
Question No 10:
Question No :11

Question No :12
A set-associative cache consists of 64 lines, or slots, divided into four-line sets. Main memory
contains 4K blocks of 128 words each. Show the format of main memory addresses
 Question No :13
A two-way set-associative cache has lines of 16 bytes and a total size of 8 kbytes. The 64-Mbyte
main memory is byte addressable. Show the format of main memory addresses.

Solution

Question No :14
Consider a 4-way set associative mapping with 16 cache blocks. The memory block
requests are in the order-
0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155
If LRU replacement policy is used, which cache block will not be present in the cache?
1. 3
2. 8
3. 129
4. 216
Also, calculate the hit ratio and miss ratio.

Solution-

We have,
 There are 16 blocks in cache memory numbered from 0 to 15.
 Each set contains 4 cache lines.
 In set associative mapping, a particular block of main memory is mapped to a
particular set of cache memory.
 The set number is given by-
Cache line number = Block address modulo Number of sets in cache
 For the given sequence-
 Requests for memory blocks are generated one by one.
 The set number of the block is calculated using the above relation.
 Within that set, the block is placed in any freely available cache line.
 If all the blocks are already occupied, then one of the block is replaced in accordance
with the employed replacement policy.

Thus,
 Out of given options, only block-216 is not present in the main memory.
 Option-(D) is correct.
 Hit ratio = 1 / 17
 Miss ratio = 16 / 17

Question 15:

Consider a machine with a byte addressable main memory of 216 bytes and block size of 8 bytes.
Assume that a direct mapped cache consisting of 32 lines is used with this machine.

a. How is a 16-bit memory address divided into tag, line number, and byte number
b. b. Into what line would bytes with each of the f
 0001 0001 0001 1011
 1100 0011 0011 0100
 1101 0000 0001 1101
 1010 1010 1010 1010

Solution a:

Solution b:

Line 3.

Line 6.

Line 3.

Line 21.

Question 16:
Consider a memory system that uses a 32-bit address to address at the byte level, plus a cache
that uses a 64-byte line size.

a. Assume a direct mapped cache with a tag field in the address of 20 bits. Show the address
format and determine the following parameters: number of addressable units, number of blocks
in main memory, number of
b. Assume an associative cache. Show the address format and determine the following
parameters: number of addressable units, number of blocks in main memory, number of lines in
cache, size of tag.

c. Assume a four-way set-associative cache with a tag field in the address of 9 bits. Show the
address format and determine the following parameters: number of addressable units,
number of blocks in main memory, number of lines in set, number of sets in cache, number of
lines in cache, size of tag.

Solution :

Question No 17:
Consider a computer with the following characteristics: total of 1Mbyte of main memory; word
size of 1 byte; block size of 16 bytes; and cache size of 64 Kbytes.

a. For the main memory addresses of F0010, 01234, and CABBE, give the corresponding tag,
cache line address, and word offsets for a directmapped cache.
b. Give any two main memory addresses with different tags that map to the same cache slot for
a direct-mapped cache.
c. For the main memory addresses of F0010 and CABBE, give the corresponding tag and offset
values for a fully-associative cache.
d. For the main memory addresses of F0010 and CABBE, give the corresponding tag, cache set,
and offset values for a two-way set-associative cache.

Solution a:

Solution b:
Solution C:

Solution d:
 Cache Performance based problems

Question No 1:
A computer system has a MM access time of 200 ns supported by a cache having a 10 ns
access time and a hit rate of 99%.

Solution :

Suppose access to cache and main memory occurs concurrently. (The accesses overlap.)

The EAT is: 0.99(10 ns) + 0.01(200 ns) = 9.9 ns + 2 ns = 11 ns.

Question No 2:

Suppose a single cache fronting a main memory, which has 80 nanosecond access time.

Suppose the cache memory has access time 10 nanoseconds.

If the hit rate is 90%, then TE = 0.9 · 10.0 + (1 – 0.9) · 80.0

` = 0.9 · 10.0 + 0.1 · 80.0 = 9.0 + 8.0 = 17.0 nsec.

If the hit rate is 99%, then TE = 0.99 · 10.0 + (1 – 0.99) · 80.0

` = 0.99 · 10.0 + 0.01 · 80.0 = 9.9 + 0.8 = 10.7 nsec.

Suppose a L1 cache with T1 = 4 nanoseconds and h1 = 0.9

Suppose a L2 cache with T2 = 10 nanoseconds and h2 = 0.99
This is defined to be the number of hits on references that are a miss at L1.
Suppose a main memory with TS = 80.0

TE = h1 · T1 + (1 – h1) · h2 · T2 + (1 – h1) · (1 – h2) · TS.

= 0.90 · 4.0 + 0.1 · 0.99 · 10.0 + 0.1 · 0.01 · 80.0
= 0.90 · 4.0 + 0.1 · 9.9 + 0.1 · 0.80
= 3.6 + 0.99 + 0.08 = 4.67 nanoseconds.

Note that with these hit rates, only 0.1 · 0.01 = 0.001 = 0.1% of the memory references are
handled by the much slower main memory